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29 commits

Author SHA1 Message Date
Olof Kindgren
c7fc57213c Avoid releasing trap signal too early 
The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.
 2023-10-31 22:21:12 +01:00
Olof Kindgren
2bb988b553 Add reset for mie_mtie 2022-02-09 18:15:08 +01:00
Olof Kindgren
d2a4243033 Add reset for new_irq register 2021-08-27 13:10:06 +02:00
Olof Kindgren
6fbdea58d6 Optimize trap handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
d5febe8f63 Simplify and document trap handling 2021-01-18 22:38:07 +01:00
Olof Kindgren
3751b58253 Clean up serv_csr interface 2020-11-10 15:16:19 +01:00
Olof Kindgren
3aa1a2c6e5 Simplify and document mstatus/mcause assignments 2020-08-26 16:45:40 +02:00
Olof Kindgren
fa6c420b10 Remove redundant mstatus register 2020-08-26 16:45:40 +02:00
Olof Kindgren
119473d506 Move CSR_SOURCE_ constants into serv_csr.v 2020-08-13 23:37:11 +02:00
Olof Kindgren
1d311edb7d Make counter internal in serv_state 2020-04-15 10:29:50 +02:00
Olof Kindgren
5aa1fbe709 Stop depending on run state 2019-12-08 22:51:28 +01:00
Olof Kindgren
40000cbeb9 Fix IRQ 
This contains a lot of fixes as IRQ support was broken on both
RTL and zephyr side

* Interrupts are now synced to instruction lifetimes
* Interrupts are disabled on traps and mie is pushed to mpie
* Zephyr applications regenerated from rewritten Zephyr port
* Timer is 32-bit to avoid wrapping around too often
* MEPC was not read properly from CSR storage
 2019-11-19 11:06:50 +01:00
Olof Kindgren
8bc54a99ad Move mcause generation to serv_csr 2019-09-26 23:36:02 +02:00
Olof Kindgren
1248043a39 Separate state and decode from CSR signals 2019-09-14 22:18:03 +02:00
Olof Kindgren
d2cf7e547a Interrupt refactoring 2019-08-25 22:47:29 +02:00
Olof Kindgren
16c93a58ee Move mepc and mtval into RF memory 2019-07-08 07:49:58 +02:00
Olof Kindgren
e107627e71 Reduce warnings 2019-06-24 15:22:08 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00
Olof Kindgren
3438e0f172 Optimize mcause CSR 2019-03-21 09:24:11 +01:00
Olof Kindgren
9a97c535bd Use ring buffer for counter LSBs 2019-01-15 08:00:32 +01:00
Olof Kindgren
45f6d408f8 Remove dead code 2019-01-15 08:00:32 +01:00
Olof Kindgren
813f9f4951 Rewrite CSR selection 2019-01-10 18:15:20 +01:00
Olof Kindgren
468e99ac7c Syntax fixes to please Quartus 2018-12-07 22:55:55 +01:00
Olof Kindgren
cd983190b3 Interrupts working. Adding philosophers example 2018-11-26 23:03:40 +01:00
Olof Kindgren
11a2195146 First attempt att interrupt support 2018-11-26 16:01:07 +01:00
Olof Kindgren
b8f5133267 Random optimizations 2018-11-23 13:59:07 +01:00
Olof Kindgren
f66f82a57a Add explicit wire defs to ports 2018-11-17 21:30:03 +01:00
Olof Kindgren
0036756157 Pass compliance tests 2018-11-15 14:16:01 +01:00
Olof Kindgren
a92c933af1 csr, verilator, traps 2018-11-14 12:16:20 +01:00