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Author SHA1 Message Date
AlAlves
2fb56ac62d Update serv_top.v 2019-07-08 07:47:12 +02:00
Olof Kindgren
e107627e71 Reduce warnings 2019-06-24 15:22:08 +02:00
Olof Kindgren
4b371c533f Add nexys a7 support 2019-06-24 13:18:34 +02:00
Olof Kindgren
fe9d2677ba Add SERV_CLEAR_RAM parameter 2019-06-24 13:18:34 +02:00
Olof Kindgren
70bdce9d8e Refactor gpio/uart output in tb 2019-06-24 13:18:34 +02:00
Olof Kindgren
bad78b0bd7 Declare wires before use 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00
Aliaksei Chapyzhenka
c91a5a43c1 Update README.md 2019-06-07 23:27:51 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00
Olof Kindgren
b0a062ae21 Speed up instruction fetching 2019-04-12 08:15:08 +02:00
Olof Kindgren
bba836ad8c Fix width mismatches to make code verilator clean 2019-03-25 20:57:13 +01:00
Olof Kindgren
3438e0f172 Optimize mcause CSR 2019-03-21 09:24:11 +01:00
Olof Kindgren
6e91409990 Optimize alu eq check 2019-03-20 08:35:43 +01:00
Olof Kindgren
a550137453 Use bufreg for shifter 2019-03-20 08:35:43 +01:00
Olof Kindgren
102936ba40 Add license file 2019-01-16 08:12:13 +01:00
Olof Kindgren
fe33d6abdc Move dbus address handling to global bufreg 2019-01-15 08:00:32 +01:00
Olof Kindgren
9a97c535bd Use ring buffer for counter LSBs 2019-01-15 08:00:32 +01:00
Olof Kindgren
215da65e82 Optimize serv_mem_if 2019-01-15 08:00:32 +01:00
Olof Kindgren
6f4c85f16d Optimize alu_sub control flag 2019-01-15 08:00:32 +01:00
Olof Kindgren
45f6d408f8 Remove dead code 2019-01-15 08:00:32 +01:00
Olof Kindgren
3a68cc0e77 Improve critical path in ctrl 2019-01-15 08:00:32 +01:00
Olof Kindgren
813f9f4951 Rewrite CSR selection 2019-01-10 18:15:20 +01:00
Olof Kindgren
f5a1590422 Remove duplicated adder+inverter 2019-01-10 18:15:20 +01:00
Olof Kindgren
ba79ffdf0b Prevent writes to x0 2019-01-10 18:15:20 +01:00
Olof Kindgren
8ae05ea4cf Rewrite immediate decoder 2018-12-25 13:13:04 +01:00
Olof Kindgren
78821c16b3 Optimize op_b selector 2018-12-25 13:13:04 +01:00
Olof Kindgren
e3e616903e Optimize bool operations 2018-12-25 13:13:04 +01:00
Olof Kindgren
1d04ed9c50 Fix errors in core file 2018-12-16 08:48:48 +01:00
Olof Kindgren
4a224fc985 Fix failing compliance tests 2018-12-13 12:03:42 +01:00
Olof Kindgren
3f5c25d8f2 Silence LSE warnings 2018-12-12 21:20:44 +01:00
Olof Kindgren
09bb05071e Fix bugs and missing resets to pass formal 2018-12-11 22:05:32 +01:00
Olof Kindgren
af1d4da8bf Fix rvfi logic 2018-12-11 22:02:03 +01:00
Olof Kindgren
f52eb1931d Add info about some of serv's shortcomings 2018-12-08 00:16:35 +01:00
Olof Kindgren
f627aee1a1 Syntax fixes to please Vivado 2018-12-07 23:20:47 +01:00
Olof Kindgren
468e99ac7c Syntax fixes to please Quartus 2018-12-07 22:55:55 +01:00
Olof Kindgren
6cd3d2d3ef Fix rvfi_insn 2018-12-06 23:47:52 +01:00
Olof Kindgren
836a013462 Fix clock generation 2018-12-06 22:12:03 +01:00
Olof Kindgren
b569d08d02 Update documentation 2018-12-05 19:36:14 +01:00
Olof Kindgren
fc82862e96 Add icepll generator and run tinyfpga BX at 32MHz 2018-12-03 12:26:17 +01:00
Olof Kindgren
16666c319e Update zephyr submodule 2018-11-26 23:17:21 +01:00
Olof Kindgren
7fabafa9cf Add sync example 2018-11-26 23:15:53 +01:00
Olof Kindgren
25791b10c2 Add memsize param to FPGA targets 2018-11-26 23:13:50 +01:00
Olof Kindgren
cd983190b3 Interrupts working. Adding philosophers example 2018-11-26 23:03:40 +01:00
Olof Kindgren
e1a883acc2 Add zephyr fork as submodule 2018-11-26 18:05:01 +01:00
Olof Kindgren
05640dfe30 Update README 2018-11-26 18:00:39 +01:00
Olof Kindgren
4649b7073f Update example applications 2018-11-26 18:00:29 +01:00
Olof Kindgren
ec8252ea0a Add memsize parameter 2018-11-26 17:54:10 +01:00
Olof Kindgren
11a2195146 First attempt att interrupt support 2018-11-26 16:01:07 +01:00
Olof Kindgren
12039dec0e Add support for setting memory contents during synthesis 2018-11-26 09:49:08 +01:00
Olof Kindgren
e1f5bcc4f3 Rewrite register file 2018-11-26 00:09:52 +01:00