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3076 commits 27 branches 9 tags 1.6 GiB
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57 commits

Author SHA1 Message Date
Blaise Tine
b634f9f47d count_leading_zeros fix 2024-09-28 20:15:03 -07:00
Blaise Tine
a9a5ded030 bitmanip logceil fix 2024-09-23 23:54:43 -07:00
Blaise Tine
a80be895ba fixed compiler errors 2024-09-23 03:05:46 -07:00
Blaise Tine
b8199decf4 opaesim and xrtsim multi-bank memory support 2024-09-22 03:54:40 -07:00
Blaise Tine
a37309c6b0 xrtsim implementation 2024-09-19 04:24:20 -07:00
tinebp
6c607d32fe
Merge pull request #169 from sij814/simx 
simx HBM initial implementation
 2024-08-17 20:24:37 -07:00
donghanyuan
1a9a04ac76 replace local static allocator to global static 
Ensure MemoryPool construct before SimPlatform,
thus MemoryPool destruct after SimPlatform.

Avoid use-after-free issue clearing events_ of SimPlatform
after SimPortEvent's allocator is destructed.
 2024-08-13 18:13:41 +08:00
sij814
47427ab22e regression test with source_id 0 2024-08-12 16:22:30 -07:00
sij814
bab9496117 debugging segmentation fault with 8 clusters 2024-08-12 03:52:48 -07:00
sij814
de81baaabf hbm for vortex 2.2 2024-08-12 02:52:47 -07:00
Blaise Tine
50b12ef754 fixed memory block size configuration 2024-08-06 12:46:19 -07:00
Blaise Tine
2bc8a881b6 fixed trace log formatting 2024-07-30 12:05:36 -07:00
Blaise Tine
60f7786e17 BitVector class bug fixes 2024-07-23 09:40:20 -07:00
Blaise Tine
95f59d23a8 simx memory coalescer bug fix 2024-07-23 00:02:43 -07:00
Blaise Tine
24e8e91a94 DramSim fix 2024-07-22 03:37:10 -07:00
Blaise Tine
fb141ae522 Ramulator 2.0 with HBM 2.0 support 
Verilator 5.0 support
SimX C++17 requirement
 2024-07-21 06:57:13 -07:00
Blaise Tine
99eaaf6189 uuid_gen cleanup 2024-06-08 01:57:38 -07:00
Blaise Tine
aea1d2c8eb minor updates to the build system 2024-04-30 16:27:20 -07:00
Blaise Tine
9df25ff48f minor update 2024-04-28 04:42:22 -07:00
Blaise Tine
db0f0fd353 runtime API refactoring to support memory reservation and protection 2024-04-28 04:23:00 -07:00
Blaise Tine
ac669a30ca UUID refactoring 2024-04-14 22:01:03 -07:00
Blaise Tine
840ced22a9 simx refactoring - emulation vs simulation discrete separation 2024-03-12 00:23:42 -07:00
Blaise Tine
ff6f33acff simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_ 2024-03-11 15:39:49 -07:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Blaise Tine
1bd25acb0b cmov 2022-02-05 17:58:12 -05:00
Santosh Srivatsan
b7e5a83ba3 Merged branch xlen-parameterization into staging 2022-02-05 13:47:42 -05:00
Blaise Tine
140124b423 additional bug fixes 2022-02-05 07:42:50 -05:00
Blaise Tine
5fbace9fa0 fixed several bugs and refactor memory access 2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Santosh Srivatsan
836c777680 XLEN parameterization for simx 2022-02-03 15:19:31 -05:00
Santosh Srivatsan
01d183c6a9 Removed xlen.h 2022-02-01 13:59:39 -05:00
Santosh Srivatsan
3eb2b71955 removed traces of xlen. Overloaded sext 2022-02-01 13:54:51 -05:00
Santosh Srivatsan
a73f656d06 Minor bug fixes 2022-01-31 17:01:14 -05:00
Santosh Srivatsan
4cf596338d Minor bug fixes 2022-01-31 15:53:49 -05:00
Santosh Srivatsan
7aa93a735d Added FLEN parameterization for RV32/64 F and D instructions 2022-01-24 15:42:15 -05:00
Santosh Srivatsan
91c22a2592 Fixed some riscv-tests 2022-01-22 12:54:10 -05:00
Blaise Tine
29df0da8b5 minor warning fixes 2022-01-10 20:33:37 -05:00
Santosh Srivatsan
f93303bac7 Minor update 2021-12-15 17:21:38 -05:00
Santosh Srivatsan
b1e82223ee Renamed rv_f* functions to rvf*_s to follow the naming convention between single and double precision floating point 2021-12-13 20:37:29 -05:00
Santosh Srivatsan
885bb58ca9 Merged RV64IMFD extensions to master branch 2021-12-11 17:06:29 -05:00
Santosh Srivatsan
3324b32a29 Moved Dockerfile to miscs 2021-12-10 21:54:41 -05:00
Santosh Srivatsan
5edb9098ce Merge branch 'simx64' 2021-12-10 21:48:29 -05:00
Santosh Raghav Srivatsan
bde789b320 Added support for RV32D and RV64D instructions 2021-12-10 16:30:24 -05:00
Blaise Tine
5825b7c15a dram simulator fix 2021-12-07 22:44:06 -05:00
Santosh Raghav Srivatsan
e6eda67d0c Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension 2021-12-06 18:55:13 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
41d7e6c63a cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes 2021-11-30 07:08:15 -05:00
Santosh Raghav Srivatsan
64d47f3637 Added support for RV64I instructions 2021-11-27 12:33:30 -05:00
Blaise Tine
b995843a5b cocogfx fixes and refactoring 2021-11-25 13:58:09 -05:00
Blaise Tine
a671e1a05d moving submodules into third_party folder 2021-11-24 18:10:00 -05:00