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184 commits

Author SHA1 Message Date
felsabbagh3
313a8e3b4b All cache bugs fixed - Handshaking 2020-03-28 21:43:02 -07:00
Blaise Tine
c8a6470595 redesigned driver demo, fixed startup code, removed --cpu from simx, 2020-03-29 00:38:17 -04:00
felsabbagh3
5dc9493c61 ALL tests passing - handshake 2020-03-27 21:34:49 -07:00
Blaise Tine
f7e0d1e491 missing runtime changes from OPAE 2020-03-27 22:51:54 -04:00
Blaise Tine
96e960fa69 missing runtime changes from OPAE 2020-03-27 22:51:54 -04:00
Blaise Tine
5a5c9f3981 merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
Blaise Tine
9b1b8789ac merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
felsabbagh3
614797e52f Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
felsabbagh3
39516a6f98 Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
wgulian3
3b74f071a7 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
f126a23114 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
wgulian3
123fb17723 Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
felsabbagh3
4e6de0dc38 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
5372c07b01 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
felsabbagh3
82ea79c680 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
Blaise Tine
8b4397f0ec fixed runtime Makefile 2020-03-16 14:58:02 -04:00
Blaise Tine
36547821fc temp files cleanup 2020-03-09 10:18:11 -04:00
Blaise Tine
717a75ade8 fixed opencl benchmarks 2020-03-09 09:55:16 -04:00
felsabbagh3
e2ffbcf14b MULTICORE WITH L2 WORKING 2020-03-09 01:17:11 -07:00
felsabbagh3
469334f23e MULTICORE WITH L2 WORKING 2020-03-09 01:17:11 -07:00
wgulian3
61803741f8 Merge branch 'master' into fpga_synthesis 
# Conflicts:
#	rtl/VX_back_end.v
#	rtl/VX_gpr_stage.v
#	rtl/VX_writeback.v
#	rtl/simulate/test_bench.cpp
#	rtl/simulate/test_bench.h
#	runtime/mains/dev/Makefile
 2020-02-18 03:34:38 -05:00
wgulian3
4184980188 verilator: run all riscv tests 2020-02-13 13:50:57 -05:00
wgulian3
e662ef4134 Fix verilator 2020-02-13 13:42:43 -05:00
wgulian3
86bfa4d1e4 Fix verilator 2020-02-13 13:18:06 -05:00
Blaise Tine
759349f2bf updated README and Makefile environment settings 2020-01-21 21:21:56 -05:00
fares
b752ce5485 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2019-11-25 02:52:22 -05:00
fares
44b8cdf5c1 Benchmarking stuff 2019-11-25 02:52:09 -05:00
Euna Kim
62ab6b3e98 Merge remote-tracking branch 'refs/remotes/origin/master' 2019-11-23 22:25:45 -05:00
fares
d2bd560593 OpenCL benchmarks running 2019-11-23 20:37:14 -05:00
fares
852d844618 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2019-11-23 10:00:15 -05:00
fares
597165d4e1 Fixed malloc problem 2019-11-23 01:31:24 -05:00
proshan3
30c8ef3931 Added support for vmacc 2019-11-22 23:55:47 -05:00
proshan3
0d763fd735 Vector matrix addition working 2019-11-22 19:23:54 -05:00
proshan3
10505feaf5 Vector matrix addition working 2019-11-22 19:23:54 -05:00
fares
e61f8ecace Removed the need to do vx_tmc(1) at start of main 2019-11-22 18:04:01 -05:00
fares
d733509c91 Removed the need to do vx_tmc(1) at start of main 2019-11-22 18:04:01 -05:00
proshan3
53e5e62e6c changes vector 2019-11-22 12:52:35 -05:00
proshan3
d7fa303282 changes vector 2019-11-22 12:52:35 -05:00
fares
c4d315dfed VCD for power 2019-11-21 23:25:51 -05:00
fares
fd80fa14c7 Uploaded vecadd that uses split/join 2019-11-21 20:26:07 -05:00
proshan3
b4ebc803f3 Added vector mask instructions 2019-11-21 20:18:29 -05:00
proshan3
9edb7fe76c Vector changes 2019-11-21 17:07:49 -05:00
fares
f4d982b3a4 basic rvvector example 2019-11-21 11:22:20 -05:00
Blaise Tine
3217588b37 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2019-11-21 00:44:59 -05:00
Blaise Tine
2dcd0ddfdc opencl sgemm benchmark 2019-11-21 00:41:17 -05:00
fares
13ebe51f03 Created a global linker file to fix descrepencies 2019-11-21 00:24:42 -05:00
fares
9cbceff690 Making sure nothing was lost 2019-11-20 23:59:44 -05:00
fares
f3e2bacee7 lseek simulator working 2019-11-18 15:30:51 -05:00