14 commits

Author	SHA1	Message	Date
Hanran Wu	ea9560b33b	merge	2024-08-23 17:44:24 -04:00
Jaewon Lee	d531fa6b26	64bit support	2024-06-29 17:43:20 -04:00
Blaise Tine	6b81b26ffc	enabling Makefile configuration with build folder support	2024-03-30 02:28:39 -07:00
Blaise Tine	1512138a15	minor update	2020-05-22 19:14:07 -07:00
wgulian3	f126a23114	Generate define overrides based on env vars for C and Verilog. ... gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.	2020-03-26 04:08:43 -04:00
wgulian3	5b3df797a4	Add modified RTL files for parameterized builds with VX_define_synth.v	2020-03-20 04:04:15 -04:00
felsabbagh3	0ee74bc566	migrated 100% to modelsim	2019-10-27 20:08:44 -04:00
felsabbagh3	e67310acfb	New Warp Scheduler + VCD Enable	2019-09-15 00:12:41 -04:00
felsabbagh3	3c3a443bd5	New RF with Evaluation	2019-09-11 01:04:23 -04:00
felsabbagh3	8c2ae97510	1 WARP 8 THREADS TESTED + FULLY WORKING	2019-03-31 05:21:00 -04:00
felsabbagh3	781c11c93f	Updated TODO	2019-03-22 04:21:21 -04:00
chris porter	91bfd7fa0f	ignore more test output	2017-09-19 16:49:35 -04:00
chris porter	96621adce4	ignore dot bin files	2017-09-12 17:50:28 -04:00
chris porter	f761c82ceb	add a gitignore	2017-09-12 17:48:56 -04:00