github-mirrors
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Updated 2025-09-28 03:13:12 -06:00
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
Updated 2022-09-30 19:16:01 -06:00
HARV - HArdened Risc-V
Updated 2022-03-10 11:29:46 -07:00
Basic RISC-V CPU implementation in VHDL.
Updated 2020-09-11 17:23:50 -06:00
A 5 stage-pipeline RV32I implementation in VHDL
Updated 2020-03-12 18:45:17 -06:00