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github-mirrors/ neorv32

VHDL 0 0

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asip axi cpu embedded fpga microcontroller neorv32 on-chip-debbuger processor risc-v riscv rtl rtos rv32 safety soc soft-core system-on-chip verilog vhdl

Updated 2025-04-17 13:02:34 -04:00

blizzardfinnegan/ icefunVHDL

VHDL 0 0

Tinkering with the iceFUN FPGA board, based on the iCE40-HX8K FPGA

Updated 2024-11-04 21:58:20 -05:00

github-mirrors/ harv

VHDL 0 0

HARV - HArdened Risc-V

fault-tolerance fpga processor reliability risc-v rv32i

Updated 2022-03-10 13:29:46 -05:00

github-mirrors/ RPU

VHDL 0 0

Basic RISC-V CPU implementation in VHDL.

apache2-license cpu fpga risc-v riscv vhdl

Updated 2020-09-11 19:23:50 -04:00