Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
André Sintzoff
c51819dcbd
verible-verilog-format: apply it on core directory ( #1668 )
...
using verible-v0.0-3430-g060bde0f/bin/verible-verilog-format
with default configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2023-12-04 11:16:35 +00:00
AEzzejjari
36c105a50d
Code_coverage: condition RTL with the AxiBurstWriteEn parameter ( #1667 )
2023-12-01 22:59:12 +01:00
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory ( #1540 )
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using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration
Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
2023-10-18 16:36:00 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter ( #1320 )
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* Variane as CVA6 parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix FPGA build
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix tipo in cva6.sv
* fix lint warnings
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix is_*_fpr functions
* remove blank lines
* set IsRVFI out of CVA6Cfg
* define config_pkg
* Fix ariane_pkg comments
* Fix Lint from André's feedbacks
* Fix parameter transmission
* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv
* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
2023-08-22 14:04:06 +02:00
JeanRochCoulon
716d21c424
Define AXI as cva6 input parameters ( #1315 )
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* add axi parameters to cfg
* Move axi_intf.sv from core to corev_apu
* Move ariane_axi_pkg.sv from core to corev_apu
* Merge axi and l15 into noc
* Fixes to build and run openpiton
---------
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
2023-07-24 10:34:30 +02:00
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter ( #1293 )
2023-07-19 08:21:39 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy ( #1287 )
...
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-07-01 17:24:21 +02:00
Zbigniew Chamski
a0893bce2b
Enable assertions in Verilator after migrating to Verilator v5. ( #1185 )
2023-04-19 09:35:40 +02:00
JeanRochCoulon
6d006558f1
Better control user AXI field when disabled ( #1159 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-04-03 10:20:51 +02:00
Nils Wistoff
d9933a5f86
Make AXI transactions modifiable ( #948 )
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
2023-03-13 10:57:47 +01:00
Nils Wistoff
17743bc712
cache_subsystem: Parametrise AXI interface ( #982 )
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Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified:
XLEN Cacheline Width AXI data width AXI address width
64 128 64 64
64 128 128 52
64 512 128 64
32 512 256 48
32 64 32 48
2022-10-26 11:20:19 +02:00
JeanRochCoulon
56f8c9f5fe
Add user field between memory and caches ( #857 )
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* wt_dcche_wbuffer.sv: fix assert
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Many files: Add user between memories and cva6
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Update std_nbdcache.sv
Make wb cache work
* Update setup.sh
Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2022-04-20 12:47:07 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
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* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
