Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
This PR is adding the APU design adapted to Altera Agilex7 FPGA.
It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.
