10 commits

Author	SHA1	Message	Date
Florian Zaruba	f0d267c363	Move UART to interrupt 0	2018-11-28 13:39:01 +01:00
Florian Zaruba	91d7babc87	🐛 Fix potential AXI ordering issue	2018-11-26 17:55:10 +01:00
Florian Zaruba	6381b3d3ee	Add ILA and GPIO peripheral	2018-11-25 21:22:51 +01:00
Florian Zaruba	785577d37a	🐛 Fix reset strategy in TB	2018-11-23 19:04:37 +01:00
Florian Zaruba	3e3d266078	Ethernet fixes, instantiate RGMII to MII converter	2018-11-23 17:18:44 +01:00
Florian Zaruba	4558960b88	Small pre-release clean-up	2018-11-23 11:37:14 +01:00
Florian Zaruba	db4f99e2ad	Ethernet preparation, fpga fixes	2018-11-20 19:02:52 +01:00
Florian Zaruba	bb821300f1	Put batch flow in place (incl small flow fixes)	2018-11-19 19:24:31 +01:00
Florian Zaruba	0c8eb5a52e	Fix PLIC address map and DTS	2018-10-10 17:23:03 +02:00
Florian Zaruba	63eb2cdc6d	Add Xilinx IPs	2018-10-03 14:36:48 +02:00