ed89c717f7
Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly. |
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|---|---|---|
| .. | ||
| 01_cva6_user | ||
| 02_cva6_requirements | ||
| 03_cva6_design | ||
| 04_cv32a65x | ||
| 05_cva6_apu | ||
| 06_cv64a6_mmu | ||
| _static | ||
| common | ||
| csr-from-ip-xact | ||
| design | ||
| riscv-isa | ||
| scripts | ||
| user_guide | ||
| .gitignore | ||
| conf.py | ||
| index.rst | ||
| Makefile | ||
| README.md | ||
| requirements.txt | ||
CVA6 documentation
CVA6 documentation is published as a Read the Docs documentation.
It can be generated by running make in this directory.
This generates all necessary sub-documents.
Configuration-specific manuals
For each supported target (e.g. cv32a65x), there are two manuals included in the main documentation: a tailored RISC-V instruction set manual, and a design documentation.
These documents are generated when building the main documentation.
Instruction set manual
Instruction set manuals (privileged & unprivileged) are based on the official RISC-V Instruction Set Manual repository. Some parts are stripped down or annotated to only include what's relevant for each specific configuration.
These manuals can be manually generated with: make -C 04_cv32a65x/riscv priv-html unpriv-html.
Replace 04_cv32a65x with the desired target.
Some of the files used in this documentation (config.adoc) are directly generated from the RTL.
Design documentation
Design documentation describes the internal architecture of the CVA6 processor.
It can be manually generated with: make -C 04_cv32a65x/design design-html.
Some of the files used in this documentation (config.adoc, parameters.adoc, port_*.adoc, csr.adoc, isa.adoc) are directly generated from the RTL.