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cva6/verif/sim
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Jalali e4a8ffb1f6
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Code coverage : exclude second instanciation (#2925) 
of instr_scan and cva6_fifo_v3

Signed-off-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
2025-04-14 14:30:24 +02:00
..
dv@f0c570d112 Convert DV into a submodule (#1591) 2023-11-03 11:20:08 +01:00
cov-exclude-mod.lst Code coverage : exclude second instanciation (#2925) 2025-04-14 14:30:24 +02:00
cva6-simulator.yaml move files to a verif directory 2023-09-07 09:50:50 +02:00
cva6.hvp FENCE_i : Remove fence_i from HVP and core-dv (#2811) 2025-03-06 13:21:49 +01:00
cva6.py [CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822) 2025-03-13 06:12:47 +01:00
cva6.yaml Add vcs-uvm-gate ISS target 2024-10-08 21:14:33 +02:00
cva6_base_testlist.yaml add UVM interrupt agent (#2309) 2024-07-05 11:54:34 +02:00
cva6_spike_log_to_trace_csv.py [Spike Yaml] Integrate Spike Yaml support. (#2304) 2024-07-11 08:37:37 +02:00
init_run_uvm_fsdb.do move files to a verif directory 2023-09-07 09:50:50 +02:00
init_run_uvm_vpd.do move files to a verif directory 2023-09-07 09:50:50 +02:00
init_uvm.do move files to a verif directory 2023-09-07 09:50:50 +02:00
Makefile add macros for assertions else clauses (fix #1624) (#2888) 2025-04-01 12:25:36 +02:00
setup-env.sh [CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822) 2025-03-13 06:12:47 +01:00
verilator_log_to_trace_csv.py move files to a verif directory 2023-09-07 09:50:50 +02:00