This MR implements the non-RTL part of CVA6 project changes needed for #2734:
* changes to scripts
* changes to configuration files
* turn off Zifencei support in RTL configuration.
* RVFI Tracer : Update tracer to support interrupts
* Randomize sv_seed by default
* Change pc64 to pc
* Fixes
* cva6.py : add the capability to create a log for sv_seed
* Tracer : keep pc64 64 targets failed
* Fix UVM seed for performance tests
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache.
When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory).
This PR contains the following modifications:
The CVA6 controller module rises the flush signal to the caches when executing a fence or fence.i instruction.
The HPDcache cache subsystem translates this fence signal to a FLUSH request to the cache (when the HPDcache is in WB mode).
Add new parameters in the CVA6 configuration packages:
DcacheFlushOnInvalidate: It changes the behavior of the CVA6 controller. When this parameter is set, the controller rises the Flush signal on fence instructions.
DcacheInvalidateOnFlush: It changes the behavior of the HPDcache request adapter. When issuing a flush, it also asks the HPDcache to invalidate the cachelines.
Add additional values to the DcacheType enum: HPDCACHE_WT, HPDCACHE_WB, HPDCACHE_WT_WB
In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer.
Introduction
This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension.
Implementation
Zbkb Extension:
Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip.
Modifications
1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set.
2. Updated the ALU and decoder to recognize and handle Zbkb instructions.
Documentation and Reference
The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added.
Verification
Assembly Tests:
The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include:
pack-01.S
packh-01.S
packw-01.S
brev8-01.S
unzip-01.S
zip-01.S
* cva6 refactor & cleanup to enable tandem reports generation for elf tests such as testelf for simu-gate:
1. merge redundant functions to run directed tests in `cva6.py` (`run_c`, `run_elf`, `run_assembly` -> `run_test`)
2. removed broken and unused functions by the way (`run_c_from_dir`, `run_assembly_from_dir`)
* collect sim reports of simu-gate job to display them in the cva6 dashboard : ⚠️ the simu gate job will still fail but the result on the dashboard will be accurate and will allow debugging
- FIX: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
- Declare VLEN as new CVA6 parameter
- smoke-hwconfig: run with vcs-uvm and use return0 tests to speed-up CI light stage timing execution
- Use dedicated linker scripts for 65x configuration.
- Use dedicated spike.yaml for 65x configuration.
- Set BHTEntries=128, cache=WT, scoreboard entries=8 to improve Coremark and Dhrystone results
- Run 4 iterations of coremark to improve results
