github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-23 13:47:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 7
cva6/corev_apu
History
Exact
Yannick Casamatta ce22b73d87 flist add vendorized obi references
2024-08-27 17:02:05 +02:00
..
axi_mem_if@b494701501 Add user field between memory and caches (#857) 2022-04-20 12:47:07 +02:00
bootrom Remove DROMAJO (#1204) 2023-04-24 23:05:53 +02:00
clint Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
fpga flist add vendorized obi references 2024-08-27 17:02:05 +02:00
openpiton Define AXI as cva6 input parameters (#1315) 2023-07-24 10:34:30 +02:00
register_interface@73de8e51b7 Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
riscv-dbg@e19d69efe7 riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (#746) 2021-10-01 17:02:34 +02:00
rv_plic@5b5c5a4c1c Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
src Fixes and Update CVXIF non regression tests, regression and TB (#2424) 2024-08-01 16:06:24 +02:00
tb Display number of cycles at test termination (#2443) 2024-08-13 17:12:13 +02:00