mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 03:44:46 -04:00

History

khandelwaltanuj 3a389af151 Some checks are pending bender-up-to-date / bender-up-to-date (push) Waiting to run Details ci / build-riscv-tests (push) Waiting to run Details ci / execute-riscv64-tests (push) Blocked by required conditions Details ci / execute-riscv32-tests (push) Blocked by required conditions Details added correct reset val (#2823 ) For cv64a60ax configuration		2025-03-12 15:19:15 +01:00
..
cv32a65x	[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. (#2651 )	2024-12-09 13:22:38 +01:00
cv64a60ax/spec	added correct reset val (#2823 )	2025-03-12 15:19:15 +01:00
Makefile	Update riscv-config infra to better match expressivity needs of CV32A65X. (#2193 )	2024-06-04 18:12:14 +02:00
README.md	Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. (#2133 )	2024-05-21 07:21:57 +02:00

File organization

Makefile: the makefile needed to regenerate the Yaml files using riscv-config.
TARGET: directory holding input and output files for configuration named TARGET (currently only cv32a65x)
- spec: Directory holding input files
  - isa_spec.yaml: specification of the ISA, including CSRs and privileges (expressed as canonical extension letters)
  - custom_spec.yaml: specification of custom CSRs
  - platform_spec.yaml: specification of platform-level values/properties
- generated: Directory holding generated files produced by riscv-config from the spec files
  - isa_gen.yaml: ISA definition completed y riscv-config
  - custom_gen.yaml: Custom CSR definitions completed by riscv-config
  - platform_gen.yaml: Platform-specific values/properties completed by riscv-config

Prerequisites

From any directory, run

make -C <CVA6_top_directory>/config/riscv-config all