f7dd49efa5
Introduction This PR adds support for Zbkb extension in the CVA6 core. It also adds the documentation for this extension. These changes have been tested with self-written single instruction tests and with the riscv-arch-tests. This PR will be followed by other PRs that will add complete support for the Zkn - NIST Algorithm Suite extension. Implementation Zbkb Extension: Added support for the Zbkb instruction set. It essentially expands the Zbb extension with additional instructions useful in cryptography. These instructions are pack, packh, packw, brev8, unzip and zip. Modifications 1. A new bit ZKN was added. The complete Zkn extension will be added under this bit for ease of use. This configuration will also require the RVB (bitmanip) bit to be set. 2. Updated the ALU and decoder to recognize and handle Zbkb instructions. Documentation and Reference The official RISC-V Cryptography Extensions Volume I was followed to ensure alignment with ratification. The relevant documentation for the Zbkb instruction was also added. Verification Assembly Tests: The instructions were tested and verified with the K module of both 32 bit and 64 bit versions of the riscv-arch-tests to ensure proper functionality. These tests check for ISA compliance, edge cases and use assertions to ensure expected behavior. The tests include: pack-01.S packh-01.S packw-01.S brev8-01.S unzip-01.S zip-01.S |
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| .. | ||
| 01_cva6_user | ||
| 02_cva6_requirements | ||
| 03_cva6_design | ||
| 04_cv32a65x | ||
| 05_cva6_apu | ||
| 06_cv64a6_mmu | ||
| _static | ||
| common | ||
| csr-from-ip-xact | ||
| design | ||
| riscv-isa | ||
| scripts | ||
| user_guide | ||
| .gitignore | ||
| conf.py | ||
| index.rst | ||
| Makefile | ||
| README.md | ||
| requirements.txt | ||
CVA6 documentation
CVA6 documentation is published as a Read the Docs documentation.
It can be generated by running make in this directory.
This generates all necessary sub-documents.
Configuration-specific manuals
For each supported target (e.g. cv32a65x), there are two manuals included in the main documentation: a tailored RISC-V instruction set manual, and a design documentation.
These documents are generated when building the main documentation.
Instruction set manual
Instruction set manuals (privileged & unprivileged) are based on the official RISC-V Instruction Set Manual repository. Some parts are stripped down or annotated to only include what's relevant for each specific configuration.
These manuals can be manually generated with: make -C 04_cv32a65x/riscv priv-html unpriv-html.
Replace 04_cv32a65x with the desired target.
Some of the files used in this documentation (config.adoc) are directly generated from the RTL.
Design documentation
Design documentation describes the internal architecture of the CVA6 processor.
It can be manually generated with: make -C 04_cv32a65x/design design-html.
Some of the files used in this documentation (config.adoc, parameters.adoc, port_*.adoc, csr.adoc, isa.adoc) are directly generated from the RTL.