* [rtl] Changed the default number of performance counters from 0 to 10 (#214)
* [rtl] Turning debug halt and exception addresses from parameters into signals (#269)
* [doc] Updating the docs regarding the turning of debug halt and exception addresses into signals (#269)
* Adding buildsim.log to .gitignore, as it is created by some make targets
* Adding Reset-value and detailed table to MISA register in the CV32E20 UM
* Adding detailed table to MISA register in the CV32E20 UM
* Replace Hardcoded Values with Parameters
* Removing RVB Comment
* remove parameter BranchPredictor
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter(s) from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from core lists
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the example configurations
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter from documentation
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove related and dead code
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
- Jinja2 is required by sphinx
- Version 3.1 and later are incompatible with the specified sphinx version
- see https://github.com/sphinx-doc/sphinx/issues/10291
- explicitly requiring this older version of Jinja2 solves this
- could be removed when moving to newer sphinx version
* remove parameter option WritebackStage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from formal verification code generated for SymbioticEDA
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove reference to the deleted parameterd from the documentation
Do not refer to WriteBack as to a stage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove related code to Writeback stage
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Removal of related and dead code after Writeback-stage removal
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* substitute ASSERT macro with one ignoring rst_ni and clk signals
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* keep clk_i and rst_ni for the sake of assert alone
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* BUGFIX: reintroduce en_wb signal between id and wb
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Remove dead and related code
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
When in the FLUSH state we cannot have `csr_pipe_flush` set as it
depends upon `instr_executing` being set (within `ibex_id_stage`) and
that is only set in the DECODE stage.
Co-authored-by: Greg Chadwick <gac@lowrisc.org>
* remove BranchTargetALU param.
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the documentation
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from the example configurations
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from examples
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from compliance verification
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* remove references to the removed parameters from core lists
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
* Remove references to the removed parameter(s) from Yosys framework configuration parser
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
---------
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
When the icache is enabled and data independent timing is required
variable fetch latency due to cache hit or miss may introduce
undesirable timing behaviour. This adds explicit mention of this to the
documentation.
We're going to want to make a couple more releases of Spike, cleaving
a bit closer to the upstream repository. Let's be explicit about which
version people should get.
This is to allow more consistent signalling in systems that integrate
Ibex (e.g. OpenTitan) so bus integrity errors external to Ibex and one's
detected within Ibex can be fed into the same alert whilst seperating
out Ibex's various internal alert causes.
We can now point at a single version of Spike (the "ibex_cosim"
branch, until we've managed to upstream things properly). And ditch
the OVPsim stuff: that's not going to be supported again any time
soon.
