Commit graph

13 commits

Author SHA1 Message Date
Davide Schiavone
f5b21e71c9
removed unused irq_enable signal in controller (#178) 2023-12-12 13:40:59 +01:00
christian-herber-nxp
9e0615bc3b
Merge pull request #156 from davideschiavone/patch_lowRISC_3
[rtl] do not take interrupts when single stepping and ignore MIE bit in U mode
2023-10-04 11:40:41 +02:00
Davide Schiavone
cb3c4a4bf4
Fix incorrect debug_cause priority against riscv-debug 1.0.0-STABLE (#154)
The relevant page [Debug Spec v1.0.0-STABLE, p.53] gives the following
priorities for resolving multiple concurrent reasons for entering debug mode....

DCSR.cause : Explains why Debug Mode was entered.

When there are multiple reasons to enter Debug Mode in a single cycle,
hardware should set cause to the cause with the highest priority.
1: An ebreak instruction was executed.                        (priority 3)
2: A Trigger Module trigger fired with action=1.              (priority 4)
3: The debugger requested entry to Debug Mode using haltreq.  (priority 1)
4: The hart single stepped because step was set.              (priority 0, lowest)
5: The hart halted directly out of reset due to resethaltreq. (priority 2)
   It is also acceptable to report 3 when this happens.
6: The hart halted because it’s part of a halt group.         (priority 5, highest)
   Harts may report 3 for this cause instead.

Other values are reserved for future use.

Co-authored-by: Harry Callahan <hcallahan@lowrisc.org>
2023-09-26 18:23:01 +02:00
Greg Chadwick
72c2f3ec4e merge [rtl] Ignore MIE bit in U mode 2023-09-26 17:50:30 +02:00
Davide Schiavone
9a79be864f
move nmi to irq 32 (#139)
* move nmi to irq 32

* fix exc cause

* update top tracing

* fix mcause read
2023-08-30 14:24:16 +02:00
Mike Thompson
e6cc750fc8
Identify source of display() in cve2_controller.sv
Adding the "%m" formatter to the $display message makes it easy to identify the source of the message.
2023-07-26 16:50:10 -04:00
christian-herber-nxp
066ff47261
remove branch predictor (#49)
* remove parameter BranchPredictor

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to the removed parameter(s) from examples

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from compliance verification

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from core lists

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from the example configurations

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to the removed parameter from documentation

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove related and dead code

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-07-20 16:40:10 +02:00
szbieg
7836daeb14
Remove dead and redundant code (#124)
Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-07-20 14:34:29 +02:00
Davide Schiavone
06c4a0c0e6
add fetch_enable_i (#118)
* add fetch_enable_i

* fix missign signals

* removed unused signals
2023-06-01 14:41:31 +02:00
christian-herber-nxp
3a9f2d058f
Feature/remove writeback stage (#56)
* remove parameter option WritebackStage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from examples

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from compliance verification

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from formal verification code generated for SymbioticEDA

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove reference to the deleted parameterd from the documentation
Do not refer to WriteBack as to a stage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove related code to Writeback stage

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Removal of related and dead code after Writeback-stage removal

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* substitute ASSERT macro with one ignoring rst_ni and clk signals

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* keep clk_i and rst_ni for the sake of assert alone

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* BUGFIX: reintroduce en_wb signal between id and wb

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-05-31 14:44:59 +02:00
christian-herber-nxp
ec096aafd3
[rtl] Don't take interrupts when single stepping (#97)
Fixes #1814

Co-authored-by: Greg Chadwick <gac@lowrisc.org>
2023-03-03 17:06:49 +01:00
christian-herber-nxp
f6268d4eb9
[rtl] Remove unused transition in ibex_controller FSM (#98)
When in the FLUSH state we cannot have `csr_pipe_flush` set as it
depends upon `instr_executing` being set (within `ibex_id_stage`) and
that is only set in the DECODE stage.

Co-authored-by: Greg Chadwick <gac@lowrisc.org>
2023-03-03 17:06:24 +01:00
christian-herber-nxp
932db14619
Rename all modules to cve2 (#25)
* rename files and modules to cve2

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* updated tb files

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remaining references to ibex: gitignore, examples, etc.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
2023-01-05 10:27:24 +01:00
Renamed from rtl/ibex_controller.sv (Browse further)