This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add a technology map for latches (only works with nandgate45 library
at the moment)
- Add a real latch-based clock gating cell
- Update timing path reporting to differentiate between register and
latch paths
- Update summary results in README to reflect the latch-based numbers,
plus add numbers for a micro-riscy-style (RV32EC) config
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Adds significant functionality to synthesis flow. Timing reports are
generated using OpenSTA and an area report is generated. Flow supports
open Nangate45 library from OpenROAD.
This PR includes the following:
- add script syn_yosys.sh, which runs sv2v and yosys for ibex_core
- add example std. cell lib cmos_cells.lib (copied from yosys repo)
- add dummy prim_clock_gating.v module
- add initial yosys synthesis script syn.ys
