syn/ filling up with result directories is a little annoying, this sets
up the default so everything ends up generated under syn/syn_out/. Flow
users can easily change this to meet their personal requirements.
- ready_i input to the prefetch buffer factored both it's own valid_o
output and the pc_set branch signal, neither of which are required.
- Refactoring the ready_i signal to just id_in_ready_i improves timing
significantly for the icache.
- Also removed offset_in_init signal which appeared to serve no purpose.
This adds a dependency on $(TESTLIST) (which is that file) for each
target that depends on $(TEST_OPTS), a set of command line options
that includes --testlist=$(TESTLIST).
In practice, we could actually just add the dependency to the
$(metadata)/instr_gen.gen.stamp target, since all the other affected
targets transitively depend on that, but this seems a little confusing
so I've made the dependency explicit.
This is mostly just adding comments and docstrings and pulling the
guts of the comparison into its own function.
I've also got rid of the subprocess calls for appending to a log file
and now calculate the pass/fail count from the return codes of the
checkers rather than grepping in the regression log (hopefully it
gives the same result!)
Since we're not doing stuff with 'make -f path/to/Makefile', we always
know that DV_DIR (as computed) is the current directory, so we can get
rid of it completely.
This is a bit more verbose, but I think it's a bit more obvious what's
going on, and quite a lot of the added lines are docstrings explaining
the code.
We now split "find the list of commands to run" from "run the
commands" with or without LSF.
The other major change is that the --lsf_cmd parameter defaults to
None, rather than the empty string. The patch also updates the
Makefile accordingly.
Finally, since we're now a little more careful with passing paths
around, we don't have to change cwd for each run. I'm not convinced
that the LSF mode actually worked before, since we needed to run each
command in a different directory. It should probably work now, but I
don't have access to LSF to check.
The only sad thing is that UVM leaves a 'tr_db.log' file lying around
in the current directory. I don't think we really care about the
contents, but can't see how to disable it, so I've added it to
gitignore.
Before this patch, the default behaviour picked a different random
seed for each test run (and didn't store it anywhere). I think this is
a bit confusing: you can't reproduce the test without digging around
in log files. Now, we pick a seed at the start of the program, print
it, and use it for each test (not as crazy as this sounds: the seed
controls things like random stalls, but the tested program will be
different each time).
Note that this patch won't actually have any effect, since we
currently only use sim.py from dv/uvm/core_ibex/Makefile, which
specifies the seed every time.
Since these are boolean flags "enable this, please", we use argparse's
support for them.
Command line change:
Before: --en_cov=0
After:
Before: --en_cov=1
After: --en_cov
and similar for en_wave
This generally tidies up and documents how we substitute options and
environment variables in get_simulator_cmd. It's now slightly laxer,
so it won't moan about a missing environment variable or option if
it's not actually used in the command.
This means we can wrap main() in a try/except block. That way, future
patches can change code that fails to throw an exception, rather than
having to do the ugly "write to stderr; exit 1" dance.
This also catches a global (cwd) which we were passing implicitly to
rtl_sim. Fortunately, we already have that value in _CORE_IBEX, so can
just use that.
We now put sys.path back after importing things and no longer import
'*' from anything (which means static analysis tools can now spot when
we've got a name wrong).
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3f584adef07b7f04edda8a6ba1dfc01a14df5d98
* update ebreak generation for ML test (Udi Jonnalagadda)
Signed-off-by: Udi <udij@google.com>
Correcting some small issues that cause newer versions of OpenSTA to
fail (previously it issued an error and continued).
- ABC/OpenSTA disagree how set_driving_cell command works so introduce
seperate ABC SDC file
- Run clean before generating STA netlist, otherwise yosys generates
some assignements to unused wires that OpenSTA's verilog parser dislikes
The third pipeline stage is a new writeback stage. Ibex can now be
configured as the original two stage design or the new three stage
design using the `WritebackStage` parameter in ibex_core. This defaults
to 0 (giving the original two stage design).
The three stage design is *EXPERIMENTAL*
In the three stage design all register write back occurs in the third,
final stage. This allows a cycle for responses to loads and stores so
when the memory system can respond in a single cycle there will be no
stall. This offers significant performance benefits.
Documentation of the three stage design is still to be written so
existing documentation applies to the two stage design only as various
aspects of Ibex behaviour will change in the three stage design.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4583049cc2b3469ba9dea56b5e2d75809a89d8f3
* Allow running compile command in LSF (google/riscv-dv#506) (taoliug)
* improve documentation of config options (Udi Jonnalagadda)
* Update AMO region and data sections (google/riscv-dv#503) (taoliug)
* Avoid jumping to a sub program of other harts (google/riscv-dv#502)
(taoliug)
* Use .section for data sections by default (google/riscv-dv#501)
(taoliug)
* create PMP accessible region for exception handlers and start/end
sections (Udi Jonnalagadda)
* minor change to signature_addr passed to generator (google/riscv-
dv#497) (udinator)
* Solve before cconstraints modified (google/riscv-dv#476) (Dariusz
Stachańczyk)
* Move instruction sections together for multi-harts (google/riscv-
dv#495) (taoliug)
* add seed capability to CSR test generation (Udi Jonnalagadda)
* fix pmp/shifted_addr compile warning (google/riscv-dv#493)
(udinator)
* User long jump to switch between different harts (google/riscv-
dv#491) (taoliug)
* Fix s_region generation (google/riscv-dv#487) (taoliug)
* update rv32imc/riscv_pmp_test testlist options (google/riscv-dv#486)
(udinator)
* Fix default value of num_of_harts (google/riscv-dv#485) (taoliug)
* Add shared memory region for multi-harts AMO (google/riscv-dv#484)
(taoliug)
* Add a runtime option num_of_harts (google/riscv-dv#483) (taoliug)
* Add multi-thread support (google/riscv-dv#482) (taoliug)
Signed-off-by: Udi <udij@google.com>
The --end_signature_addr argument doesn't go to Verilog; instead it
makes it through run.py (vendored-in, so hard to change) and
eventually gets inserted into some assembly code.
Before this patch,
make ITERATIONS=1 TEST=riscv_csr_test ISS=spike SEED=123
failed with:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S: Assembler messages:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:526: Error: illegal operands `li x2,8ffffffc'
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:533: Error: illegal operands `li x2,8ffffffc'
The main point of this is that it's somewhere we can store what it
calls "ss_opts": the options that we must pass to Spike to tell it the
memory layout of the simple_system environment.
While we're at it, I've tried to make this reasonably pleasant to use.
So you can do
spike-simple-system.sh <elf-file>
just to run the thing. To pass stuff to Spike without the
bash script getting in the way, use '--':
spike-simple-system.sh -- my option -h --here <elf-file>
We do this by pulling the definition of host_addr_o and host_req_o out
of an always_comb process in riscv_testutil.sv.
When set inside the process, Verilator warns about a combinatorial
loop. This happens because a read request could go out on the bus and
appear again (combinatorially) on the slave interface, setting
read_signature_and_terminate. This doesn't actually happen (because
read_signature_and_terminate only takes effect when we are in state
WAIT), but Verilator's sensitivity tracking isn't fine-grained enough
to notice.
If you just build simple_system a fusesoc line like
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system
then the change to ibex_simple_system.sv suffices, but if you
explicitly set a parameter in fusesoc like this:
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system \
--RV32M=1
then it overrides the default parameter with a literal 1. We declare
the parameter as an 'int', so I guess that's quite a reasonable
behaviour from fusesoc. Anyway, this check only triggers when a 1-bit
parameter is set with a literal 1, so should be safe. (If you do
something buggy like setting it to 2, it will still moan at you). This
patch adds a waiver file in examples/simple_system that silences the
warning.
This patch also makes the equivalent change to riscv_compliance,
adding a waiver file in dv/riscv_compliance/lint and fixing up the
default parameters.
