This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)
This adds Verilator lint support to our fusesoc core file. A waiver file
is created to waive all well-understood lint warnings. The UNOPTFLAT
warnings are not well understood at the moment, they are waived for now
and further discussion is expected to happen in a GH issue (referenced
in the waiver).
Run with
```
fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core
```
The waiver file support requires edalize >= 0.1.5.
Update code from upstream repository https://github.com/google/riscv-
dv to revision a07e0a726edf0230314c08d31546eecbed23054b
* Merge pull request #53 from google/flow (taoliug)
* Update README file for the new flow (Tao Liu)
* Merge pull request #52 from google/flow (taoliug)
* Add timeout mechanism to the flow (Tao Liu)
* Merge pull request #51 from google/flow (taoliug)
* Simulation flow update (Tao Liu)
* Merge pull request #50 from udinator/master (taoliug)
* added license for csr_template.yaml (Udi)
* Merge pull request #49 from google/dev (taoliug)
* Update log process script (Tao Liu)
* Merge pull request #48 from google/dev (taoliug)
* Fix illegal instruction issue (Tao Liu)
* Merge pull request #47 from google/dev (taoliug)
* Refactor the simulation flow (Tao Liu)
* Merge pull request #45 from danghai/master (taoliug)
* Add .gitignore to remove untracked files (danghai)
* Fix warning from Questa optmize (danghai)
* Add optimize log file for Questa simulator (danghai)
* New YAML based simulation flow (Tao Liu)
* Merge pull request #40 from scottj97/typos-redone (taoliug)
* Fix typos in comments (Scott Johnson)
* Fix typos/grammar in README (Scott Johnson)
* Merge pull request #43 from udinator/master (taoliug)
* use hex format in YAML description (Udi)
* CSR test description (Udi)
* removed run script (Udi)
* Modified CSR test generation code to adhere to style guidelines.
(Udi)
* Merge pull request #41 from vandanaprabhu/questa (taoliug)
* CSR Generation Script and YAML template (Udi)
* Prevent Xcelium from attempting to run a simulation during the
compile step (Scott Johnson)
* Document support for Questa (Scott Johnson)
* Fix simulation-time warnings from Mentor Questa (Scott Johnson)
* Fix compile warnings from Mentor Questa (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Adding support for using the Questa simulator (Vandana Prabhu)
* Pass proper seed to Cadence Xcelium simulator (Scott Johnson)
* Convert compile commands to functions instead of variables (Scott
Johnson)
To enable recoverable non-maskeable interrupts (NMIs), an additional
set of registers is needed to backup `mstatus.MPP/MPIE` as well as
`mepc` and `mcause`. This is currently not part of the RISC-V Priv
Spec (v1.11). This commit adds these registers called `mstack` CSRs
according to the following proposal:
https://github.com/riscv/riscv-isa-manual/issues/261
These CSRs are only accessed by the hardware and not accessible to
software running on the core.
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This commit adds the `mip` and `mie` CSRs as well as the software,
timer and external interrupts.
Currently these interrupts are overlapped with some of the legacy
interrupts, i.e., the core will jump to the same address for different
interrupts. For example, the software interrupt has the same ID as
legacy interrupt #3. Thus, the handler must read the `mip` register
to find out whether the interrupt routine has been entered because of
the software interrupt or the legacy interrupt.
Eventually, the number of legacy interrupts will be reduced to avoid
this overlapping, and they will be connected to the `mie` and `mip`
CSRs directly.
We want people to get an error when compiling the tracer with Verilator:
this file should not be used with Verilator. An error is better than
silently getting the wrong result.
This change is slighly painful, but a necessary cleanup around the
tracer.
- We now provide a separate core file for the tracer, called
"ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
"lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
"ibex_core_tracing.sv", and the core file is correspondingly called
"ibex_core_tracing.core. The core in it is called
"lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
This ensures that we have the same name for the core file, the source
entry point, and the core name.
IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
The ibex_tracer_define.sv file was removed from the FuseSoC core files,
but not from the src_files.yml (for Bender) and the .f file.
This is in line with the changes made in
f12b94c2a2.
The custom reg-reg load instruction was added in the original design but
is no longer needed. This commit removes it. Also, load instructions
with `instr[14:12] == 3'b110` are now decoded as illegal.
This resolves#25.
Without this commit, the PC is still set to a possible wrong jump
target on illegal JALR instructions ultimately causing the wrong PC
being saved to `mepc` during the illegal instruction exception.
This bug has been reported by @taoliug. This commit resolves#170.
This commit fixes the write back FSM to not store values returned from
memory to the register file when the LSU is reporting a load error.
This bug was reported by @ivanmgribeiro. This commit resolves#162.
This commit changes the controller to save the PC of the next
instruction to the dpc CSR when entering debug mode upon a halt
request instead of the PC of the current instruction (only valid
for EBREAK instructions).
This bug was reported by @taoliug. This resolves#164.
This commit fixes two bugs in the decoder:
1. For illegal branch condition selections, the illegal instruction
condition must be signaled as long as the instruction is being executed
and not just during the first cycle, as the controller cannot interrupt
multicycle instructions.
2. Illegal instructions should also be signaled when `instr[28]` is set
for register-register ALU operations. Previously, these were not
signaled as the original design used `instr[28]` to encode custom bit-
manipulation instructions.
These bugs were discovered by @taoliug. This resolves issue #163.
The RVFI implementation make use of signals from the decoder and
controller to detect the state of the processor.
Especially the signal for a new and retired instruction.
* Controller: remove impossible condition for `DBG_TAKEN_IF`
There is no way to jump into `DBG_TAKEN_IF` because of an EBREAK
instruction. Thus, this case also does not need to be checked.
* Controller: do not enter debug when `debug_req_i` goes low
With this commit, the core is prevented from entering debug mode when
the debug request signal is deasserted during that procedure.
Previously, the core would still enter debug mode but not updating the
debug CSR.
This resolves#153 reported by @taoliug.
* Update ibex_controller.sv
