This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Vendor in some updates to PMP test generation.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 17d79847e376a591cb3dcaae7601c98b0e70e8ac
* Update pygen/pygen_src/isa/riscv_cov_instr.py (Hodjat Asghari
Esfeden)
* Minor issues fixed in the functional coverage flow (Hodjat Asghari
Esfeden)
* fix pmp offset constraint (Udi Jonnalagadda)
* Fix minor issues (aneels3)
* - Adds riscv_instr_cover_group file with a few covergroups -
Confirms riscv_instr_cov_test script is up and running fine -
Initializes the registers to 0 during their first gpr_state access
(for ovpsim output log) (Hodjat Asghari Esfeden)
* update directed pmp sequence constraint (Udi Jonnalagadda)
* remove unreachable if...else statement (Udi Jonnalagadda)
* update post_process() (aneels3)
* add ecall_handler (aneels3)
* Fix post_process() issue (aneels3)
* Fix typo in post_process (aneels3)
* Completed riscv_cov_instr class (decoupled from riscv_instr_cov_test
file) Added private _riscv_cov_instr module to manually retrieve
format/category/group/imm_t based on the name of the instruction
(Hodjat Asghari Esfeden)
* add post_process() (aneels3)
Signed-off-by: Udi <udij@google.com>
The shortlog from the vendor tool's automated patch is reproduced at
the bottom of this commit message.
The automated commit is squashed with one to update how we depend on
bus parameters. Before, we had to provide an "Ibex top package". This
behaved the same as OpenTitan's "lowrisc:constants:top_pkg", but
avoided having to vendor in that file.
On the OpenTitan side, this has been tidied up with commit
d266c68 ("[dv] Update dv_utils sources to use bus_params_pkg"). This
changes the dependency of dv_utils to
"lowrisc:opentitan:bus_params_pkg". We still have to provide our
own (now called "lowrisc:ibex:bus_params_pkg") and need to patch the
dv_utils dependency, but this is a bit cleaner because dv_utils is
less likely to accidentally include dependencies on OpenTitan
internals.
On our side, we have to update the vendoring patch for dv_utils (and
change its name). We also need an equivalent patch for dv_lib. Then we
rename our hacky "Ibex top package" to "bus_params_pkg". The ICache DV
environment also needs patching to use the bus parameters properly.
Phew!
* [dv] Update prim_present cov opt (Srikrishna Iyer)
* [dv] Align VCS and Xcelium cov var names (Srikrishna Iyer)
* [dv] Split coverage for functional and auto tests (Srikrishna Iyer)
* [dvsim] Do builds smartly (Srikrishna Iyer)
* [syn] Carry over synthesis flow updates from bronze (Michael
Schaffner)
* [dvsim] Lint cleanup (Srikrishna Iyer)
* [dvsim] Allow testplan to be omitted (Srikrishna Iyer)
* [dvsim] Address lowRISC/opentitan#3071 comments (Srikrishna Iyer)
* [dvsim] lint cleanup (Srikrishna Iyer)
* [dvsim] Add support for second-level indirection (Srikrishna Iyer)
* [dvsim] Change cores-root to avoid conflicts with autogen'd core
files (Michael Schaffner)
* [dvsim] Update `tests` key behavior in regressions (Srikrishna Iyer)
* [lint] Minor update of ERROR patterns in parser script (Michael
Schaffner)
* [packer] Revise the implementation (Eunchan Kim)
* [flow] Remove lint makefile (Timothy Chen)
* [flows] Various updates to tools and documents to suppose top/ip
select (Timothy Chen)
* [dv/shadow_reg] shadow_reg update error (Cindy Chen)
* [rtl/alert] change the naming from _en_i to _req_i (Cindy Chen)
* [dvsim] Tidy up config file loading in FlowCfg.py (Rupert Swarbrick)
* [dvsim] Make it simpler to derive from FlowCfg (Rupert Swarbrick)
* [lint] Update warning/error exclusions in parser scripts (Michael
Schaffner)
* [dvsim] Fix for `--tool` override (Srikrishna Iyer)
* [dvsim] Bug fix in LintCfg.py (Srikrishna Iyer)
* [prim/dv] Integrate LFSR TB with dvsim (Udi Jonnalagadda)
* [uvmdvgen] Update template to reflect bind reorg (Srikrishna Iyer)
* [dv] remove prim_lfsr_bind (Srikrishna Iyer)
* [dv] Cleanup lint warnings in csr_utils_pkg (Srikrishna Iyer)
* [dv] Cleanup lint warnings in clk_rst_if (Srikrishna Iyer)
* [dvsim] Fix coverage dashboard link (Srikrishna Iyer)
* [prim] Rename prim_util_memload.sv to svh (Philipp Wagner)
* [lint/doc] Update linting readme to reflect recent updates (Michael
Schaffner)
* [lint] Remove legacy Makefile flow for linting tools (Michael
Schaffner)
* [dvsim/lint] Enable Verilator lint in Dvsim (Michael Schaffner)
* [prim_arbiter_fixed/fpv] Add generated FPV testbench (Michael
Schaffner)
* [prim_arbiter_fixed] This adds a fixed priority arbiter (Michael
Schaffner)
* [prim] Domain-Oriented Masking AND logic (Eunchan Kim)
* [dv] Update dv_utils sources to use bus_params_pkg (Srikrishna Iyer)
* [dv] Update mem_model to use bus-params_pkg (Srikrishna Iyer)
* [dv] Update dv_lib sources to use bus_params_pkg (Srikrishna Iyer)
* [uvmdvgen] Support for setting vendor name in VLNV (Srikrishna Iyer)
This signal aimed to ensure loads/stores completed succesfully when an
interrupt or debug request appeared at the same time they were being
executed when the writeback stage is present. However other stall logic
suffices for this purpose (debug/interrupt will wait for instruction to
unstall in ID/EX which only happens once request has been sent out, then
first instruction of debug/interrupt handler will stall until load/store
response has been seen based on the generic stall logic for lsu requests
in the writeback stage).
With this signal in place debug single stepping was broken around loads
and stores.
Fixes#1029
- Add a technology map for latches (only works with nandgate45 library
at the moment)
- Add a real latch-based clock gating cell
- Update timing path reporting to differentiate between register and
latch paths
- Update summary results in README to reflect the latch-based numbers,
plus add numbers for a micro-riscy-style (RV32EC) config
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This PR adds a riscv-dv option `enable_write_pmp_csr=1` to each of the
tests in the existing PMP test suite.
This will enable the core to execute a directed test sequence to write
random values to each `pmpaddr` and `pmpcfg` CSR in order to test write
accessibility and spec compliance.
The original values stored in these CSRs are restored after this random
write.
Signed-off-by: Udi <udij@google.com>
This commit makes sure that whenever Vivado is used, the Verilog
define `FPGA_XILINX` is set. This define can be used to enable Xilinx
specific pragmas in the RTL code. It is currently used to implement
the performance counters with DSP slices (incl. integrated output
registers for counter widths <= 32) which helps to save logic resources
and FFs (-7% and -15% when using e.g. 10 counters).
Previously, we had to set this parameter in every single top-level .core
file using Ibex.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Verible lint now supports waivers without regex and line arguments. Use
this new feature and remove the workaround we had in place.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
This PR updates the `implemented_csrs` list in `riscv_core_setting.sv`
and adds the two custom CSRs `cpuctrl` and `secureseed` to the
`custom_csrs` list. Both are for use by the riscv-dv generator.
Signed-off-by: Udi <udij@google.com>
This removes the manually copied version at dv/uvm/core_ibex/common
and vendors things properly now that the vendor tool supports such
things (this picks up the same OpenTitan version as the previous
commit: lowRISC/opentitan@067272a2).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
067272a253f4eeed4ae58a9171ee266256528117
* [dv/common] initial support for shadow register (Cindy Chen)
* [rtl/prince] Small fixes for PRINCE cipher logic (Udi Jonnalagadda)
* [dv doc] Fix rendered testplan table (Srikrishna Iyer)
* [prim/dv] Enable coverage collection for PRESENT (Udi Jonnalagadda)
* [dvsim/syn] Minor fix in message reporting (Michael Schaffner)
* [prim] Make prim_clock_inverter a tech specific prim (Michael
Schaffner)
* [vsg] fix _i/_o for several modules (Scott Johnson)
* [doc] Update Licence Headers to fit agreed style (Sam Elliott)
* [vsg] fix _i/_o usage on sram_arbiter (Scott Johnson)
* [vsg] fix _i/_o usage on prim_fifo (Scott Johnson)
* switch to host, primary, or over-arching as appropriate (Scott
Johnson)
* [dvsim/lint/syn] Properly set the errors_seen value to return
nonzero status (Michael Schaffner)
* [dvsim] Fix open() call with Pathlib for older Python versions
(Michael Schaffner)
* [style-lint] Last round of minor fixes to get all targets clean
(Michael Schaffner)
* [prim] Add shadow register primitive (Pirmin Vogel)
* [flash_ctrl] Cosmetic updates enum literals (Srikrishna Iyer)
* [tool/script] delete clean section in make files (Cindy Chen)
* [dvsim] Add git commit and branch info to reports (Michael
Schaffner)
* [dvsim/syn/lint] Add options to selectively sanitize reports
(Michael Schaffner)
* [lint] Update waiver file for prim_generic_pad_wrapper (Michael
Schaffner)
* [prim_pad_wrapper] Update pad wrapper (Michael Schaffner)
* [alert_handler/rtl] priority between ping_ok and sig_int_err (Cindy
Chen)
* [prim] Add a few prim cells needed for clock / resets (Timothy Chen)
* [dv] added default timeout message to DV_SPINWAIT (Srikrishna Iyer)
* [dv] Add mechanism to configure vseq via knobs (Srikrishna Iyer)
* Make the wmask assertion in prim_generic_ram_*p only apply to writes
(Rupert Swarbrick)
* [prim_gate_gen] Recalibrate gate generator for new std cells
(Michael Schaffner)
* [primgen] Use SafeDumper for YAML (Philipp Wagner)
* [primgen] Fix some flake8-reported style issues (Philipp Wagner)
* [prim] Improve extraction of parameter port list (Philipp Wagner)
* [prim] Remove outdated comment from primgen (Philipp Wagner)
* Added missing include prim_assert.sv (Dawid Zimonczyk)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This fixes a test failure that I was seeing when following a "many
errors" test by something different. To reproduce,
make -C dv/uvm/icache/dv \
SEED=1465832714 \
TESTS=ibex_icache_stress_all_with_reset
There are actually two different ways this can come unstuck:
(1) Memory request goes out and gets put into the response queue.
req_i goes low. Sequence changes. req_i goes high and we get the
response from the previous request (but mem_err_shift has changed
in the meantime).
To fix this, we pair up the memory seed and its associated
mem_err_shift in the scoreboard queue, rather than retrieving
mem_err_shift from the config object when the response comes in.
(2) Memory request goes out. Sequence changes. Memory request is
handled (with new mem_err_shift). Scoreboard sees the result. New
sequence generates its first item.
In this case, the scoreboard will expect the old mem_err_shift and
see the new one. To fix this, we add an extra entry to the list of
valid states in the scoreboard if needed so that we also check the
mem_err_shift currently in the config object.
You might worry about what happens if we have two back-to-back
sequence changes that change mem_err_shift without ever changing seed:
what happens if we have a situation like (1), but for the "middle"
sequence. To avoid this problem, we actually add the extra entry in
the fix for (2), so it will look like a new seed arrived as part of
the middle sequence, so long as we have read at least one
result (always true in the core sequence).
This now allows you to specify how many seeds to run. Sadly, you can't
say "give me 10 seeds, starting at 1234" because dvsim doesn't support
that at the moment. But it does at least avoid quite such long command
lines.
Instead of:
../../../../vendor/lowrisc_ip/dvsim/dvsim.py \
ibex_icache_sim_cfg.hjson \
--scratch-root ../../../../build \
--reseed 5 \
-c
you can run:
make RESEED=5 COVERAGE=1
We now have a clock/reset interface and the dv_utils stuff vendored
from OpenTitan so can delete the duplicates and point the file list at
the vendored files.
The only difficulty is that the clock interfaces are slightly
different, so there are a couple of minor changes to the core_ibex
test lib, renaming "clk_if" to "clk_rst_if" and changing how we apply
resets.
Note that the testbench (core_ibex_tb_top.sv) starts the clock and
resets the DUT at the start of time. This is different from how other
OpenTitan VIP does things (where the reset happens in the sequence),
but this is the smallest change I could make from how it worked
before (where the reset happened in the clock interface itself).
The idea is that this can supply top_pkg.sv, a top-level thing in
OpenTitan, for DV code we vendor from there. It's probably better to
do this than to directly vendor in OpenTitan's top_pkg, because the
latter has information about e.g. flash memory layout, which doesn't
really have any meaning for Ibex.
cov_report_page is used by dvsim's SimCfg.py to print a message to the
console with the path to the dashboard HTML page. Most of these
messages have the full path (useful for copy-pasting), but this one
didn't.
This is essentially a duplicate of OpenTitan PR 2934[1] (because we're
not able to vendor these files properly yet).
[1] https://github.com/lowRISC/opentitan/pull/2934
As pointed out by @tomroberts-lowrisc in #983, the current
implementation of riscv_debug_single_step_test cannot handle
single-stepping over instructions that change the PC.
This PR aims to introduce this functionality, utilizing the
new instr_monitor_if.
Now, if the core single-steps onto a branch/jump instruction, the
testbench will log the new target PC and compare it against the actual
target address stored in `dpc`.
"Normal" instructions are checked as usual by incrementing the
instruction's PC by either 2 or 4 (depending whether it is compressed)
and comparing that against `dpc`.
Previously, these bits were not checked when decoding slli, srli and
srai, causing some illegal instruction encodings not to trigger an
illegal instructions exception.
This resolveslowRISC/Ibex#1018.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This PR modifies the Ibex DV environment to use request/response
terminology instead of the current outdated naming scheme.
These changes are purely aesthetic.
- Add SECDED ECC checking to the register file when SecureIbex is
enabled
- No correction is attempted, but an alert is raised for the system to
intervene
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
But if you are using precompiled UVM it may be compiled with other timescale depending on compilation option used when it was compiled or tools default timescale value (uvm does not set timescale int the code).
In this case for us precompiled UVM timescale is 1ps/1ps - so UVM gets 1000000000 in set timeout but interprets it as ps. As a result timeout is 1000 times smaller that you expect. That is why we are getting timeouts.
It is hard to find perfect solution. One of them is to recompile the UVM with -timescale 1ns/ps (or whatever you will use for your design).
Fix a lint error reported by AscentLint:
```
E ALWAYS_SPEC: ibex_counter.sv:59 Edge triggered block may be more accurately modeled as always_ff New
```
* Mention the need to install `libelf-dev`. Thanks to Bert Pieters for
reporting this.
* Guide users to install our Python dependencies, including fusesoc and
edalize, from `python-requirements.txt`, to ensure they have the
right version.
* Prefer ELF files for Verilator simulations. This makes it easier to
use existing ELF files from another software build system.
Fixes#1019
We previously had a dependency on all primitives in Ibex, even though we
only depend on the LFSR primitive. Now that there's a more fine-grained
dependency available, we can use that.
This has the great benefit of restricting all lint tools to only the
code we're interested in, and not linting all primitives in OpenTitan
together with Ibex. This also helps tools like yosys, which aren't able
to parse all of OpenTitan's code yet.
