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  • 5f3b73ab8a Remove all case inside from decoder Sven Stucki 2015-08-28 18:50:22 +02:00
  • 2c93147fc3 Remove dead wb_stage file and module Andreas Traber 2015-08-28 17:17:46 +02:00
  • 1cbbcfb90b Fix linting errors/warnings and remove dead signals Part #2 Andreas Traber 2015-08-28 17:15:55 +02:00
  • d0f4ac75fb Fix linting warnings and errors Remove lots of dead code Part #1 Andreas Traber 2015-08-28 16:48:20 +02:00
  • de0d3dc76d Small cosmetics on IF stage Sven Stucki 2015-08-28 15:41:44 +02:00
  • 18e0373468 Take #3, don't mix blocking and non-blocking assignments Andreas Traber 2015-08-28 14:01:39 +02:00
  • 5ea5e01990 Synthesis problems... take #2 Andreas Traber 2015-08-28 13:55:50 +02:00
  • 6cf4b2f229 Fix PCMR for synthesis... Andreas Traber 2015-08-28 13:52:59 +02:00
  • f54b164778 Fix external performance counters Andreas Traber 2015-08-28 13:43:23 +02:00
  • 0188441cc7 Silence exception warning Andreas Traber 2015-08-28 11:31:09 +02:00
  • d99621f699 Add performance counters Andreas Traber 2015-08-28 09:57:37 +02:00
  • 8c4a99b5ec Fix jalr stall and make jump more efficient Andreas Traber 2015-08-27 13:57:13 +02:00
  • 4baf8eaad9 Added missing compressed instruction: c.slt Andreas Traber 2015-08-27 09:39:22 +02:00
  • cdabd40c59 Improve tracer output slightly Sven Stucki 2015-08-27 01:11:34 +02:00
  • 302747b9e4 Fix c.sllr and c.srlr decoding Sven Stucki 2015-08-27 01:11:10 +02:00
  • 5b3ba2d1d6 Works, but bug in compressed decoder for sll Andreas Traber 2015-08-26 22:57:49 +02:00
  • d324cfc01f IF Sync, problems in RVC Sven Stucki 2015-08-26 19:13:09 +02:00
  • 685b6dbabb Make illegal insn warning less verbose in simulation Sven Stucki 2015-08-26 19:12:25 +02:00
  • a18972db26 Add c.nop Sven Stucki 2015-08-26 19:11:54 +02:00
  • 793d45f254 Fix illegal instruction exception throwed when not actually decoding an instruction Sven Stucki 2015-08-26 18:14:00 +02:00
  • 9efada0ffa Fix last commit, small cleanup Sven Stucki 2015-08-26 17:21:35 +02:00
  • 84bec09a64 Fix illegal RVC instructions not causing exceptions Sven Stucki 2015-08-26 16:40:22 +02:00
  • 8bdb45799f Fix jump_in_id signal should only be set in DECODE in controller Sven Stucki 2015-08-26 15:22:49 +02:00
  • 08b2be2b76 First version of optimized new IF stage, simplified a lot Sven Stucki 2015-08-26 15:13:04 +02:00
  • 384f160f2b Eliminate pc_mux_boot Sven Stucki 2015-08-25 15:34:35 +02:00
  • b7d05855f8 Optimized IF intermediate step Sven Stucki 2015-08-25 15:22:48 +02:00
  • 20110184e6 IF Store (preparation for entirely new approach) Sven Stucki 2015-08-25 15:06:00 +02:00
  • 96b5d1940d Fix issue with cross line access and stalls, cleanup Sven Stucki 2015-08-25 01:19:54 +02:00
  • 08f2311745 Fix ack latching for jumps/branches Sven Stucki 2015-08-24 06:11:14 +02:00
  • 6f5367478f Fix ack handling in IF Sven Stucki 2015-08-24 03:49:15 +02:00
  • 67425b0f19 Fix LUI/AUIPC output of tracer Sven Stucki 2015-08-24 03:06:11 +02:00
  • 94aef4ec05 Small cleanup Sven Stucki 2015-08-22 14:21:01 +02:00
  • 0da283fb58 Fix instruction corruption issue in IF Sven Stucki 2015-08-18 17:49:37 +02:00
  • 0042daa8c9 Fix jump/branch problem in IF Sven Stucki 2015-08-17 23:03:06 +02:00
  • 4d02dc1490 Simplify instruction masks in defines Sven Stucki 2015-08-17 22:46:14 +02:00
  • bd6e0d4d05 Small IF cleanup, add defines for branch types Sven Stucki 2015-08-17 20:51:48 +02:00
  • a08f53928a Fix basic incr PC flow, ID PC miscalculation Sven Stucki 2015-08-17 05:13:38 +02:00
  • 0addc4f1bd IF stage sync. Sven Stucki 2015-08-17 00:07:16 +02:00
  • a91cc2f0cb Remove some garbage Sven Stucki 2015-08-10 15:52:43 +02:00
  • 80ca650893 Intermediate commit, trying out some things Sven Stucki 2015-08-10 04:29:10 +02:00
  • 8e26797549 Add control FSM to IF stage Sven Stucki 2015-08-05 03:19:29 +02:00
  • 1f1ea049f4 Rename signals in instr_core_if Sven Stucki 2015-08-03 16:12:46 +02:00
  • 5ede08fc29 Remove instr_core_if and rewire I$ directly to IF stage Sven Stucki 2015-07-31 02:04:37 +02:00
  • e9d3ab56b7 Remove dead signals Andreas Traber 2015-08-17 15:19:48 +02:00
  • aaf3aca410 Fuse dbg fsm and main control fsm => less FSMs :-) Andreas Traber 2015-08-17 15:15:46 +02:00
  • f535f79bd8 Separate controller and decoder Andreas Traber 2015-08-17 14:53:34 +02:00
  • 39daf53892 Move debug from CS registers to debug unit as they do not need to be accessible from the core anyway Andreas Traber 2015-08-14 16:31:03 +02:00
  • 73dd948f59 Working on debug support Andreas Traber 2015-08-10 17:00:02 +02:00
  • 102691a06a Improve instruction tracer (added cycle count, formatting) Sven Stucki 2015-08-06 14:16:41 +02:00
  • 69b2473daa Fix instruction trace displaying immediates wrong Sven Stucki 2015-08-06 02:39:50 +02:00
  • 7c211e0da5 Fix constant names Sven Stucki 2015-08-03 15:21:48 +02:00
  • 55f211ab0a Cleanup defines Sven Stucki 2015-08-03 15:00:01 +02:00
  • 4ec8c090ad Add post-increment and reg-reg stores Sven Stucki 2015-07-31 01:39:51 +02:00
  • 57edf30a46 Minor controller cleanup Sven Stucki 2015-07-28 15:04:28 +02:00
  • b4768564ce Added post increment loads, reg-reg loads and post-increment reg-reg loads Sven Stucki 2015-07-28 14:58:14 +02:00
  • a1b4551804 Four more compressed instructions Sven Stucki 2015-07-24 18:24:18 +02:00
  • d9b75c2ec0 Added vim swap file Sven Stucki 2015-07-24 15:26:32 +02:00
  • bb2fbf8e54 Updated all file headers Sven Stucki 2015-07-24 15:26:12 +02:00
  • 10bc98382e More cleanup, fixed more warnings Sven Stucki 2015-07-24 02:53:55 +02:00
  • f908f34fcf More warnings fixed Sven Stucki 2015-07-23 02:30:44 +02:00
  • da7c740870 Fixed Verilator width warnings where appropriate Sven Stucki 2015-07-23 01:59:45 +02:00
  • 186245bc49 Cleanup; removed carry and overflow (mostly) Sven Stucki 2015-07-23 01:20:57 +02:00
  • 509c13dff8 Another compressed instruction, include guards for verilator Sven Stucki 2015-07-21 17:57:49 +02:00
  • 45f23be416 Even more compressed instructions Sven Stucki 2015-07-16 17:35:49 +02:00
  • 4289008afe Added 6 more compressed instructions Sven Stucki 2015-07-16 01:46:29 +02:00
  • a1430b3394 Fixed typo/error in ex stage from last commit Sven Stucki 2015-07-14 02:05:13 +02:00
  • 7a34cde770 Removed flag from signal and handling from core (still in ALU) Sven Stucki 2015-07-14 01:53:10 +02:00
  • 0d59ca91d9 More compressed instructions and fixes for existing ones Sven Stucki 2015-07-10 12:14:02 +02:00
  • 5c93a289ea Fixed warning in id_stage Sven Stucki 2015-07-10 12:13:38 +02:00
  • 274901090c Added default case to RISCV main controller, fixed indentation Sven Stucki 2015-07-10 12:10:17 +02:00
  • ce7f33aee8 Improved tracer output for loads Sven Stucki 2015-07-10 12:09:06 +02:00
  • f11858a8d8 Major RiscV update, now supports compressed instructions (partially, work-in-progress until full standard is released) Sven Stucki 2015-06-12 19:21:46 +02:00
  • aa1821ba2d Fixed inferred latches in RV Sven Stucki 2015-06-05 12:23:35 +02:00
  • b9e0bd9cbd Fixed missing signal declaration in id_stage Sven Stucki 2015-06-01 01:14:38 +02:00
  • 60a842c81d Added all RiscV CSR manipulation instructions, major update and cleanup Sven Stucki 2015-06-01 01:01:33 +02:00
  • c0c5b5f8a1 RiscV: exception controller and CSR core and synthesis update Sven Stucki 2015-05-26 00:08:28 +02:00
  • 01caa041c4 Realigned RiscV with Or10n, code cleanup Sven Stucki 2015-05-24 23:04:08 +02:00
  • 72147fceed RiscV update with preliminary exception support, added multiplier and all the other things that didn't survive the GIT reorg Sven Stucki 2015-05-20 17:54:00 +02:00
  • 29012978d7 Fixed bug in branch code, wrong vector size Sven Stucki 2015-04-21 13:31:26 +02:00
  • ff712bf367 Improved instruction tracer, added custom instruction for core id Sven Stucki 2015-04-20 11:21:02 +02:00
  • 43ccb41536 Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0 Sven Stucki 2015-04-19 02:34:43 +02:00
  • 10d9a75f27 Fixed space/tab mixture and indentation in instr_core_interface Sven Stucki 2015-04-16 15:21:03 +02:00
  • af8b208029 Fixed Jumps and Branches (jump target now calculated in ID, up for debate) and some general code cleanups Sven Stucki 2015-04-15 18:27:51 +02:00
  • c974349bbc Fixed indentation in riscv_core (partially), some changes for to fix jumps/branches Sven Stucki 2015-04-14 14:38:49 +02:00
  • 902badaf3b Added BRANCH support Sven Stucki 2015-04-13 16:08:27 +02:00
  • 20b51d01b4 Added instruction tracer to riscv core Sven Stucki 2015-04-10 16:03:16 +02:00
  • c9a0ffdc7d JAL working Sven Stucki 2015-04-09 16:09:37 +02:00
  • 6d8d6287b4 Moved LSU addr calculation out of ALU into EX stage Sven Stucki 2015-04-08 12:59:22 +02:00
  • 5d96d3e7a1 Started implementing JAL/JALR target calculation in ALU, improved a few defaults Sven Stucki 2015-04-07 18:35:20 +02:00
  • d7e8aba2f9 Fixed JAL/JALR instruction check, added pretty print function for invalid instructions Sven Stucki 2015-04-07 18:15:50 +02:00
  • 85d2632a38 Additional code cleanup and defines Sven Stucki 2015-04-07 16:42:34 +02:00
  • 5e4db58f21 Code cleanup in ID stage Sven Stucki 2015-04-07 16:40:45 +02:00
  • a960d85c9e Fixed indentation in controller (1 level = 2 spaces) Sven Stucki 2015-04-07 16:39:28 +02:00
  • a3bce7cb91 Added loads to CPU Sven Stucki 2015-04-02 10:32:58 +02:00
  • a6d67016ac Initial RiscV core commit; still in an early stage, but ALU instructions work Sven Stucki 2015-04-01 11:11:07 +02:00