The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Andreas Traber 847b652ce5 Change IF fifo depth to 3 to get performance from old IF back		2015-09-10 13:12:19 +02:00
docs/datasheet	Add a basic datasheet for RI5CY	2015-09-09 18:35:07 +02:00
include	Add performance counter for compressed instructions	2015-09-08 17:24:39 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Use 'x to simplify synthesis	2015-09-02 09:25:06 +02:00
compressed_decoder.sv	Prefetcher basically done, works in pulpino without rvc	2015-09-10 13:12:19 +02:00
controller.sv	Add performance counter for compressed instructions	2015-09-08 17:24:39 +02:00
cs_registers.sv	Add performance counter for compressed instructions	2015-09-08 17:24:39 +02:00
debug_unit.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
ex_stage.sv	More cleanup, remove unused signal	2015-09-05 16:33:51 +02:00
exc_controller.sv	Cleanup ID	2015-09-05 16:00:41 +02:00
hwloop_controller.sv	Finish hwloops addition	2015-09-07 03:40:28 +02:00
hwloop_regs.sv	Cleanup unneeded signals and dead code	2015-09-02 18:07:44 +02:00
id_stage.sv	Move compressed decoder/expander to IF stage	2015-09-08 19:33:10 +02:00
if_stage.sv	Prefetcher basically done, works in pulpino without rvc	2015-09-10 13:12:19 +02:00
instr_core_interface.sv	Change IF fifo depth to 3 to get performance from old IF back	2015-09-10 13:12:19 +02:00
load_store_unit.sv	Move LSU related signals out of ex_stage and alu and put them inside LSU	2015-09-02 08:55:44 +02:00
mult.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
register_file.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
riscv_core.sv	Move compressed decoder/expander to IF stage	2015-09-08 19:33:10 +02:00