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Author	SHA1	Message	Date
Rose Thompson	be7aeab3bc	tcl cleanup.	2025-05-30 13:33:35 -07:00
Rose Thompson	810ce4e774	Updated comments in fpga top level.	2025-05-30 13:11:38 -07:00
Rose Thompson	56826c9e51	Increased genesys 2 clock speed to 40MHz!	2025-05-30 13:06:26 -07:00
Rose Thompson	23c0c751da	Holy smokes! first try and I got the genesys2 board running!	2025-05-30 11:52:53 -07:00
David Harris	19a26cfbd0	Merge pull request #1436 from jordancarlin/fix_riscof ... Update Sail config files	2025-05-28 05:46:19 -07:00
Jordan Carlin	9b1964e928	Update Sail config files	2025-05-27 20:51:13 -07:00
Jordan Carlin	516bc91e9e	Merge pull request #1435 from jacassidy/newmain ... Updated Riscof Makefile so that it doesn't give invalid reports	2025-05-27 18:28:11 -07:00
jacassidy	70b9384068	changes to fix makefile for riscof and run vector excpetions coverage	2025-05-27 18:24:16 -07:00
David Harris	1c0fb856e7	Merge pull request #1427 from georgiatai/devcvw ... Changes in wally, sail, and spike config to support vector verification	2025-05-27 08:40:43 -07:00
David Harris	e0af0e68a3	Merge pull request #1416 from coreyqh/ccov ... otherpagefault ccov hole covered	2025-05-27 03:07:06 -07:00
David Harris	f87b036bc1	Merge pull request #1428 from jordancarlin/installation_fixes ... Fix Verilator installation on Ubuntu 20.04 and Debian 11	2025-05-24 03:36:35 -07:00
Jordan Carlin	2f2edc8743	Pin Verilator to v5.036 on Ubuntu 20.04 and Debian 11 to fix installation issue	2025-05-24 00:37:32 -07:00
Jordan Carlin	c7f115c3dd	Remove workaround for riscv-gnu-toolchain shallow clone	2025-05-24 00:36:37 -07:00
Jordan Carlin	04480c01b7	Fix color in setup.sh script	2025-05-24 00:30:42 -07:00
Georgia Tai	10648e9ccb	spike update	2025-05-22 13:12:22 -07:00
Georgia Tai	634ac3322b	config changes for all vector sew suites	2025-05-22 13:08:54 -07:00
Georgia Tai	e96eb3a95d	riscof and config changes to support vector	2025-05-22 13:06:49 -07:00
David Harris	11a62233a4	Merge pull request #1426 from jordancarlin/gcc15 ... Fix compilation with GCC 15	2025-05-20 16:09:21 -07:00
Jordan Carlin	916233e789	Fix embench compilation with gcc 15	2025-05-20 15:19:36 -07:00
Jordan Carlin	15a0d7dde9	Fix zsbl compilation with GCC 15	2025-05-20 15:19:05 -07:00
David Harris	56e6749eec	Merge pull request #1411 from rosethompson/main ... Fixes Misalgined Instruction Page Fault	2025-05-14 10:46:55 -07:00
David Harris	b7bca76be8	Merge pull request #1421 from jordancarlin/egrep ... Replace egrep with grep -E for better compatibility	2025-05-14 02:36:49 -07:00
Jordan Carlin	0c3a60aeae	Replace egrep with grep -E for better compatibility	2025-05-14 01:31:30 -07:00
David Harris	be7f6be5a7	Merge pull request #1420 from jordancarlin/fpu_test_fix ... Workaround binutils 2.44 objdump 6-byte instruction bug in fpu.S coverage test	2025-05-13 20:17:15 -07:00
Jordan Carlin	42989867de	Workaround binutils 2.44 objdump 6-byte instruction bug in coverage/fpu.S	2025-05-13 17:42:08 -07:00
Jordan Carlin	6bee068779	Makefile cleanup	2025-05-13 16:07:39 -07:00
David Harris	c06054f888	Merge pull request #1418 from jordancarlin/new_riscof ... Fix riscv-config isa yaml for compatability with latest RISCOF for PMPs	2025-05-13 04:22:25 -07:00
Jordan Carlin	d2350c6ec1	Install latest version of riscv-config from git	2025-05-13 01:03:30 -07:00
Jordan Carlin	544f3b4af9	Fix riscv-config isa yaml for compatability with latest RISCOF for PMP	2025-05-13 00:55:56 -07:00
David Harris	24c605a9fc	Merge pull request #1415 from jordancarlin/sail_coverage ... Functional coverage from Sail + Update Sail version	2025-05-11 05:30:52 -07:00
Corey Hickson	a3a3c18052	otherpagefault ccov hole covered	2025-05-10 19:35:15 -07:00
Jordan Carlin	cf25dcea09	Fix cvw-arch-verif version	2025-05-10 17:03:32 -07:00
Jordan Carlin	ee961021d6	Restore deleted pmp test	2025-05-10 17:01:35 -07:00
Jordan Carlin	602cc42b03	Enable more tests in Sail	2025-05-10 16:55:47 -07:00
Jordan Carlin	2b1569a281	Enable lots of rv64 wally-riscv-arch-test tests to run in Sail	2025-05-10 16:48:50 -07:00
Jordan Carlin	4f1e602c7c	Reenable rv64 misalign tests for real	2025-05-10 16:27:53 -07:00
Jordan Carlin	531c8752f7	Fix riscof configs	2025-05-10 16:21:57 -07:00
Jordan Carlin	c6de5ce0bf	Merge pull request #1403 from SadhviNarayanan/version2 ... Cache Validation integrated into regression-wally	2025-05-10 16:14:59 -07:00
SadhviNarayanan	df1a787c60	removed rv64gc python cache script, updated testbench.sv	2025-05-10 13:36:10 -07:00
Jordan Carlin	f549ee3df7	Update Sail config files	2025-05-10 12:27:55 -07:00
SadhviNarayanan	75dcf6801c	revert cvw-arch-verif submodule push	2025-05-10 10:24:17 -07:00
SadhviNarayanan	3b058ed4bf	minor code changes and optimizations	2025-05-10 10:21:47 -07:00
Jordan Carlin	5ced604974	Bump cvw-arch-verif version	2025-05-09 17:41:14 -07:00
Jordan Carlin	c234aebefb	Fix coverage collection	2025-05-09 17:40:57 -07:00
Jordan Carlin	922c0d7171	Misaligned tests still mismatch with Sail	2025-05-09 17:08:40 -07:00
Jordan Carlin	012272b9c4	Only run coverage for cvw-riscv-arch-test tests	2025-05-09 17:03:09 -07:00
Jordan Carlin	71d52bc6dc	Update to new version of Sail	2025-05-09 16:12:29 -07:00
Jordan Carlin	3b0f763674	Update to work with new version of Sail	2025-05-09 15:43:31 -07:00
Jordan Carlin	af7c219e37	Don't build rv32e	2025-05-09 14:55:18 -07:00
Jordan Carlin	d2ea9a58da	Generate coverage report for riscof makefile	2025-05-09 14:47:23 -07:00