- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This commit makes the BASE field of the `mtvec` CSR writable to
allow changing the trap-vector base address at runtime without
changing the boot address input. Similar to the boot address,
the trap-vector base address must always be aligned to 256 bytes.
At bootup, the trap-vector base address is initialized to the boot
address.
This commit resolveslowrisc/ibex#118.
Most of this work has been done by @ivanmgribeiro as part of
lowrisc/ibex#193.
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This commit adds the `mip` and `mie` CSRs as well as the software,
timer and external interrupts.
Currently these interrupts are overlapped with some of the legacy
interrupts, i.e., the core will jump to the same address for different
interrupts. For example, the software interrupt has the same ID as
legacy interrupt #3. Thus, the handler must read the `mip` register
to find out whether the interrupt routine has been entered because of
the software interrupt or the legacy interrupt.
Eventually, the number of legacy interrupts will be reduced to avoid
this overlapping, and they will be connected to the `mie` and `mip`
CSRs directly.
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
The RVFI implementation make use of signals from the decoder and
controller to detect the state of the processor.
Especially the signal for a new and retired instruction.
This commit moves the generation of these signals into the ID stage
to generate it with more accurate timing. More precisely, an
instruction is now considered as retired once it has been completely
executed and not once the next instruction is pushed into the IF-ID
pipeline register.
Also, it no longer depends on whether the instruction was valid or
illegal. For RVFI and the tracer, also illegal instructions must be
considered.
Once the core is executing, the IF stage now only gets two signals
from the controller: One to clear the instruction valid output and one
to prevent the IF stage from pushing new instructions.
The former `if_valid_o` of the IF stage has been renamed to clarify
that this is not a valid bit but just the write enable for the
pipeline register.
This commit cleans up the LSU and fixes two bugs:
1. If a misalgned transaction creates an error during the first
part of the transaction, the second part is not pushed out and
the transaction is aborted. Previously, the LSU tried to output
also the second part but did not adhere to the defined
protocol.
2. Misaligned operations are again working correctly. Previously,
the generation of the byte enable and the alignment of read
data was broken as these operations rely on the updated
address from the AGU to have the same alignment as the
original address.
This partially resolves#121.
This commit moves logic directly related to the decoder from the ID
stage into the decoder. This logic includes:
- Generation of immediates and decoder-based mux selectors
- Generation of register file addresses
- CSR operand check and manipulation depending on value in `rs1`
- Register file address check for RV32E (still disabled)
The muxes themselves stay in the ID stage as their control signals also
depend also on other, non-decoder-based signals (LSU, EX, WB FSM).
These signals do not need to be generated by the WB FSM inside the ID
stage and be fed back into the decoder. They simply depend on whether
the instruction is new (we execute for the first cycle) or not.
The EX block actually signals when its output is valid, and not when it
is ready to accept new input. The LSU valid signal is not needed inside
the EX block and can thus be fed directly to the ID stage.
For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.
Interrupts are handled in vectored mode as before.
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
Performance counters are an optional feature. Disable them by default to
avoid users having them enabled unknowingly and paying the (rather
large) area price for it.
Generate signals for RISC-V Formal Verification.
Output of signals is partially delayed to get values before and after
the completion of an instruction.
The timing of the output is based on the detection of a retired
instruction. This change is detected on changes of the instruction
code itself, changes of the program counter and the valid signal.
The compressed instruction is forwarded because the decoder maps the
compressed instruction into the corresponding uncompressed instruction,
but the original instruction is needed to detect the correct format.
Register output based on the requirements from RVFI.
This commit adds checks to CSR accesses. If a CSR is accessed that is not
implemented, or if a read-only CSR is written to, an illegal instruction
exception is caused.
This commit adds the CSRs `mcycle(h)`, `minstret(h)`, `mcountinhibit` and
mhpmcounter3(h) - mhpmcounter31(h) as well as `mphmevent3 - mhpmevent31`.
The registers `mphmevent3 - mhpmevent31` are hardwired and cannot be
reconfigured.
The core ignores the lowest byte of the boot address and thus does not
support booting from addresses not aligned to 256 bytes. This commit
updates both the documentation accordingly and adds an assert to the
IF stage.
In case of interrupts, `exc_cause` carries the interrupt ID in the lower
bits and its MSB is 0 anyway. There is no need to forward only the lower
bits to the IF stage.
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
be set through command-line flags to the simulation/synthesis tools.
Initial version by Nils Gräf.
