This commit fixes the generation of the exception cause ID for fast
interrupts. Without this commit, the core tries to handle fast
interrupts using the handlers of other interrupts like external,
software, and timer interrupts.
This commit resolveslowRISC/ibex#290 reported by @udinator.
- See issue #265 (partially fixes)
- Remove path from instr_rvalid_i to instr_req_o
- Prefetch buffer unit can now issue up to two outstanding requests
- Structure moved from state machine to request queue
- Change fetch fifo to use an unaligned flag rather than updating
the address each time
- Relates to issue #265
- External signals data_rvalid_i and data_err_i were factored
into the external data_req_o signal
- To improve timing, these signals are decoupled
- The second part of an unaligned transaction will now be issued
even if the first received an error response
- The state machine will service the abandoned requests
- pmp_err_q fixed to only update at specific times
- The RISC-V Debug Spec v.0.13.2 (p.41) mandates that the core
debug CSRs dcsr, dpc, dscratch0 and dscratch1 must not be
accessible if not in debug mode. Fixes#275
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
Executing a DRET instruction outside of debug mode now causes an
illegal instruction exception as mandated by the Debug Spec v0.13.2
p.41.
This resolveslowRISC/ibex#270.
We currently have a documentation block at the beginning of each file,
containing author credits and module-level documentation. The
module-level documentation is retained for historic reasons and
duplicated with the newer comments below it.
For the authors, maintaining author credits in the file is error-prone,
as this information gets outdated very soon. A more reliable way to see
who modified a file is to use the history information in git.
Additionally, we now have the CREDITS.md file, which lists all
contributors, even the ones which don't appear in the git history (e.g.
because the code was copied and commited by someone else).
This file lists all code contributors to Ibex as of today, and
acknowledges the great work done by the PULP team at ETH Zürich.
The names in this file have been compiled from the git history, and all
authors which are named in the individual source files.
This sets up Azure Pipelines to run the following two tasks:
- Run Verilator lint on the SystemVerilog code.
- Run the RISC-V compliance test suite for RV32IMC
This commit clarifies why CSR-related pipeline flushes are needed
(e.g. when enabling interrupts), only introduces them when doing the
critical modifications (write/set bits in `mstatus` and `mie` CSRs
for enabling interrupts, reads and clears are uncritical for these
CSRs), and makes sure the controller is actually able to start
handling interrupts while doing a CSR-related pipeline flush.
This resolveslowrisc/ibex#6.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 07599f689a385794cb73932922008bdbe8131d82
* Fix introduced TypeError in run.py (Udi)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e905e9f134e0b7cf7da491218d1a30c75ce8649a
* add pass_val and fail_val into csr test flow for EOT correctness
checking (Udi)
* Support unaligned load/store (Tao Liu)
* refactored test generation logic (Udi)
* refactored test generation logic (Udi)
* Give error when mutually exclusive between -co, and -so argument
(dang hai)
* documentation, and small fixes (Udi)
* no_iss bug (Udi)
* no_iss/no_post_compare optional, CSR read_only is now only specified
at field level granularity (Udi)
* made no_iss optional (Udi)
* rm print (Udi)
* setup_logging call (Udi)
* undo overriding --verbose in run.py, comment cleanup in csr gen
script (Udi)
* missed verbose arguments (Udi)
* verbose arg (Udi)
* updated csr description, integrated csr test into flow (Udi)
* updated csr description, integrated csr test into flow (Udi)
* Enhance verbose information by logging instead of using print (dang
hai)
* Report date time for output directory (dang hai)
* Add main entry point for run.py (dang hai)
* Separate command line parser by function (dang hai)
* Skip generating S/U mode program for machine mode test (Tao Liu)
* minor update to README.md (Tao Liu)
* Update the README.md to match command reference from --help (Tao
Liu)
* Ignore untrack file from python script (dang hai)
* Make questa work for new YAML based regression flow (dang hai)
* Fix typo in README (Tao Liu)
* Fix README google/riscv-dv#54 (Tao Liu)
* changed formatting of generator option table (Udi)
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
