When an exception occurs controller goes into the flush state and then
does a pc_set to go the exception handler. So there is no need for the
incoming signals that indicate an exception to factor directly into
pc_set_o. This flops exc_req and illegal_insn to break long timing
paths that were occurring because of this.
Fixes#305
When an instruction that caused an exception occurred the controller
would clear the instr_valid bit but rely on the instruction bits staying
in the ID register so it could still use them in the FLUSH state to
decide what to do. This reworks the control logic slightly so
instr_valid remains asserted when the controller goes into the FLUSH
state so relevant signals can be qualified with the instr_valid bit.
There were no known functional issues caused by the previous behaviour
however this gives a more robust approach.
Update code from upstream repository https://github.com/google/riscv-
dv to revision d3419444ca2fdb499a204587b2d36c6f5c1e0c44
* Update README (Udi)
* Add knob to enable full CSR randomization, fix mstatus.spp (Udi)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e3e1e308cfc3d718aeb94bb3463371979d9a31ae
* Disable full trace in the run script (google/riscv-dv#180) (taoliug)
* Fix spike logging issue (google/riscv-dv#179) (taoliug)
* Add functional coverage for HINT instructions (google/riscv-dv#177)
(taoliug)
* Add functional coverage for various hazard conditions (google/riscv-
dv#176) (taoliug)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44505927a70a6234b996d15f2e51bd1e2632b68e
* Dump performance counters to testbench at EOT (Udi)
* Fix a constraint issue (google/riscv-dv#174) (taoliug)
* Allow split a long test to small batches (google/riscv-dv#173)
(taoliug)
* Fix ius compile problem (google/riscv-dv#172) (taoliug)
* Add basic functional coverage for RV64IMC (google/riscv-dv#171)
(taoliug)
* Initial prototype of functional coverage (google/riscv-dv#169)
(taoliug)
The syntax of this statement is not correct without the `$fatal()` SV
construct. This causes errors in some tools even if the error condition
is not met.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 80d429475138b4b94d863030246a06980c89889d
* Fix mstatus randomization issue (google/riscv-dv#168) (taoliug)
* Lower the percentage of JAL instruction (google/riscv-dv#167)
(taoliug)
* Add an option to run a directed assembly test with ISS
(google/riscv-dv#166) (taoliug)
* Add memory fault handlers (Udi)
Give higher priority to data accesses from the CPU to improve
performance. This is the recommended setup for Ibex.
The test utility host needs still higher priority, otherwise the CPU
takes all bus capacity (the downside of strict priority arbitration).
Previously, verilated_toplevel.h contained a macro, VERILATED_TOPLEVEL()
to produce a class TOPLEVEL (whatever the toplevel happens to be). This
required all compilation units referring to that TOPLEVEL class to call
the macro.
After this change, the class is always generated in
verilated_toplevel.h. For that to work, a new define TOPLEVEL_NAME must
be globally set (e.g. passed to the compiler with -DTOPLEVEL_NAME=xxx).
- Fixes#288
- Add missing grant qualification to stop incorrect address updates
- Make RTL robust to spurious rvalid signalling
- Make sure a request is held until granted
- Remove incorrect assertion
Without this commit, the `nmi_mode` register is continuously cleared and
set again, and the core can never handle the NMI.
This resolveslowRISC/ibex#300 reported by @udinator.
