The RVFI implementation make use of signals from the decoder and
controller to detect the state of the processor.
Especially the signal for a new and retired instruction.
* Controller: remove impossible condition for `DBG_TAKEN_IF`
There is no way to jump into `DBG_TAKEN_IF` because of an EBREAK
instruction. Thus, this case also does not need to be checked.
* Controller: do not enter debug when `debug_req_i` goes low
With this commit, the core is prevented from entering debug mode when
the debug request signal is deasserted during that procedure.
Previously, the core would still enter debug mode but not updating the
debug CSR.
This resolves#153 reported by @taoliug.
* Update ibex_controller.sv
The FSM now uses input signals for interrupt and debug request handling
that depend on whether the core is in debug mode. This avoids the need
for many `debug_mode_q` guards and somewhat simplifies the FSM.
If in debug mode, the core shall not handle interrupts according to the
spec anyway.
This commit moves the generation of these signals into the ID stage
to generate it with more accurate timing. More precisely, an
instruction is now considered as retired once it has been completely
executed and not once the next instruction is pushed into the IF-ID
pipeline register.
Also, it no longer depends on whether the instruction was valid or
illegal. For RVFI and the tracer, also illegal instructions must be
considered.
Previsouly, the regfile write enable output of the decoder was always
fed through the WB FSM which is unnecessary except for stores and
mult/div operations.
Once the core is executing, the IF stage now only gets two signals
from the controller: One to clear the instruction valid output and one
to prevent the IF stage from pushing new instructions.
The former `if_valid_o` of the IF stage has been renamed to clarify
that this is not a valid bit but just the write enable for the
pipeline register.
The register file shall not be written upon illegal CSR operations
and when the core is idle (waiting for new instructions). Otherwise
the write enable signal from the WB FSM/decoder is used.
Single stepping should execute exactly one more instruction, not abort
any running (multicycle) instructions, and only enter debug mode after
the current instruction is finished. In case the current instruction
leads to an exception, the exception registers must be set accordingly,
but the core must jump into debug mode instead of the exception
handler.
Previous to this commit, single stepping would immediately jump into
debug mode and ignore any exceptions.
This commit makes sure that interrupts and debug requests do not
interrupt currently running multicycle instructions. Priority is
given 1) to the currently running instruction, possible exceptions
caused by this instruction, 2) debug requests, 3) interrupt
requests.
Previously, currently running instructions were aborted upon
incoming debug and interrupt requests, which could corrupt the
processor state and lead to exceptions being ignored.
This commit resolves#108 and #121.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 949552f964eec9d058c7c90889bdd5b80d1e60ad
* Merge pull request #33 from google/dev (taoliug)
* Add control for the privileged CSR checking (Tao Liu)
* Merge pull request #32 from google/dev (taoliug)
* Fix minor issue in comparing script (Tao Liu)
It is not necessary to do this check in the compressed decoder. If a
compressed instruction in RV32E tries to access any register x16 - x31,
the regular decoder triggers an illegal instruction exception and the
controller writes the actual faulting (compressed) instruction to
`mtval`.
To make the regfile address check in RV32E not triggering false alarms
when accessing reg x16 - x31, the decoder should only set the muxes
for the regfile output when the instruction actually requires the
regfile output.
It is cleaner to explicitly set the `alu_op_x_mux_sel` signals to
`OP_X_REG_X` instead of relying on the default assignment if they
are really needed.
This commit cleans up the LSU and fixes two bugs:
1. If a misalgned transaction creates an error during the first
part of the transaction, the second part is not pushed out and
the transaction is aborted. Previously, the LSU tried to output
also the second part but did not adhere to the defined
protocol.
2. Misaligned operations are again working correctly. Previously,
the generation of the byte enable and the alignment of read
data was broken as these operations rely on the updated
address from the AGU to have the same alignment as the
original address.
This partially resolves#121.
This commit moves logic directly related to the decoder from the ID
stage into the decoder. This logic includes:
- Generation of immediates and decoder-based mux selectors
- Generation of register file addresses
- CSR operand check and manipulation depending on value in `rs1`
- Register file address check for RV32E (still disabled)
The muxes themselves stay in the ID stage as their control signals also
depend also on other, non-decoder-based signals (LSU, EX, WB FSM).
