Some commands utilise a logfile argument, while others capture the stdstreams
into a file. Discard the stdout/stderr when a logfile argument is used.
This keeps the logs readable.
This commmit enables parallelism of more steps of the dv process by capturing
the commands generated by the riscv-dv tool, then populating and executing a
sub-makefile. This allows us to have parallelism at the level of the makefile
jobserver.
Seperated instr_gen build and run steps
A python script construct_makefile.py is used to capture the raw output commands
and construct a trivial makefile for each stage.
This commit also renames some of the helper variables and stamps for consistency.
- Every line in a recipe must start with a tab, except wrapping lines of dependencies.
- Wrapping dependencies of a target use only spaces. Use two spaces by default.
Vivado gives synthesis error complaining about assignment of irq_nm_int_cause to '0 by saying it is an enum type.
Change the assignment to NMI_INT_CAUSE_ECC, which is defined to 5'b0 in ibex_pkg.sv
The prefetch buffer and icache both treat the branch_i and
branch_mispredict_i signals identically, so it's a bit cleaner to pull
that treatment up into ibex_if_stage.sv
This commit doesn't change the modules below: it just passes zeros for
the "mispredict" version. Removing those ports will be done in a
follow-up commit.
An internal interrupt triggers an NMI. A single one is implemented, one
on integrity errors being seen in load data. This replaces a synchronous
exception on an integrity error which caused timing issues.
It turned out that with the default value of 1, Vivado infers a separate
18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA
examples. This can be very wasteful in terms of resource utilization
especially for smaller configurations.
As our examples don't use ECC or parity and mainly target simualation
and FPGA, it's better to use a value of 8 for the DataBitsPerMask
parameter. Vivado will then not distribute words across different BRAM
instances which results in more efficient FPGA resource utilization.
For a detailed analysis and explanation, please refer to
lowRISC/Ibex#1587.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision cb4295f9ce5da2881d7746015a6105adb8f09071
* Update list search (Matthew Ballance)
* Trap and report exceptions encountered in sub-processes and
propagate error back (Matthew Ballance)
* Workaround fix for loop test colon issue (aneels3)
* Fix typo (aneels3)
* Add support for RV64AFD (aneels3)
* Fix typo (aneels3)
* Update README.md (aneels3)
* Add support for sub_programs (aneels3)
* fix issue with imm value for 64 bit instr (aneels3)
* Allow for underscores and capital letters in ISA for ISS (Pirmin
Vogel)
* implement rv64i (shrujal20)
* Add support for RV32FD coverage (aneels3)
* Integrate random seed for pyflow (aneels3)
* Add riscv_loop_test (ShraddhaDevaiya)
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This is necessary for having VCS support with simple system example.
Because in the ibex_simple_system_main.cc we are including some
Verilator exclusive header files.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit adds ibex_icache_ram_if to connect between DUT and tag /
data RAMs.
This interface injects 1 or 2 bit error on rdata if enable_ecc_errors
bit is set. It also checks that ecc_err_o pin is asserted by DUT
whenever an ecc error is injected.
ibex_icache_ecc_vseq and ibex_icache_base_vseq have been modified to
inject ecc errors through the ram interface.
Fixes a bug where both Xcelium and Python open the same sim.log file and race to
write the simulation results into it. This change makes Python the sole writer of this
file using the captured stdout/stderr from the subprocess.run call in
run_rtl.py.
This bug was also previously present for VCS but was fixed in 90ff7ca6c.
Added coverpoint and cross names to relevant plan entries so plan is up
to date with implemented coverage. Also some minor changes to remove
plan entries that are no longer required.
This groups the various different illegal instructions categories within
ibex_id_stage rather than spreading them between ibex_id_stage and
ibex_controller.
This commit removes extra hierarchy of ic_top inside icache TB and moves
the scrambling request generation logic and instantiation of data and
tag RAMs to tb.
This commit adds a new scrambling agent to drive scrambling key and
valid to the data and tag memory interfaces.
Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5
Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
Earlier the design supported single clock cycle error responses from PMP
block whenever a read was done from blocked memory. Now there is at
least one clock cycle delay after the request has been granted for the
error to be asserted. Therefore, this commit removes the support for
single clock cycle PMP error response.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
7c4f8b3fde4bb625ac3330ff52d3f66507190fe5
Please note that we're adding push_pull_agent for the first time in this
commit.
Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
There was issue with rtespect to calculating number of instructions per
word and this commit fixes that issue.
Number of instructions per word = 1/4*1 + 3/4(1/4*3/2 + 3/4*2) = 53/32.
Earlier th5s was calculated as 7/4.
Ideal window length needed to calculate fetch ratio percentage is
calculated as 53/32*C*2 = 848. Earlier it was calculated to be 300.
Previously integrity checks for incoming memory reads and integrity
generation for outgoing memory writes were handled within ibex_lockstep
and weren't duplicated.
This moves the integrity checks and generation into the core so they are
replicated and checked as part of the lockstep mechanism.
Additionally it generates a bus error on any memory integrity check
failure. This will result in Ibex taking an exception if any data read
or instruction fetch has bad integrity.
