github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 12:57:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
2477 commits 21 branches 8 tags 70 MiB
Commit graph

2477 commits

This branch
This branch
All branches
Author SHA1 Message Date
Harry Callahan
5bba52713f Fix randomize bug, add assertion for cnt != 0 2022-07-15 12:45:42 +01:00
Harry Callahan
806989a745 Commenting UVM testbench code, tidy formatting, minor refactoring 
- Adds comments for quicker explanation of test and library functionality
- Refactor types and naming of control knob signals for clarity
- Move constraints from MEMBER to CLASS for more flexibility
- Add missing license header

Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
 2022-07-15 12:45:42 +01:00
Marno van der Maas
3459d7f8df [lint] Remove whitespace from non-vendored source files 
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
 2022-07-14 15:59:34 +01:00
Canberk Topal
7ba6667f32 [dv] Check privilege after DRET 
Timing fix for dret_test and modelling controller behaviour for FLUSH transition.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-07-12 18:02:02 +03:00
Greg Chadwick
ab510f8acf [dv/doc] Tweaks/fixes to functional coverage 
This fixes up some minor issues in the functional coverage plan and
implemented cover points
 2022-07-11 12:10:55 +01:00
Canberk Topal
5c49fad9a2 [fcov] Adding debug related functional coverage 
Includes coverpoints for:

- Hardware trigger point matches
- Debug simple step entrance in controller
- Seeing different insns while single stepping

Also updates on coverage plan to fill up missing mentions of
coverpoints/crosses

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-06-29 16:02:53 +03:00
Timothy Chen
31531f7325 Update crash dump to contain mtval 
- mtval is a bit more useful for double fault situations
  as on the second exception we can still "remember" the
  data address and PC of the first exception.

Signed-off-by: Timothy Chen <timothytim@google.com>
 2022-06-16 07:58:19 -07:00
Harry Callahan
81590d86c2 Fix multi-line string formatting in $sformatf for uvm_fatal macro 
Before the change the indentation of the second line would be printed as spaces
in the fatal message.
 2022-06-09 16:34:08 +01:00
Harry Callahan
15230d2c86 Subprocess timeout feature 
Sometimes spike does not terminate when you might expect.
This is a bit of a hack to get CI dailies to fail in a reasonable time.
 2022-06-09 16:33:56 +01:00
Pirmin Vogel
f71b23ddf8 Update google_riscv-dv to google/riscv-dv@0b2b3d6 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b2b3d65ce8fdff4de8974d1f328a90d6c1db5dd

* [epmp] Add support for mseccfg CSR (Pirmin Vogel)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-06-09 09:00:42 +02:00
Rupert Swarbrick
9b68b5ef14 [dv,core_ibex] Allow instructions near the top of initialised IMEM 
If you call the read() function on the memory model with an
uninitialised word, it generates a UVM error.

This is reasonable for data memory (where we never want to read
something without an architectural value) but is not reasonable for
IMEM, where Ibex runs ahead. Squash the error in this case, but force
bad integrity for the fetch to make sure we see something explode.
 2022-06-01 14:02:45 +01:00
Canberk Topal
c253bd76a9 [dv] PMP related functional coverage points 
Adding MSECCFG CSR related functionality also some write checks etc.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-06-01 13:25:09 +01:00
Canberk Topal
ea4e9383db [syn] Use sv2v for prim_generic_buf 
Convert `prim_generic_buf` to Verilog as well.
Also, replace 'prim_buf' with 'prim_generic_buf' whenever we see a
`prim_buf` in a generated Verilog file.

Fixes #1557

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-06-01 11:24:19 +01:00
Pirmin Vogel
e1f614887e Update spike_cosim.cc to be able to build against newer Spike versions 
This works with versions ibex-cosim-v0.2 and ibex-cosim-v0.3. The latter
version is required to support the mseccfg CSR added with ePMP.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-06-01 00:50:49 +02:00
Canberk Topal
57d810e7fe [fcov] Implementing interrupts section of covplan 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-30 15:56:05 +01:00
Canberk Topal
97a949df02 [doc] Update coverage plan to point crosses/cp's 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
3b2e792a53 [fcov] Cross for Decoded Insn and Controller FSM 
Bins are defined specifically for interested cases implied in coverage
plan.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
1ad55daf96 [dv] Randomize mstatus.mprv properly 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
c2f5fea8a9 [fcov] MPRV with Load/Store and RAW Hazard 
Added in functional coverage interface

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
51bcae432b [rtl] PMP Logic Refactoring 
This makes use of functions in a way that enables us to use `priv_lvl`
dependent logic in the DV environment.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
46f1f69209 [rtl] Remove unused clk/rst_n in PMP module 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
04ce927a74 [fcov] Add various coverage points 
Mostly related to WFI, but also double fault and icache enable

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
f21b6545ac [fcov] CSR related coverage points 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Canberk Topal
11002708ea xlm support for PMP coverage groups 
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-05-25 13:37:30 +01:00
Pirmin Vogel
223f7cd25b Update google_riscv-dv to google/riscv-dv@cc4b870 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cc4b87057cb38c91cb0c2ecb065e38281df7aa97

* Fix google/riscv-dv#857 (aneels3)
* [euvm] Fixed a typo in the README file (Puneet Goel)
* [euvm] updated the README file (Puneet Goel)
* [euvm] Moved euvm specific README to euvm folder (Puneet Goel)
* [euvm] ported some SV updates (Puneet Goel)
* [euvm] Fixed generated ASM code indentation (Puneet Goel)
* Add support for RV64IMC instr coverage (aneels3)
* Add register definitions for privilege spec 1.12 and debug spec
  1.0.0 (Henrik Fegran)
* Updated README note for EUVM (Puneet Goel)
* Use current date in output folder name (Puneet Goel)
* Try to create output file folder if it does not exist (Puneet Goel)
* Added a readme for EUVM port (Puneet Goel)
* Allow providing a randomization seed from command line (Puneet Goel)
* Make merging of directed instruction streams scalable (Puneet Goel)
* Create and use new class riscv_prog_instr_stream (Puneet Goel)
* Added and used append and prepend functions for instr_list (Puneet
  Goel)
* Added new targets and tests (Puneet Goel)
* Expose riscv instruction classes in the riscv gen package (Puneet
  Goel)
* Use mixin templates to create RISCV instruction classes (Puneet
  Goel)
* Fix a bug in asm section tag generation (Puneet Goel)
* EUVM upgrade for bitmanip (Puneet Goel)
* Use new clog2 implemented in esdl.data.bvec module (Puneet Goel)
* Add debug and clean targets to Makefile (Puneet Goel)
* Use Queue functions in place of array concatenation (Puneet Goel)
* Misc fixes after review (Puneet Goel)
* Fix broken run.py script (Puneet Goel)
* Use more verbose naming in main function in the test (Puneet Goel)
* Removed some redundant code comments (Puneet Goel)
* Allow verbosity and instr count specification from make run command
  (Puneet Goel)
* Handle riscv_loop_instr confliting constraint in post_randomize
  (Puneet Goel)
* Use variable names that do not conflict with outers (Puneet Goel)
* Use constraint in place of Constraint (Puneet Goel)
* Fixed a typo where '-' was getting printed in place of ' ' (Puneet
  Goel)
* Pick urandom from new location -- esdl.base.rand (Puneet Goel)
* Fixed an issue where newline character was not getting added to some
  instructions (Puneet Goel)
* Fixed an issue with sup program generation (Puneet Goel)
* Added EUVM riscv_instr_base_test (Puneet Goel)
* Added EUVM riscv_instr_register module (Puneet Goel)
* Moved EUVM files to euvm folder (Puneet Goel)
* Add makefile command to to run a test (Puneet Goel)
* Cast return value from ceil to integer (Puneet Goel)
* Miscelleneous fixes (Puneet Goel)
* Fixed some issues in riscv_loop_instr (Puneet Goel)
* Use variable for setting rand_mode (Puneet Goel)
* Use false in place of '0' for bools (Puneet Goel)
* Added build makefile (Puneet Goel)
* misc fixes (Puneet Goel)
* Added riscv instruction definitions (Puneet Goel)
* Added euvm module riscv_instr_registry (Puneet Goel)
* Added euvm module riscv_data_page_gen (Puneet Goel)
* Added euvm module riscv_privileged_common_seq (Puneet Goel)
* Added euvm module riscv_debug_rom_gen (Puneet Goel)
* Use urandom!bool in place of inappropriately named function toss
  (Puneet Goel)
* Added euvm module riscv_illegal_instr (Puneet Goel)
* Added euvm module riscv_asm_program_gen (Puneet Goel)
* Use esdl.rand: toss instead os uniform(0, 2) (Puneet Goel)
* Fixed randomization of avail_regs in euvm module riscv_instr_stream
  (Puneet Goel)
* Use esdl.rand: shuffle instead of randomShuffle (Puneet Goel)
* Added euvm module riscv_directed_instr_lib (Puneet Goel)
* added euvm module riscv_load_store_instr_lib (Puneet Goel)
* urandom has moved to package esdl.rand (Puneet Goel)
* Added euvm module riscv_instr_sequence (Puneet Goel)
* Added euvm module riscv_amo_instr_lib (Puneet Goel)
* Added euvm module riscv_instr_stream (Puneet Goel)
* A small fix in riscv_pmp_cfg module (Puneet Goel)
* Added euvm module riscv_loop_instr (Puneet Goel)
* Added euvm module riscv_pseudo_instr (Puneet Goel)
* Added euvm module riscv_vector_instr (Puneet Goel)
* Added euvm module riscv_floating_point_instr (Puneet Goel)
* Added euvm module riscv_b_instr (Puneet Goel)
* Added euvm module isa/riscv_compressed_instr (Puneet Goel)
* Added euvm module isa/riscv_amo_instr (Puneet Goel)
* Added euvm module isa/riscv_instr (Puneet Goel)
* Added euvm module riscv_callstack_gen (Puneet Goel)
* Added euvm module riscv_page_table_list (Puneet Goel)
* Used ranged switch case statements where required (Puneet Goel)
* Added euvm module riscv_privil_reg (Puneet Goel)
* Add @UVM_DEFAULT uda on the class members where required (Puneet
  Goel)
* Added euvm module riscv_reg (Puneet Goel)
* Added euvm module riscv_pmp_cfg (Puneet Goel)
* Added euvm module riscv_vector_cfg (Puneet Goel)
* Added euvm module riscv_page_table_exception_cfg (Puneet Goel)
* Added euvm module riscv_page_table_entry (Puneet Goel)
* Added euvm module riscv_page_table (Puneet Goel)
* Added riscv_core_setting module (Puneet Goel)
* Added new file riscv_instr_gen_config (Puneet Goel)
* Fixed some module imports (Puneet Goel)
* Added new file riscv_signature_pkg (Puneet Goel)
* Added D port of riscv_instr_pkg (Puneet Goel)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-05-24 18:57:25 +02:00
Harry Callahan
c5567e8f66 Change makefile default simulator for core_ibex dv to xcelium 2022-05-23 17:24:12 +01:00
nedguthrie
fe157648a6 Fix formatting if IcacheScramble Description 2022-05-20 20:29:04 +01:00
Rupert Swarbrick
6efb4b1597 Dump riscv-dv generation messages to a log file 
I was previously just dumping them to /dev/null because the
code always worked but... predictably I was wrong! Write them
somewhere more useful for debug.
 2022-05-19 17:34:41 +01:00
Rupert Swarbrick
efd289dc17 [core_ibex] Disable waves by default 
This seems like something you'd want to enable explicitly, to avoid
filling up a disk on a big run.
 2022-05-17 12:04:26 +01:00
Rupert Swarbrick
09d2dd2306 Update ISA strings from Xbitmanip to XZb* 
This allows us to model stuff more closely. This depends on Spike
version ibex-cosim-v0.2 (which is rebased onto a master branch commit
supporting these more specific ISA strings).
 2022-05-13 09:47:00 +01:00
Pirmin Vogel
05f3b205c5 [doc] Add missing PKG_CONFIG_PATH now required for Ibex DV 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-05-13 10:33:00 +02:00
Harry Callahan
832259401e Add warning when cosim is disabled by a plusarg 
May aid in debugging
 2022-05-12 11:01:36 +01:00
Harry Callahan
ef3549a2d3 Add pre_abort callback to cosim scoreboard for proper cleanup 2022-05-12 11:01:36 +01:00
Greg Chadwick
a0adf60d0b [dv] Fix bitmanip test building 2022-05-12 10:42:15 +01:00
Harry Callahan
0c38b203dd Run core_ibex dv with cosim by default 2022-05-11 15:46:46 +01:00
Harry Callahan
36129a2cb1 Modify existing comparison scripts to process cosim trace 
Don't yet tear out the old logfile-comparision code, add a new path for the
cosim flow.

This uses the existing riscv-dv functions to parse the cosim logfile, as it is
fundamentally still generated by spike so should be checked for errors.
 2022-05-11 15:46:46 +01:00
jamesrbailey
361f2ddedf Update ibex_top.sv 
Adding conditional to instantiate non-scrambling instruction cache memories when ICacheScramble parameter is not set.
 2022-05-04 14:40:00 +01:00
Karol Gugala
73a0586944 Sim: simple_system: pass MHPMCounterNum to core 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2022-05-02 10:12:44 +01:00
Harry Callahan
e34bb4d92f Construct compile-tb cmds to link against ISS for cosim 
This is a continuation of PR's #1613 and #1575 work.

If cosim in enabled, we need to pass the appropriate flags to the eda tool for
it to link against the precompiled ISS when building the testbench.
This commit assembles the appropriate flags using pkg-config to query the
SPIKE_ISS build, then uses the scripts_lib.subst_vars() method to populate the
templated commands in the yaml.

The eda tools have different requirements for consuming the flags, so massage
them into the appropriate shape on the python side.
 2022-04-29 11:13:21 +01:00
Harry Callahan
345dd6644b Fix variable-checking in makefile 2022-04-29 11:13:21 +01:00
Harry Callahan
d4c945622e Replace concatenation with mask operations 
Make Xcelium happy
Add leading zero for readability (Addresses PR comment)
 2022-04-29 11:13:21 +01:00
Rupert Swarbrick
42ce56b6b6 [dv] Simplify instructions for how to use Spike with cosim 
This depends on Spike version ibex-cosim-v0.2 (which exposes the
various library headers with pkg-config, making configuration much
easier).
 2022-04-29 11:13:21 +01:00
Canberk Topal
394a0d2160 Updating parameters for OpenTitan option 
Updated the parameters with respect to top_earlgrey.hjson in OpenTitan
repository. For other builds, kept the previously undeclared parameters
as their default values.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-04-28 15:14:42 +01:00
Rupert Swarbrick
2f28987916 Remove some unused variables from core_ibex Makefile 2022-04-28 13:52:07 +01:00
Rupert Swarbrick
26f824b907 Infer PMP config from Ibex config in core_ibex scripts 2022-04-28 13:52:07 +01:00
Rupert Swarbrick
f6f84b0b06 Read config data in 2 steps in core_ibex scripts 
No functional change, but this means we can look at the configuration
object to do other stuff without having to reload things.
 2022-04-28 13:52:07 +01:00
Rupert Swarbrick
ecdb1e01f6 Remove ISA, ISA_ISS from Makefile 
Move their calculation into the Python scripts, which means that we
don't have to make sure everything is kept in sync.
 2022-04-27 16:33:49 +01:00
Rupert Swarbrick
b63ab3b120 Strengthen types in ibex_config.py 
This should make it easier for other scripts to use
parse_config().
 2022-04-27 16:33:49 +01:00
Canberk Topal
3ad3bd0d71 [dv] Coverage fixes 
Makes coverage work for VCS and XLM.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-04-27 10:52:44 +01:00
Harry Callahan
4db6d15def Fix dead link 2022-04-27 10:51:42 +01:00