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Author SHA1 Message Date
Pirmin Vogel
40e3db5f23 [rtl] Rework assertions 
This commit modifies the assertions to not fire as long as the reset
is active. Also, it updates some assertions.

This resolves lowRISC/ibex#274.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2019-11-15 10:23:03 +01:00
udinator
c05634cfdf
[DV] Enable user-mode in DV environment, add basic tests (#471) 
Signed-off-by: Udi <udij@google.com>
 2019-11-14 16:11:32 -08:00
Tobias Wölfel
103b7357f0 Update fusesoc usage 2019-11-14 13:20:19 +01:00
Tobias Wölfel
76f6a3d4c3 Use shared code for Arty A7-100T example 
Move Xilinx specific code into shared folder so it can be re-used by
different examples.
Use the shared RAM code and make use of byte enable signal.
Fixes lowrisc/ibex#144
 2019-11-14 13:20:19 +01:00
Tobias Wölfel
6be1e8aff3 Delay simulator finish 
The tracer needs time to log the final instruction.
Introduce a counter to delay calling the simulation finish.

Fixes lowrisc/ibex#468
 2019-11-14 11:57:12 +00:00
Pirmin Vogel
9738b6c703 [rtl] Rework core_busy signals, remove feedback to clk 
This commit reworks the generation of the `core_busy` signal used to
control the main clock gate of the core. Without this commit, the
controller generates a separate `first_fetch` signal only asserted in
the FIRST_FETCH state that directly controls `core_busy` and thus the
main clock gate. This is problematic as it introduces a feedback to
from the controller state into the clock.

This commit removes the problematic signal and changes the generation of
`ctrl_busy` in the FIRST_FETCH state of the controller. This signal is
now used to control the main clock gate in all states (previously all
except FIRST_FETCH) but it gets registered, thus it does not introduce
the feedback into the clock.

This resolves lowRISC/ibex#211.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2019-11-14 12:55:16 +01:00
Tom Roberts
0243e08111 [rtl] Switch to M mode on debug entry 
- Core should operate as if in M-mode while in debug mode
- Previous priv level is restored from dcsr on DRET
- Fixes #463
 2019-11-14 09:37:02 +00:00
Tobias Wölfel
0927f085ee Use gitignore for software directory 2019-11-13 14:30:53 +01:00
Tobias Wölfel
ef96678d65 Update load instruction 2019-11-13 14:30:53 +01:00
Pirmin Vogel
52b03f3637 [rtl/controller] Remove redundant check in EBREAK handling 
This commit removes a redundant for `ebrk_insn` in the `DBG_TAKEN_ID`
state. If this signal is not set, the controller does not enter this
state in the first place. This is not changing functional behavior,
but removes a `MISSING_ELSE` coverage hole reported by @udinator.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2019-11-13 13:12:15 +01:00
Pirmin Vogel
6a5ee22395 [rtl/controller] Remove redundant check in execption handling 
This commit turns the last case in the exception handling if/else block
from an `else if` to an `else`. This is not changing functional
behavior as the same condition is checked previously, but removes a
`MISSING_ELSE` coverage hole reported by @udinator.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2019-11-13 13:12:15 +01:00
Pirmin Vogel
d538261c78 [rtl] Ignore LSB only for writes to dpc 
Without this commit, writes to `dpc` with the LSB set are completely
ignored. This commit changes the implementation to ignore the LSB only.
This is the same behavior as seen required for `mepc`. This resolves
lowRISC/ibex#444.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2019-11-13 13:11:22 +01:00
Marek Pikuła
9b390c5d4e Fix formatting of table in simple system 
Fixes #454
 2019-11-13 11:09:05 +00:00
udinator
6ce8b6ecf2
Update google_riscv-dv to google/riscv-dv@4b333ba (#462) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e

* cg instantion based on supported_isa (google/riscv-dv#303)
  (udinator)
* Fix coverage collection issue, change default target to rv32imc
  (google/riscv-dv#302) (taoliug)
* Integrate whisper(swerv-ISS) (google/riscv-dv#301) (taoliug)
* Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode
  (google/riscv-dv#299) (taoliug)
* Fix jalr handling issue for ovpsim (google/riscv-dv#298) (taoliug)
* Add noclean option, change default output directory of coverage
  collection (google/riscv-dv#297) (taoliug)
* Enable using core trace logs for coverage collection (google/riscv-
  dv#291) (udinator)
* Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296)
  (taoliug)
* fixed line widths (x2) and check error returns for any questa
  simalator (google/riscv-dv#293) (simond-imperas)
* Unknown instruction fix (google/riscv-dv#290) (simond-imperas)
* Fix ovpsim log process issue (google/riscv-dv#289) (udinator)
* adding riscvOVPsim vector instruction trace to csv processing -
  start (3rd Attempt) (google/riscv-dv#288) (simond-imperas)

Signed-off-by: Udi <udij@google.com>
 2019-11-12 14:39:22 -08:00
Tobias Wölfel
1cc4831480 Add rv32Zicsr target in azure 
Fixes lowrisc/ibex#459
 2019-11-12 21:59:40 +00:00
Tobias Wölfel
87b05b6f0e Update expected failure for riscv-compliance 
[riscv-compliance] changes the tests for rv32i.
Update the expected output.

[riscv-compliance]: df18fa8d95
 2019-11-12 21:59:40 +00:00
udinator
7ea79ae366
[funct_cov] Fix GPR assignment bug (#456) 2019-11-12 10:07:12 -08:00
udinator
2ee9828a78
[Doc] Update verification documentation (#449) 2019-11-12 10:06:41 -08:00
udinator
2a3c6c6430
[funct_cov] Update Makefile options for coverage (#455) 2019-11-11 15:07:20 -08:00
udinator
23589f5a91
[funct_cov] Update Ibex log parsing (#453) 2019-11-11 13:52:47 -08:00
Pirmin Vogel
0a1a8514c4 [rtl] Rework access to performance counter CSRs 
This commit reworks the code section describing how the performance
counter CSRs are accessed by CSR instructions. Instead of using an
address mask inside the default case, and excluding CSRs in the same
address range previously handled (like `mcycle(h)`, `minstret(h)`,
`mcountinhibit`), all performance counter CSRs are now explicitly
enumerated. This enhances readability of the code and enhances
compatibility with some tools without changing behavior or causing
lint problems.

This commit is based on suggestions from @MarekPikula. It replaces the
proposal in lowRISC/ibex#336.
 2019-11-11 19:01:49 +01:00
Greg Chadwick
2041f10c69 Added simple system 
Simple system is a basic verilator top-level testbench for running
 executables.  It has functionality for outputting text to a log file
 and for the software to terminate the simulation
 2019-11-09 07:48:47 +00:00
Greg Chadwick
31d423ae47 Added top-level shared directory 
shared is to be used for RTL/Code that is used by multiple parts of the
directory tree or does not fit neatly under other places in the tree.
 2019-11-09 07:48:47 +00:00
udinator
502b5a951e
[DV] clean up stale TODOs (#448) 2019-11-04 16:52:01 -08:00
udinator
498786aef5 Update google_riscv-dv to google/riscv-dv@44bec76 (#447) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44bec7695fd2399166e181fa84b66a608b5f745f

* Re-enable custom OVPsim configuration files (google/riscv-dv#282)
  (udinator)
 2019-11-04 13:41:36 -08:00
udinator
098fb7d847
[DV/flow] Integrate with RISCV-DV (#446) 2019-11-04 13:22:47 -08:00
udinator
f3f3f3de09
Update google_riscv-dv to google/riscv-dv@cce71d2 (#445) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cce71d24b56f641d994fbf69b8b50aa3756b9322

* Add handshake documentation (Udi)
* Fix coverage debug mode (google/riscv-dv#281) (taoliug)
* Fix coverage script issue (google/riscv-dv#280) (taoliug)
* code block highlight (google/riscv-dv#279) (taoliug)
* Replace setting directory with a default target (google/riscv-
  dv#278) (taoliug)
* fixed trace handling issues (google/riscv-dv#274) (eroom)
* Allow running the script from other directory (google/riscv-dv#277)
  (taoliug)
* Add dummy writes to status and ie CSRs (Udi)
* Script typo fix (google/riscv-dv#272) (Dan Petrisko)
* Fix misa setup issue (google/riscv-dv#271) (taoliug)
* Enable mie.mtie for timer interrupts (Udi)
* Update illegal system instr generation (Udi)
* Fix duplicate (google/riscv-dv#268) (taoliug)
* Add experimental instruction distribution control (google/riscv-
  dv#267) (taoliug)
* Update README to clarify the flow setup instructions (google/riscv-
  dv#265) (taoliug)
* Remove debug logging (google/riscv-dv#264) (taoliug)
* Fix compressed instruction test setup (google/riscv-dv#263)
  (taoliug)
* adding __init__ in the scripts dir since python3.7 requires that for
  directories to be recognized as modules (google/riscv-dv#252)
  (Jielun Tan)
* Fix riscvOVPsim.ic (google/riscv-dv#261) (taoliug)
* Fix ovpsim sim problem (google/riscv-dv#260) (taoliug)
* Add alternative command options for directed instruction stream
  (google/riscv-dv#254) (taoliug)
* Fix dsim compilation issue (google/riscv-dv#253) (taoliug)
 2019-11-04 10:48:02 -08:00
Tom Roberts
48adda0b47 [verilator] Fix a few verilator DV issues 
- Speed up compile time by only optimizing hot code
- Fix some incorrect references in tb_cs_registers
- Add a comment for FST vs VCD tracing
 2019-11-01 16:02:46 +00:00
Pirmin Vogel
275c3310fa [rtl] Remove unused set-less-or-equal-than ALU ops 
These operations (ALU_SLET, ALU_SLETU) are remnants of of the original
OpenRISC design. RISC-V just has set-less-than (ALU_SLT, ALU_SLTU).

This resolves lowRISC/ibex#432 reported by @udinator.
 2019-11-01 11:51:25 +00:00
udinator
e2ab24b9e3
[DV] Assert interrupt during write to MSTATUS and MIE (#435) 2019-10-31 11:14:53 -07:00
Greg Chadwick
5ce6351530 Add performance counter utils for verilator sims 2019-10-30 16:56:55 +00:00
Tom Roberts
70b53068db [DV] Add registers testbench 
- Sample C++ unit testbench for system registers module
- Only tests a few PMP registers at the moment
 2019-10-30 14:46:33 +00:00
Pascal Cotret
e5cf0c0fcf Error synthesis in Vivado 2019-10-28 20:36:37 +00:00
Pirmin Vogel
36ce999fbb [rtl/lsu] Rework assertion checking response valid 
This commit replaces an obsolete assertion with one checking that
response valid is received only if the LSU is ready to handle it.

This resolves lowRISC/ibex#421 reported by @udinator.
 2019-10-26 14:51:19 +01:00
udinator
edf9371c6c
[DV] Increase number of resets in reset_test (#418) 2019-10-25 14:28:06 -07:00
udinator
d3c7b887d7
[DV] Increase number of illegal instructions generated (#426) 2019-10-25 14:00:22 -07:00
Pirmin Vogel
0331ed61b1 [rtl/alu] Remove unused comparison operations 
These operations (ALU_GT, ALU_GTU, ALU_LE, ALU_LEU) are remnants of
of the original OpenRISC design. RISC-V does not have these instructions
and instead implements the operations by reversing operands for ALU_LT,
ALU_LTU, ALU_GE, ALU_GEU.

This resolves lowRISC/ibex#420 reported by @udinator.
 2019-10-25 13:58:59 +01:00
Marek Pikuła
294849bb18 [RTL] Add MultiplierImplementation parameter in top level 2019-10-24 14:33:24 +01:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead

* Incorrect deletion (google/riscv-dv#249) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248)
  (eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247) (taoliug)
* Coverage model fixes (google/riscv-dv#246) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#243) (taoliug)
* Functional coverage improvement (google/riscv-dv#242) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
  dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240)
  (taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239)
  (taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234)
  (taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233)
  (eroom)
* Refine README structure (google/riscv-dv#231) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230)
  (taoliug)
 2019-10-23 10:46:31 -07:00
udinator
023b7b6856
[RTL/Tracer] Fix compressed jump RD write (#416) 2019-10-23 10:30:11 -07:00
udinator
8e40f65582
[DV] Enable timer interrupts (#415) 2019-10-23 09:33:50 -07:00
Tobias Wölfel
0728fb7e9f [DV] Update simulation terminate argument 
Add description to usage output.
Add short option '-c'.
 2019-10-21 22:19:24 +02:00
udinator
c808fed7d1
[DV] testplan documentation (#409) 2019-10-21 11:45:40 -07:00
udinator
beb40d89f6
[DV] Add interrupt wfi test to address coverage hole (#410) 2019-10-21 11:44:23 -07:00
Philipp Wagner
1c3903e2ce Tracer: Decode an all-zero instruction as c.unimp 
Fixes #396
 2019-10-17 13:48:29 +01:00
Greg Chadwick
edb33cca56 Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
Greg Chadwick
6b1a7add5d [Doc] Added extra setup info for Verification 2019-10-17 10:31:18 +01:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf (#406) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd

* Add more ebreak generation control (google/riscv-dv#229) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226)
  (taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225)
  (Greg Chadwick)
* Minor README typo (google/riscv-dv#219) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
  dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220)
  (taoliug)
* Fix floating point comparison issue (google/riscv-dv#218) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215)
  (Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
  (google/riscv-dv#214) (Hai Hoang Dang)
 2019-10-16 17:50:23 -07:00
udinator
fc80203af3
[DV] Debug_ebreak test fix (#405) 2019-10-16 17:44:47 -07:00
taoliug
1b71320230
Add RV32IM test (#404) 2019-10-16 10:15:49 -07:00