simplesat (required by fusesoc) was broken by an update to the attrs
library. Now simplesat 0.8.2 has been released which fixes the issue, we
can remove the explicit pinning of the old attrs version.
- If an error is signalled in the first part of an unaligned
transaction, the second part is issued anyway (to avoid a
timing loop from data_err_i -> data_req_o)
- Previously, the error was signalled and an exception was taken
as soon as the first transaction completed. This commits makes
the core wait until both transactions have completed.
- This prevents strange behaviour caused by the lsu and controller
being out of sync (fixes#374).
This miscompilation is now reported and fixed, mention it in the code to
refer back to it when we can revert back to the old code (which will
take a couple months until we can require a newer Verilator version).
Fixes#372
Add fusesoc description for core with tracing enabled, implicitly
linting the ibex_tracer as well.
Run with
$ fusesoc --cores-root=. run --target=lint lowrisc:ibex:ibex_core_tracing
The ibex_tracer module implements an execution tracer, observing the
execution flow and writing a human-readable execution trace. The trace
information is coming from the RVFI signals, as specified at
https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md.
The existing implementation was tailored for use in ModelSim and other
commercial simulators, and used SystemVerilog features which are not
supported in Verilator or Icarus Verilog, such as classes, queues and
non-standard format specifiers (e.g. the `-` specifier for right-aligned
output). Being unable to see an execution trace when using Verilator
significantly reduced productivity and its usefulness.
This commit refactors the tracer to only use SystemVerilog constructs
which are supported in Verilator. While doing so, multiple improvements
were made for correctness and style.
Major changes:
- Improve compatibility with Verilator. Remove many non-synthesizable
SystemVerilog constructs, such as classes and queues.
Use casez instead of casex for better Verilator support (Verilator
doesn't support X).
- Make the decoded output of the tracer match objdump from binutils
exactly. Doing so is beneficial for two reasons: we can easily
cross-check the decoded output from the tracer against the disassembly
produced by objdump (and we did that), and users don't need to get
used to another slighly different disassembly format.
- A plusarg "+ibex_tracer_file_base=ibex_my_trace" can be used to set a
different basename for the trace log file.
Smaller cleanups:
- Remove decoding of reg-reg loads, which were leftover from a PULP
extension.
- Make better use of the data available on the RVFI. Pass all of RVFI
to the tracer, and use the provided data instead of manually
recreating it, e.g. to get register data or the jump target.
- Rename all "instr" abbreviations to "insn". "insn" is what RVFI uses
(and we cannot change that), so for consistency we now always use this
abbreviation across the file.
All CSR names have been imported from binutils' riscv-opc.h file, available at
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=include/opcode/riscv-opc.h
using this small C program:
#include <stdio.h>
#define STR(s) #s
int main(int argc, char **argv) {
printf("unique case (csr_addr)\n");
#define DECLARE_CSR(name, csraddr) \
printf(" 12'd%d: return \"%s\";\n", csraddr, STR(name));
#include "riscv-opc.h"
printf(" default: return $sformatf(\"0x%%x\", csr_addr);\n");
printf("endcase\n");
return 0;
}
The RISC-V compliance test suite for the RV32 I, M, and C extensions has
been executed and traced. The disassembly of all traces have been
compared against traces produced by objdump to ensure identical output.
This PR is based on work by Rahul Behl <raulbehl@gmail.com> in #280.
Thank you Rahul for providing a great starting point for this work!
This testbench was helpful in creating the initial tracer, but is not
fully working any more, and too limited to test the trace fully.
Extending it is inconvenient, as the creation of instruction sequences
through the bus interface is easy to get wrong.
When an exception occurs controller goes into the flush state and then
does a pc_set to go the exception handler. So there is no need for the
incoming signals that indicate an exception to factor directly into
pc_set_o. This flops exc_req and illegal_insn to break long timing
paths that were occurring because of this.
Fixes#305
When an instruction that caused an exception occurred the controller
would clear the instr_valid bit but rely on the instruction bits staying
in the ID register so it could still use them in the FLUSH state to
decide what to do. This reworks the control logic slightly so
instr_valid remains asserted when the controller goes into the FLUSH
state so relevant signals can be qualified with the instr_valid bit.
There were no known functional issues caused by the previous behaviour
however this gives a more robust approach.
Update code from upstream repository https://github.com/google/riscv-
dv to revision d3419444ca2fdb499a204587b2d36c6f5c1e0c44
* Update README (Udi)
* Add knob to enable full CSR randomization, fix mstatus.spp (Udi)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e3e1e308cfc3d718aeb94bb3463371979d9a31ae
* Disable full trace in the run script (google/riscv-dv#180) (taoliug)
* Fix spike logging issue (google/riscv-dv#179) (taoliug)
* Add functional coverage for HINT instructions (google/riscv-dv#177)
(taoliug)
* Add functional coverage for various hazard conditions (google/riscv-
dv#176) (taoliug)
