Update code from upstream repository https://github.com/google/riscv-
dv to revision 4583049cc2b3469ba9dea56b5e2d75809a89d8f3
* Allow running compile command in LSF (google/riscv-dv#506) (taoliug)
* improve documentation of config options (Udi Jonnalagadda)
* Update AMO region and data sections (google/riscv-dv#503) (taoliug)
* Avoid jumping to a sub program of other harts (google/riscv-dv#502)
(taoliug)
* Use .section for data sections by default (google/riscv-dv#501)
(taoliug)
* create PMP accessible region for exception handlers and start/end
sections (Udi Jonnalagadda)
* minor change to signature_addr passed to generator (google/riscv-
dv#497) (udinator)
* Solve before cconstraints modified (google/riscv-dv#476) (Dariusz
Stachańczyk)
* Move instruction sections together for multi-harts (google/riscv-
dv#495) (taoliug)
* add seed capability to CSR test generation (Udi Jonnalagadda)
* fix pmp/shifted_addr compile warning (google/riscv-dv#493)
(udinator)
* User long jump to switch between different harts (google/riscv-
dv#491) (taoliug)
* Fix s_region generation (google/riscv-dv#487) (taoliug)
* update rv32imc/riscv_pmp_test testlist options (google/riscv-dv#486)
(udinator)
* Fix default value of num_of_harts (google/riscv-dv#485) (taoliug)
* Add shared memory region for multi-harts AMO (google/riscv-dv#484)
(taoliug)
* Add a runtime option num_of_harts (google/riscv-dv#483) (taoliug)
* Add multi-thread support (google/riscv-dv#482) (taoliug)
Signed-off-by: Udi <udij@google.com>
The --end_signature_addr argument doesn't go to Verilog; instead it
makes it through run.py (vendored-in, so hard to change) and
eventually gets inserted into some assembly code.
Before this patch,
make ITERATIONS=1 TEST=riscv_csr_test ISS=spike SEED=123
failed with:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S: Assembler messages:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:526: Error: illegal operands `li x2,8ffffffc'
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:533: Error: illegal operands `li x2,8ffffffc'
The main point of this is that it's somewhere we can store what it
calls "ss_opts": the options that we must pass to Spike to tell it the
memory layout of the simple_system environment.
While we're at it, I've tried to make this reasonably pleasant to use.
So you can do
spike-simple-system.sh <elf-file>
just to run the thing. To pass stuff to Spike without the
bash script getting in the way, use '--':
spike-simple-system.sh -- my option -h --here <elf-file>
We do this by pulling the definition of host_addr_o and host_req_o out
of an always_comb process in riscv_testutil.sv.
When set inside the process, Verilator warns about a combinatorial
loop. This happens because a read request could go out on the bus and
appear again (combinatorially) on the slave interface, setting
read_signature_and_terminate. This doesn't actually happen (because
read_signature_and_terminate only takes effect when we are in state
WAIT), but Verilator's sensitivity tracking isn't fine-grained enough
to notice.
If you just build simple_system a fusesoc line like
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system
then the change to ibex_simple_system.sv suffices, but if you
explicitly set a parameter in fusesoc like this:
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system \
--RV32M=1
then it overrides the default parameter with a literal 1. We declare
the parameter as an 'int', so I guess that's quite a reasonable
behaviour from fusesoc. Anyway, this check only triggers when a 1-bit
parameter is set with a literal 1, so should be safe. (If you do
something buggy like setting it to 2, it will still moan at you). This
patch adds a waiver file in examples/simple_system that silences the
warning.
This patch also makes the equivalent change to riscv_compliance,
adding a waiver file in dv/riscv_compliance/lint and fixing up the
default parameters.
Also fix a minor nit: if something had gone really weird and we saw
a pass message followed by a fail message, the previous code would
have treated the test as a pass. Now it is treated as a failure.
This is mostly just re-indentation and being explicit about what we're
importing from what module, which allows Python lint tools (flake8 and
similar) to spot when there's a typo in a variable name or similar.
The previous version died with a confusing error if you ran it with no
arguments (because the compulsory input and output file paths are
specified as --option arguments).
I've left the arguments optional, but they now default to
stdin/stdout (which means you can now use this script in a pipe).
I've also reformatted the code I touched to look a little more like
PEP8 Python.
Before this patch, running the Makefile's default target deleted
everything and then ran the whole flow. This sometimes does
unnecessary work (if I've just changed the design, there's no need to
rebuild and re-run the instruction generator). It also definitely
won't work with Make's -j flag, since it depends on the targets being
built in order.
This patch keeps the same stages in the Makefile, but makes each stage
generate a stamp file, adding dependencies between the stages. This
way, you can make a small change to the design and re-run the
simulation without having to generate the random inputs again.
This doesn't make much difference if you're running lots of tests with
no LSF (since VCS is very slow, its runtime for simulation completely
dominates), but it can make a significant difference if you're
debugging a single test, have made a change to the design and want to
re-run.
One significant change is that running 'make' doesn't automatically
delete existing files any more. To make this possible (and useful!),
we generate random data and test results in a directory keyed by the
seed. For example
make SEED=123
will generate results in out/seed-123/regr.log (rather than
out/regr.log as before).
To make sure we rebuild things properly if you change something like
the number of iterations or the tests to run, we dump some variables
describing the mode in which we were running. If these don't match the
nnext time around, we'll rebuild stuff if necessary.
Advanced (or hurried) users of the existing Makefile might have done
things like change the design and then run
make SEED=123 compile rtl_sim
Now, the rtl_sim target depends on its logical dependencies. On the
plus side, this means that you won't accidentally simulate out-of-date
code. On the minus side, cunning tricks to avoid having to re-run
stuff after touching a design file won't work. (If you're feeling
really determined to do something like that, it's still possible with
make -t).
The seed-specific stamp files and dumped Make variables go into
$(OUT-SEED)/.metadata directory, rather than $(OUT-SEED)/instr_gen or
$(OUT-SEED)/rtl_sim. This is because of a review comment (to avoid
extra clutter in the output directories).
This should cause no functional change, but avoids a seeming
combinatorial loop reported by Verilator.
The seeming loop is because the always_comb process that contained
have_instr is sensitive to if_id_pipe_reg_we but that process wrote
the have_instr signal, which is used in the continuous assignment to
if_id_pipe_reg_we later on.
Verilator will soon support the configuration file syntax of wildcard
matches for linter warnings to waive. Switch to the new syntax that
avoids line-based rule settings.
The process_regression_list function from riscv-dv is really chatty.
When we're just compiling the testbench, we don't actually need to
figure out what tests we're running, since we'll never run them
anyway. So don't call it.
This is part of work to run binaries created for the simple system
under Spike. Spike's default behaviour (after a weird 'rom' trampoline
at 0x1000) is to obey the entry point given in the ELF file. So let's
set it correctly.
The important change is that we now tell the user to configure spike
with --enable-misaligned. This is needed because Ibex handles
misaligned loads and stores rather than jumping to a trap handler (the
default behaviour in spike).
There's also a little more information about where you can find the
various tools and how to set them up.
Note that the existing deep links to riscv-dv's documentation
bit-rotted at the start of February.
If VERDI_HOME is not set, calling fsdbDumpfile makes VCS hang with an
error message. This patch checks whether we think FSDB dumping is
actually going to work and, if not, dumps with the default VCD+
format (also called VPD) instead.
I'd written the original patch (b157573) on a branch that didn't
include commit 2431551 (which moves stuff that was in dv/uvm into
dv/uvm/core_ibex). Apparently, I'd fixed up the rule for the output
directory, but I'd missed the ucli.key file.
By default, variables in functions are static in SystemVerilog. This caused `string desc = "";` in `get_fence_description` to be executed only once, i.e. the text was continuously extended from the last call.
Mark all functions `automatic` to get behavior as one would expect from normal functions.
Recently changes in the RISC-V compliance repo have caused our tests to
fail. That indicent highlighted the issue that we use the latest master
version of the compliance suite without pinning the version.
This PR fixes that by pinning to a specific version where our tests
still succeeded.
Upstream PR to fix actual failure: https://github.com/riscv/riscv-compliance/pull/92
Works around #608
Following RISC-V privileged architecture version 1.11,
the "E" bit of misa should return the complement of the "I" bit.
Set the "I" bit only if RV32E is not used.
CloseslowRISC/ibex#612.
Use of case inside in always_ff block does not meet style guide
recomendations. Refactored to remove this.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
Add a section on supported tools to the Ibex documentation. Populate it
with my knowledge about tools we've tried. That's a starting point: we
need to add more version numbers and other information as we collect
more data points.
The Verilator version is taken from the new tool_requirements.py file
and inserted into Sphinx.
Define supported tool versions in tool_requirements.py, and check them
in a fusesoc run. If an unsupported tool version is found, fusesoc
outputs an error like this:
```
$ fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core
INFO: Preparing lowrisc:ibex:check_tool_requirements:0.1
INFO: Preparing lowrisc:prim:assert:0.1
INFO: Preparing lowrisc:ibex:sim_shared:0
INFO: Preparing lowrisc:ibex:ibex_core:0.1
INFO: Setting up project
INFO: Running pre_build script check_tool_requirements
ERROR: verilator is too old: found version 4.010, need at least 4.028
ERROR: Tool requirements not fulfilled. Please update the tools and retry.
ERROR: Failed to build lowrisc:ibex:ibex_core:0.1 : pre_build script 'check_tool_requirements' exited with error code 1
```
The only version checked at this point is Verilator, which is set
somewhat arbitrarily to the version used by me (and I know it works). CI
uses a slightly newer version. As we are about to merge changes soon
which require a newer Verilator version, there's not much point in
finding the oldest supported version right now.
* Integrate option to implement a multiplier using 3 parallel 17 bit
multipliers in order to compute MUL instructions in 1 cycle
MULH in 2 cycles.
* Add parameter SingleCycleMultiply to select single cycle
multiplication.
The single cycle multiplication capability is intended for FPGA
targets. Using three parallel multiplication units improves performance
of multiplication operations at the cost of DSP primitives. For ASIC
targets, the area consumed by the multiplication structure will grow
approximately 3-4x.
The functionality is selected within the module using the parameter
`SingleCycleMultiply`. From the top level it can be chosen by setting
the parameter `MultiplierImplementation` to 'single_cc'.
Signed-off-by: ganoam <gnoam@live.com>
- The slow multiplier is modified to terminate iterations early instead
of always going the full 32 iterations for `MUL` instructions.
- Multiplications now terminate early after clog2(`op_b`) iterations.
- The slow multiplier can be further optimized by swapping the smaller
operand into `op_b` when in the `MD_IDLE` state.
