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docs/datasheet
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Add a basic datasheet for RI5CY
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2015-09-09 18:35:07 +02:00 |
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include
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Add reg-reg and post-increment load/stores to tracer
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2015-09-29 14:10:29 +02:00 |
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.gitignore
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Added vim swap file
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2015-07-24 15:26:32 +02:00 |
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alu.sv
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Run through linter and do some cleanup
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2015-09-15 13:08:26 +02:00 |
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compressed_decoder.sv
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Cleanup compressed decoder
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2015-09-23 14:12:34 +02:00 |
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controller.sv
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Not taken branches do no longer waste cycles
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2015-09-30 13:06:22 +02:00 |
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cs_registers.sv
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Fixed synopsis syntax error
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2015-09-23 15:44:03 +02:00 |
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debug_unit.sv
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Rework pipeline flushes and exceptions
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2015-08-31 10:02:55 +02:00 |
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decoder.sv
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Edit comments in decoder
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2015-09-30 16:31:52 +02:00 |
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ex_stage.sv
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Decentralize stall control
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2015-09-21 18:26:08 +02:00 |
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exc_controller.sv
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Fix exception problem after stages are more independent
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2015-09-24 13:16:18 +02:00 |
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hwloop_controller.sv
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Finish hwloops addition
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2015-09-07 03:40:28 +02:00 |
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hwloop_regs.sv
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Cleanup unneeded signals and dead code
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2015-09-02 18:07:44 +02:00 |
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id_stage.sv
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Add MAC instruction, update regc (i.e. rs3) position
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2015-09-25 14:14:01 +02:00 |
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if_stage.sv
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Not taken branches do no longer waste cycles
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2015-09-30 13:06:22 +02:00 |
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load_store_unit.sv
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Decentralize stall control
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2015-09-21 18:26:08 +02:00 |
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mult.sv
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Run through linter and do some cleanup
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2015-09-15 13:08:26 +02:00 |
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prefetch_buffer.sv
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Rename instr_core_intf to prefetch_buffer, add if_busy signal again
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2015-09-10 13:12:19 +02:00 |
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prefetch_L0_buffer.sv
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Prefetcher now tells the core when it is safe to shut down
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2015-09-24 16:32:17 +02:00 |
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register_file.sv
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Fix linting errors/warnings and remove dead signals
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2015-08-28 17:15:55 +02:00 |
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riscv_core.sv
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Add reg-reg and post-increment load/stores to tracer
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2015-09-29 14:10:29 +02:00 |
