178 commits

Author	SHA1	Message	Date
stnolting	e7eaf09cd6	[docs] minor Vivado/ISIM updates	2024-11-02 21:13:09 +01:00
stnolting	2af4952cb8	[docs] update simulation sections	2024-11-01 07:23:19 +01:00
stnolting	9243491a65	[eclipse] update Eclipse project configuration ... add more customization variables to Eclipse makefile	2024-10-20 20:16:55 +02:00
stnolting	9c6cd3b3fc	[docs] add notes regarding ELF debug symbols	2024-09-08 13:44:09 +02:00
stnolting	cfe538eb96	[docs] UG: minor typo fixes ... fixing #1003	2024-09-05 16:25:34 +02:00
stnolting	47948ac8c2	[ug] vivado ip: add re-packaging note ... #895	2024-08-28 21:01:00 +02:00
stnolting	7873e2e508	[docs] remove VHDL2008 statement from Vivado IP ... addition to #996	2024-08-28 20:14:56 +02:00
stnolting	8b8c6fa805	[docs] ajust REGFILE_HW_RST text ... 💡 implementing the register file based on individual FFs (general logic resources) can improve timing	2024-08-28 20:12:54 +02:00
stnolting	213d0b8164	[ug] update section "General Hardware Setup"	2024-08-09 13:48:24 +02:00
stnolting	ae8cd86f7b	[docs] rework UG section "General Hardware Setup"	2024-08-09 08:11:17 +02:00
stnolting	bb3bed347a	[docs] minor edits	2024-08-09 08:10:41 +02:00
stnolting	7d0252f1a0	[vivado_ip] docs: top requires VHDL2008	2024-08-04 19:24:51 +02:00
NikLeberg	828cb65aa3	[docs] fix spelling	2024-08-04 14:04:10 +00:00
stnolting	db2b492343	[docs] minor edits	2024-08-02 07:51:07 +02:00
stnolting	c28ea75d45	[docs] minor edits	2024-07-31 20:19:04 +02:00
stnolting	f096fddb0f	[docs] minor fixes ... #968	2024-07-29 20:49:48 +02:00
stnolting	2bbfd954b8	[docs] ug: update bootloader console	2024-07-10 21:07:37 +02:00
stnolting	a44559c18c	[ug] eclipse: add xpack build tools note	2024-06-21 16:15:56 +02:00
stnolting	1429ada4cf	[docs] update JTAG signal list ... remove TRST	2024-06-17 21:43:41 +02:00
stnolting	ad8f71b26d	[docs/ug] eclipse: minor clarifications	2024-06-17 21:39:07 +02:00
stnolting	2cf9144c23	[docs/ug] add build tools and bin references	2024-06-16 10:53:40 +02:00
stnolting	f002c26b1f	[eclipse] add serial terminal to UG	2024-06-15 20:11:01 +02:00
stnolting	665f848ddf	[eclipse] add run configuration to example project	2024-06-15 19:48:59 +02:00
stnolting	f9cf153b9a	[docs/ug] add eclipse project tutorial	2024-06-15 08:34:07 +02:00
stnolting	689baa490a	[bootloader] increase auto-boot timeout ... from 8s to 10s	2024-06-14 15:07:04 +02:00
stnolting	a9ce1d49a5	[docs/ug] minor edits	2024-06-11 20:26:25 +02:00
stnolting	ba2f9e5851	[docs] UG: IP block typo fix	2024-05-29 18:58:59 +02:00
stnolting	1e274bf27e	[docs] update Vivado IP UG section	2024-05-16 17:41:43 +02:00
stnolting	a6b0d6e4a4	Add NEORV32 as Vivado IP (#894)	2024-05-05 18:23:18 +02:00
stnolting	fd88f5dee8	[docs] minor clean-up ... remove gitter link	2024-05-05 18:16:55 +02:00
stnolting	ed71771ec5	[docs] update user guide: vivado ip packaging	2024-05-04 16:10:37 +02:00
stnolting	8cb7e9d9da	minor cleanups ... trim Zbc	2024-04-04 19:59:07 +02:00
stnolting	fdbefaa44f	[docs] minor edits and updates	2024-03-21 20:29:58 +01:00
stnolting	24376dec58	[docs] update WISHBONE -> XBUS renaming	2024-03-12 21:54:48 +01:00
davidgussler	fa25b245c3	Updated user guide command to program external flash from 'p' to 's' to match the bootloader program.	2024-02-25 20:25:28 -05:00
stnolting	68b84ecc4a	[docs] Xilinx -> AMD	2024-02-24 08:49:31 +01:00
Robert Hancock	c2c8de0225	Added dummy clocks for SLINK streams in AXI4-Lite wrapper ... Fixes Vivado clock domain warnings/errors when connecting SLINK interfaces to other AXI4-Stream components	2024-02-23 17:23:36 -06:00
stnolting	b74d0e3789	[docs] update GHDL sim log	2024-02-20 22:38:52 +01:00
umarcor	7868c8fae2	[docs/userguide/simulating_the_processor] remove MARCH from the recommended hello_world simulation command; the default minimal extension subset will be used	2024-02-20 21:12:49 +01:00
umarcor	a88e050352	[docs/userguide/simulating_the_processor] recommend MARCH=rv32im to build hello_world, since the simple testbench has extension C disabled	2024-02-20 18:26:00 +01:00
umarcor	986de759f8	[docs/userguide/simulating_the_processor] add admonition about the processor hanging if intructions corresponding to disabled/unsupported extensions are used	2024-02-20 18:23:11 +01:00
stnolting	f6ea5b910b	[docs] minor fixes and edits	2024-02-18 19:02:17 +01:00
stnolting	c53a728981	[docs] add links to top logos	2024-02-04 20:04:34 +01:00
stnolting	31e312ee0c	[ug] remove redundant section ... "Enabling RISC-V CPU Extensions"	2024-01-27 13:28:54 +01:00
stnolting	30c9a15af6	[docs] minor cleanup	2024-01-08 16:01:54 +01:00
stnolting	6bc6da70e7	[docs/ug] update toolchain setup	2024-01-03 19:52:32 +01:00
stnolting	75db870bcd	[docs,ug] add bootloader ERR_EXE note ... #215	2023-11-30 19:34:25 +01:00
stnolting	b74efe5db4	[docs] fix broken WISHBONE links	2023-10-31 20:35:41 +01:00
stnolting	cc5a8f3779	[docs] update documentation	2023-10-28 14:59:19 +02:00
stnolting	95b3f9c131	[docs] Zifencei extension is now always enabled	2023-10-18 21:50:37 +02:00