stnolting
9cdd823284
[ug] add Vivado/ISIM sim-relaunch warning
2022-06-09 10:26:36 +02:00
stnolting
8e602356f1
[ug] typo fixes
2022-06-09 10:26:15 +02:00
stnolting
ed82af4b89
[ug] minor edits
2022-05-30 20:54:19 +02:00
stnolting
9862c634fa
Merge branch 'main' into bootloader_spi_rework
2022-05-29 13:25:42 +02:00
stnolting
3d9a7645eb
[ug] add note: hardcoded EBREAK instructions
2022-05-28 18:59:46 +02:00
stnolting
cdd4147ebc
[ug] add new SPI_FLASH_ADDR_BYTES configuration option
2022-05-20 17:08:39 +02:00
stnolting
1c51559224
[ug] remove flash requirements
...
will be added to the doc's bootloader section
2022-05-20 15:32:40 +02:00
stnolting
e543ed69eb
[docs] minor TRNG updates
2022-05-06 19:50:19 +02:00
stnolting
d181788b25
📚 remove A extension and LOCK signals
2022-04-27 14:08:08 +02:00
stnolting
119cff73a8
[rtl] make CPU front-end synchronous ( #300 )
...
* [sim] set explicit configuration IPB=2
* IPB entries have to be >=2
* make CPU frontend fully synchronous
* shortening critical path (memory system)
* reducing area costs
* add v1.7.0.3
* minor code cleanup
2022-04-13 12:21:46 +02:00
stnolting
f6bb7feb87
🐛 fix bug in crt0.S interrupt setup ( #297 )
...
* 🐛 fixed crt0 IRQ setup
The first thing crt0 has t do is to disable interrupts globally!
* update executable images
due to chnage of crt0.S
* add version 1.6.9.11
* add crt0 IRQ disable to docs
2022-04-08 17:00:02 +02:00
stnolting
3cb3886205
update documentation
2022-03-31 18:57:17 +02:00
stnolting
8a3f0151bf
Merge pull request #287 from ahmedcharles/patch-1
...
Typo fix
2022-03-31 18:26:12 +02:00
Ahmed Charles
815e24aedb
Fix the link using an asciidoc trick.
...
https://docs.asciidoctor.org/asciidoc/latest/macros/complex-urls/
2022-03-12 04:03:30 -08:00
Ahmed Charles
12a72307b0
Typo.
2022-03-12 03:44:14 -08:00
stnolting
a02e1c68ba
[docs] minor edits
2022-02-17 13:53:12 +01:00
stnolting
a4b8cfb373
[docs/userguide] add NEWLIB note
2022-02-16 19:30:25 +01:00
stnolting
9c9134c647
[docs] updated bootloader intro screen
2022-02-16 07:51:20 +01:00
stnolting
0fbdf962e2
[docs/userguide] reworked section "Debugging using the OCD"
...
added "hardware" breakpoint example
2022-02-10 08:06:38 +01:00
stnolting
5ffef777a7
updated links due to renamend default branch (-> main)
2022-02-08 16:57:22 +01:00
stnolting
b8c782b231
[docs/userguide] minor updates on bootloader console
2022-02-03 09:08:30 +01:00
stnolting
1470de8aed
[docs/userguide] custom hardware extension options: minor edits
2022-01-30 06:15:42 +01:00
stnolting
0e3a715e17
[docs/userguide] reworked section "Adding Custom Hardware Modules"
2022-01-29 15:00:02 +01:00
Marc Ludwig
62625799fa
[DOC] User Guide - 1.3. Installation
...
fix(doc): Closes #257 and changes `export PATH:$PATH:/opt/riscv/bin` to
`export PATH=$PATH:/opt/riscv/bin`.
2022-01-23 16:45:28 +01:00
stnolting
5a6d2bc668
[docs/userguide] added text segment vs. IMEM size note
2022-01-21 04:45:53 +01:00
stnolting
7828d0be5d
[docs/userguide] content: added neorv32-setups link
2022-01-19 19:55:09 +01:00
stnolting
7dd570623b
[docs] updated links to neorv32-setups
2022-01-17 05:02:23 +01:00
stnolting
eb58b7f71b
[docs] bootloader: added notes regarding 4kB upload issue
...
-> #215
2021-12-18 20:12:51 +01:00
stnolting
58e09023fe
[docs/userguide] note regardin IS_SIMULATION HW flag
2021-12-03 06:37:07 +01:00
stnolting
ccc7f263cc
[docs/userguide] NOTE: TRNG and Vivado block designs
...
#227
2021-12-02 15:48:45 +01:00
stnolting
ede9f2b44f
[docs/userguide] split user guide into several files
2021-11-29 11:09:33 +01:00
stnolting
82f57d8d39
⚠️ bootloader now stores executable as low-endian to flash
2021-11-28 16:18:04 +01:00
Mario Hoffmann
709d7bfa1c
Added a example serial terminal program for Linux which can easily send files.
...
Also fixed a minor typo in the preceding sentence.
2021-11-22 17:37:54 +01:00
stnolting
d3b716dafb
[docs] minor edits regarding DEFAULT mem sources
2021-11-04 00:48:48 +01:00
stnolting
da2893a252
[docs] added gitter badge
2021-11-03 13:45:31 +01:00
stnolting
c2f8bab4f7
[docs] typo fixes
2021-10-21 07:35:43 +02:00
stnolting
4e3d495219
[docs/userguide] minor typo fixes
2021-10-19 17:19:03 +02:00
stnolting
fdaaba3a0d
🪁 added link to upstream Zephyr RTOS support
...
https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html
port provided by @henrikbrixandersen
2021-10-18 18:36:08 +02:00
stnolting
d2fb1cec8b
[docs/userguide] added note: tri-state driver in vivado block designs
2021-10-18 15:44:02 +02:00
stnolting
d97df66b39
⚠️ modify handling of makefile's MARCH and MABI variables
...
Pre-commit usage: `MARCH=-march=rv32i`, the `-march` should not be here
Post-commit usage: `MARCH=rv32i`, this is more straightforward
Same for `MABI=-mabi=...` -> `MABI=...`
2021-10-15 17:20:55 +02:00
stnolting
06d1a7cd28
[docs/userguide] fixed official RISC-V gcc github link
2021-10-14 16:35:29 +02:00
stnolting
a31a24e940
[docs] fixing #181 (em dash vs. en dash)
2021-10-13 11:31:24 +02:00
stnolting
60415610c0
[docs/userguide] added how do breakpoints work
2021-09-28 16:24:37 +02:00
stnolting
96c7462ddc
🐛 [rtl/core] fixed bug in mtime coparator logic
...
"time >= timecmp" was not evaluated correctly (the split subword comparator was incorrect), which missed the interrupt for some time/timecmp combinations
2021-09-28 13:17:35 +02:00
stnolting
e3a07321de
[docs/userguide] minot edits
...
compilation _with_ debug symbols
2021-09-28 11:56:07 +02:00
stnolting
6cebb7b20a
[docs] minor edits
2021-09-28 08:39:40 +02:00
stnolting
e683d54d3d
[docs/userguide] new section "Adding Custom Hardware Modules"
2021-09-23 17:21:41 +02:00
umarcor
372a3f0a4a
[docs/userguide] update section 'Simulating the Processor'
2021-09-17 16:14:07 +02:00
Rafael Corsi
8e5d985976
[docs/userguide] update simulate instructions (new path)
2021-09-17 16:13:59 +02:00
stnolting
9c9495c69e
[docs] added split IMEM/DMEM
2021-09-13 20:59:03 +02:00
