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8436 commits 5 branches 75 tags 276 MiB
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2741 commits

Author SHA1 Message Date
stnolting
c1409c8514 [package] update version ID 2025-01-22 18:48:13 +01:00
stnolting
f9dabed06d Merge branch 'main' into pr/1165 2025-01-22 18:46:32 +01:00
stnolting
f370af147f [twd] sample ACK/NACK on rising edge of SCL 2025-01-21 21:41:45 +01:00
Lukas Pajak
78b270398e [rtl] use past SDA in twd FSM transition 2025-01-21 09:37:57 +01:00
stnolting
d043b71b56 [test_setups] update GPIO port sizes
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2025-01-19 20:50:13 +01:00
stnolting
87a78de173 [vivado_ip] minor GUI improvements 2025-01-19 20:31:49 +01:00
stnolting
456684c2b9 [vivado_ip] minor edits 2025-01-18 22:44:22 +01:00
stnolting
041f9d61a3 [axi4-bridge] allow back-to-back (atomic) transfers 2025-01-18 22:43:24 +01:00
stnolting
71d22cd5a6 [xbus] keep CYC active if atomic access 2025-01-18 22:38:38 +01:00
stnolting
1bf38b17d9 [amo_ctrl] allow error already during 1st operation (load) 2025-01-18 08:41:30 +01:00
stnolting
9c010e39bd [package] update version ID 2025-01-18 08:40:13 +01:00
stnolting
463ad44f5e [cache] minor cleanup 2025-01-18 08:39:57 +01:00
stnolting
9726fb6b29 [processor_templates] adjust GPIO port sizes
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2025-01-16 21:42:45 +01:00
stnolting
9785257b3c [package] update version ID 2025-01-16 18:40:01 +01:00
stnolting
02d7b6bab6 🐛 [twd] fix some design flaws 2025-01-16 16:40:27 +01:00
stnolting
bb01fb9af3
Merge branch 'main' into ohenley-patch-1 2025-01-15 21:33:05 +01:00
stnolting
93cb7d347f [rtl] update memory images 2025-01-15 21:14:50 +01:00
stnolting
54389e50d2 [vivado_ip] remove XIRQ; constrain GPIO ports 2025-01-15 20:14:06 +01:00
stnolting
cb38874e68 [vivado_ip] remove XIRQ 2025-01-15 20:13:51 +01:00
stnolting
7d29497559 ⚠️ [top] constrain GPIO ports to 32 bit 2025-01-15 20:08:04 +01:00
stnolting
2567296e42 [gpio] add CPU interrupt 2025-01-15 20:05:52 +01:00
stnolting
cdba1022c4 [rtl] rework GPIO controller 
add interrupt capabilities to input pins
 2025-01-15 20:05:08 +01:00
stnolting
b4cbc3b6cf ⚠️ remove XIRQ controller 2025-01-15 20:03:36 +01:00
olivier henley
cbb84a51b3
Update neorv32_ProcessorTop_MinimalBoot.vhd 
Bootstrap gpios to declared configuration

Signed-off-by: olivier henley <olivier.henley@gmail.com>
 2025-01-14 09:23:15 -05:00
stnolting
bccddc9bd7 [control] add missing signal to sensitivity list 2025-01-13 21:36:50 +01:00
stnolting
144cd4abce [rtl] update Vivado IP 2025-01-13 21:36:29 +01:00
stnolting
e1339fb939 [top] add WDT and OCD reset outputs 2025-01-12 00:41:27 +01:00
stnolting
265e333537 [rtl] sys: add reset synchronizers 2025-01-12 00:40:39 +01:00
stnolting
eac657f044 [rtl] minor comment edits 2025-01-11 23:10:53 +01:00
stnolting
6dc0206b7b [control] minor cleanups 2025-01-11 22:35:38 +01:00
stnolting
99ab672a19 [package] reserve CSR address for mxisah 
since we are running out of bits in MXISA 😅
 2025-01-11 22:35:17 +01:00
stnolting
76f157e690 [rtl] cpu: print config info only for core 0 2025-01-11 22:34:30 +01:00
stnolting
39f8a19da4 [package] update version ID 2025-01-11 19:10:37 +01:00
stnolting
01415e06ee [control] minor logic optimization 2025-01-11 19:10:27 +01:00
stnolting
1bba241f82 🐛 [top] fix ICC connection 2025-01-11 19:10:09 +01:00
stnolting
685eb82f25 [rtl] minor comment edits 2025-01-11 19:09:37 +01:00
stnolting
978fdb8ff8 [package] update version ID 2025-01-11 06:46:27 +01:00
stnolting
f2b06ed203 [rtl] comment typo fix 2025-01-10 21:42:27 +01:00
stnolting
2d00e4fe15 ✨ [cache] refine fence propagation 
for read-only caches: send fence/synchronization before reloading. for read-write caches: send fence/synchronization after flushing but before reloading
 2025-01-10 21:20:32 +01:00
stnolting
0b19ad00e6 [control] separate fence and fence.i instructions 2025-01-10 21:06:45 +01:00
stnolting
e551798ef7 [rtl] icc: minor comment edits 2025-01-10 11:12:26 +01:00
stnolting
82c1ef9f57 [rtl] update default memory images 2025-01-10 10:25:24 +01:00
stnolting
6eb9722df0 [rtl] ICC: comment edits 2025-01-10 08:55:33 +01:00
stnolting
86ca786e88 [top] rework core complex instances 
- directly instantiate all modules
- rework ICC wiring
 2025-01-10 08:44:50 +01:00
stnolting
0fa0bc22fe [cpu] rework ICC CSRs 
just use 2 CSRs instead of 4
 2025-01-10 08:36:35 +01:00
stnolting
46f2239299 [cpu] clean-up dual-core generics 2025-01-10 08:34:20 +01:00
stnolting
e794045f82 [cpu] simplify ICC links 
having only a single connection
 2025-01-10 08:32:15 +01:00
stnolting
91bf795701 ⚠️ [rtl] remove core_complex rtl file 2025-01-10 08:27:39 +01:00
stnolting
5fc77cb27d [package] update version ID 2025-01-09 23:31:57 +01:00
stnolting
99cb03080b [control] fix CSR read operations 2025-01-09 23:25:55 +01:00