stnolting
532b8d5d90
[sw/example] processor_test: added PRECISE illegal instr. checks
...
MTVAL and MEPC always have to reflect the _PRECISE_ state of the exception-causing instruction
2021-10-27 23:26:12 +02:00
stnolting
4def0602e1
[sw/example/hex_viewer] added byte/half/word modes #169
2021-10-20 15:36:02 +02:00
stnolting
da58d05767
[sw/example] updated processor_check
2021-10-17 09:58:15 +02:00
stnolting
d97df66b39
⚠️ modify handling of makefile's MARCH and MABI variables
...
Pre-commit usage: `MARCH=-march=rv32i`, the `-march` should not be here
Post-commit usage: `MARCH=rv32i`, this is more straightforward
Same for `MABI=-mabi=...` -> `MABI=...`
2021-10-15 17:20:55 +02:00
stnolting
082a08b57a
[sw/example/processor_check] updated IRQ config
2021-10-13 19:01:08 +02:00
stnolting
e44cb43819
[sw] no more use of "neorv32_uart_*" legacy wrappers
...
all of the software is now using `neorv32_uart0_*` instead of the legacy wrappers `neorv32_uart_*`; however, the legacy wrappers are still implemented
2021-10-12 16:19:18 +02:00
stnolting
8c92b2f0c3
[sw/example/processor_check] minor runtime optimizations
...
enable FIRQs only when they are actually relevant for evaluation
2021-10-09 10:58:34 +02:00
stnolting
786dc0e0f7
[sw] minor edits/fixes
...
- console output edits
- procesor_check: test if PMP test fails because of locked PMP entry
- fixed minor issue in number of PMP entries evaluation
2021-10-08 23:03:04 +02:00
stnolting
948c4dc045
[sw/example/processor_check] minor console output edits
2021-10-08 20:12:15 +02:00
stnolting
982c5e566e
🔧 updated processor_check test program
2021-10-08 19:26:18 +02:00
stnolting
22125a66fe
[sw] minor UART console output formatting edits
2021-10-08 17:25:36 +02:00
stnolting
2f6c8aa57b
[sw/example] benchmarks: minor fixes
2021-10-05 21:06:34 +02:00
stnolting
d10b495607
⚠️ removed mstatus.TW flag
...
timeout wait: WFI instruction is now always allowed to execute in any privilege mode; minor control unit logic optimization
2021-10-01 18:16:25 +02:00
stnolting
8c9bd42a47
[sw] minor edits in atomic instruction documentation and testing
2021-10-01 16:30:39 +02:00
stnolting
de4afd601f
minor typo fixes
2021-09-23 22:11:57 +02:00
stnolting
c7596c3a10
reworked external interrupts controller (XIRQ) handshake
2021-09-22 20:47:46 +02:00
stnolting
cd81575ea0
🐛 fixed instruction alignment exception bug
...
introduced in version 1.6.0.7
2021-09-22 10:04:12 +02:00
stnolting
6cbabd6aee
[sw/example] reworked processor_check test program
2021-09-21 22:56:00 +02:00
umarcor
edf86075ab
[doit] add task BuildAndInstallSoftwareFrameworkTests
2021-09-19 21:50:32 +02:00
stnolting
2cf4a59200
[sw/example] converted example programs
2021-09-17 18:29:57 +02:00
stnolting
511e37b6b6
[sw] optimized intrinsic libraries
...
Intirnsics (pseudo custom instructions) for "Zfinx" and "Zbb" extensions
* now using true inlining
* no more pseudo operations
-> faster execution; closer to the original/native instructions
2021-09-11 18:22:22 +02:00
stnolting
b28dbbd927
removed mstatus.sd and mstatus.fs bits
...
according to the revised specs. these mstatus bits are hardwired to zero / not used by the Zfinx extension
2021-09-11 07:30:25 +02:00
stnolting
eab859cb95
[sw/example/processor_check] minor edit
...
using custom instruction type with invalid opcode to check for illegal instruction exception
2021-09-09 10:36:33 +02:00
stnolting
a2ef87c2f8
[sw] added Zbb test program
...
using "intrinsics" for the Zbb instructions since there is no support in upstream gcc yet
2021-09-08 19:32:43 +02:00
stnolting
e4b29674a2
[sw] removed custom mzext CSR; moved info o new SYSINFO_CPU register
2021-08-19 13:32:05 +02:00
stnolting
0b1a478a0f
[sw/example/processor_check] added MRET test
2021-08-16 15:16:29 +02:00
stnolting
7259831b9a
[sw/example/dhrystone] minor edits
2021-08-15 16:18:18 +02:00
stnolting
6abfc3df64
[sw] added Dhrystone benchmark port
...
🚧 work in progress
2021-08-15 13:43:45 +02:00
stnolting
8cb3d4cf1f
🐛 [rtl] fixed DRET and MRET trapping
...
* `dret` has to trap if executed outside of debug-mode
* `mret` has to trap if executed in privilege modes less than machine-mode
2021-08-07 18:05:23 +02:00
stnolting
5d39d65e8c
[sw] added mstatus.SD and mstatus.FS bits
2021-08-05 17:31:08 +02:00
stnolting
55198c6170
[sw] typo fix (in comment)
2021-07-26 12:49:37 +02:00
stnolting
1f416745e5
[rtl,sw,docs] added 'mstatus.TW' CSR bit
2021-07-25 20:48:33 +02:00
stnolting
b1c1dd9923
[sw] reworked NEOLED module
2021-07-21 21:00:23 +02:00
umarcor
5b380dc56b
[sw/example] define NEORV32_HOME
2021-07-12 17:39:45 +02:00
stnolting
c849e2b5eb
[sw] added usage of central makefile
2021-07-12 17:39:45 +02:00
stnolting
0fcb1d57c8
[sw] moved central makefile to common
2021-07-12 17:39:45 +02:00
umarcor
7d4f89fd36
[sw/example] add common.mk
2021-07-12 17:39:44 +02:00
umarcor
ca8927e558
[sw] use RISCV_PREFIX instead of RISCV_TOOLCHAIN
2021-07-09 23:23:46 +02:00
stnolting
c541967e3a
🐛 fixed broken freeRTOS makefile #112
2021-07-09 12:57:17 +02:00
stnolting
8109de5590
minor edits
2021-07-09 12:49:05 +02:00
stnolting
6375439d17
minor edits, typo fixes and clean-ups
2021-07-06 15:37:28 +02:00
stnolting
805ddc4f00
[sw] clean-up of makefiles; added "hex" target
2021-07-06 15:35:22 +02:00
stnolting
a89a09d688
added XIRQ tests to processor check environment
2021-07-03 16:14:00 +02:00
stnolting
d111d65e90
added example program for new XIRQ controller
2021-07-03 16:12:40 +02:00
stnolting
b49edc6b48
[sw] increased GPIO ports from 32-bit to 64-bit; removed pin-change interrupt
...
* removed sw/example/demo_gpio_irq (obsolete now)
2021-06-30 18:26:43 +02:00
stnolting
cddf8b9d0f
[sw/example/processor_check] minor typo fix in UART1 test code
2021-06-29 15:50:34 +02:00
stnolting
b7a25826bf
[sw/example/processor_check] added SLINK check; added minimal UART result report output #89
2021-06-29 15:42:11 +02:00
stnolting
a7f3c8d35c
[sw] removed numerically-controlled oscillator (NCO) IO module
2021-06-27 14:53:46 +02:00
stnolting
f269884902
⚠️ [rtl,setups,sim,sw] removed top's FIRQ inputs
...
see CHANGELOG.md for more details
2021-06-27 12:01:44 +02:00
stnolting
2f15bf655c
[sw] minor edits
2021-06-26 15:39:01 +02:00
