.. |
ecppll.v
|
Add ulx3s 85k servant target
|
2020-04-23 00:10:08 +02:00 |
ice40_pll.v
|
Refactor to separate serv and servant
|
2019-06-24 13:18:34 +02:00 |
servant.v
|
Syntax and reset fixes for ModelSim
|
2020-11-10 15:16:19 +01:00 |
servant_ac701.v
|
servant: add AC701 board support
|
2020-09-30 15:32:33 +02:00 |
servant_arbiter.v
|
Simplify servant_arbiter
|
2019-10-29 21:53:13 +01:00 |
servant_clock_gen.v
|
Refactor to separate serv and servant
|
2019-06-24 13:18:34 +02:00 |
servant_ecp5.v
|
Add ulx3s 85k servant target
|
2020-04-23 00:10:08 +02:00 |
servant_ecp5_clock_gen.v
|
Add ulx3s 85k servant target
|
2020-04-23 00:10:08 +02:00 |
servant_gpio.v
|
Allow readback of GPIO signal
|
2019-11-19 10:46:30 +01:00 |
servant_lx9.v
|
Add support for LX9 Microboard
|
2020-05-06 20:51:55 +02:00 |
servant_lx9_clock_gen.v
|
Add support for LX9 Microboard
|
2020-05-06 20:51:55 +02:00 |
servant_mux.v
|
Allow readback of GPIO signal
|
2019-11-19 10:46:30 +01:00 |
servant_orangecrab.v
|
Add OrangeCrab R0.2 servant target
|
2020-07-26 23:57:49 +02:00 |
servant_ram.v
|
Syntax and reset fixes for ModelSim
|
2020-11-10 15:16:19 +01:00 |
servant_ram_quartus.sv
|
Sync up quartus-specific RAM to regular RAM module
|
2020-12-22 23:31:52 +01:00 |
servant_timer.v
|
Syntax and reset fixes for ModelSim
|
2020-11-10 15:16:19 +01:00 |
servant_upduino2.v
|
Add upduino2 servant target
|
2020-04-27 13:58:42 +02:00 |
servclone10.v
|
Add cyc1000 target
|
2020-02-29 15:29:07 +01:00 |
servclone10_clock_gen.v
|
Add cyc1000 target
|
2020-02-29 15:29:07 +01:00 |
service.v
|
Fix typo in service reset signal
|
2019-07-22 22:56:27 +02:00 |
servis.v
|
Add Saanlima pipistrello spartan6 LX45
|
2020-05-06 20:24:41 +02:00 |
servis_clock_gen.v
|
Add Saanlima pipistrello spartan6 LX45
|
2020-05-06 20:24:41 +02:00 |
servive.v
|
Add support for DE0 Nano
|
2020-09-29 17:57:26 +02:00 |
servive_clock_gen.v
|
Add support for DE0 Nano
|
2020-09-29 17:57:26 +02:00 |
servix.v
|
xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz)
|
2019-11-10 21:44:50 +01:00 |
servix_clock_gen.v
|
xilinx PLL: allows to specify PLL output frequency (16 or 32 MHz)
|
2019-11-10 21:44:50 +01:00 |
servus.v
|
Add zcu106 support to servant
|
2020-04-15 10:18:06 +02:00 |
servus_clock_gen.v
|
Add zcu106 support to servant
|
2020-04-15 10:18:06 +02:00 |