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SERV - The SErial RISC-V CPU
26 commits 8 branches 8 tags 17 MiB
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Olof Kindgren c2c162c2dd Update after changes to riscv-compliance repo
2018-11-18 22:32:25 +01:00
bench Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
cores Add modified core dependencies 2018-11-18 22:31:53 +01:00
data synthesized netlist works 2018-11-18 13:05:38 +01:00
picorv32_firmware Update firmware 2018-11-09 21:28:40 +01:00
riscv-target/serv Update after changes to riscv-compliance repo 2018-11-18 22:32:25 +01:00
rtl Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
barrel.mem Initial commit 2018-10-23 23:45:41 +02:00
bitbang.hex Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
decode.mem Initial commit 2018-10-23 23:45:41 +02:00
firmware.hex Update firmware 2018-11-09 21:28:40 +01:00
hellomin.hex synthesized netlist works 2018-11-18 13:05:38 +01:00
ser_add_tb.v Initial commit 2018-10-23 23:45:41 +02:00
serv.core Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
serv_top_tb.v Initial commit 2018-10-23 23:45:41 +02:00
testhalt.v Add explicit wire defs to ports 2018-11-17 21:30:03 +01:00
testprint.v Add explicit wire defs to ports 2018-11-17 21:30:03 +01:00