22 commits

Author	SHA1	Message	Date
Blaise Tine	a38d47c0df	riscv-tests update	2024-05-28 22:34:00 -07:00
Blaise Tine	68d2ac6f5e	32-bit/64-bit address space compatibility	2024-05-28 22:30:59 -07:00
Blaise Tine	f8ef570778	riscv tests refactoring	2024-05-28 10:46:31 -07:00
Blaise Tine	8a933520f0	minor update	2024-04-14 22:00:39 -07:00
Blaise Tine	6b81b26ffc	enabling Makefile configuration with build folder support	2024-03-30 02:28:39 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00
Blaise Tine	bda77760c8	addition bug fixes	2022-02-05 09:14:35 -05:00
Blaise Tine	cf2a0a5f39	code refactoring	2022-02-04 00:07:24 -05:00
Santosh Srivatsan	212ee21b54	Updated excluded 32-bit tests	2022-02-03 22:33:47 -05:00
Santosh Srivatsan	836c777680	XLEN parameterization for simx	2022-02-03 15:19:31 -05:00
Santosh Srivatsan	7aa93a735d	Added FLEN parameterization for RV32/64 F and D instructions	2022-01-24 15:42:15 -05:00
Santosh Srivatsan	91c22a2592	Fixed some riscv-tests	2022-01-22 12:54:10 -05:00
Santosh Srivatsan	a9e3104ce1	Removed ramulator log from tests/riscv/isa	2021-12-15 17:30:12 -05:00
Santosh Srivatsan	f93303bac7	Minor update	2021-12-15 17:21:38 -05:00
Santosh Srivatsan	039f5eb733	Moved 64-bit riscv-tests to tests/riscv/isa from tests/riscv/isa64	2021-12-13 20:21:51 -05:00
Blaise Tine	2a7a4df342	simx directory name fix	2021-11-30 07:17:58 -05:00
Blaise Tine	b8682f56ac	softfloat library integration	2021-10-10 13:20:50 -07:00
Blaise Tine	54bddeee9c	simulation framework refactoring	2021-10-09 10:20:42 -04:00
Blaise Tine	12b8b4af24	minor updates	2021-08-28 15:21:40 -07:00
Blaise Tine	93fee18d59	minor update	2021-07-01 02:59:44 -07:00
Blaise Tine	e8c01e18d8	regression fixes	2021-06-29 04:32:32 -04:00
Blaise Tine	03406c0a3f	project tests refactoring	2021-06-13 17:42:04 -07:00