21 commits

Author	SHA1	Message	Date
Blaise Tine	5c694a997c	update scope tap testing	2024-09-29 00:09:25 -07:00
Blaise Tine	87e613d29d	fixed XRT AFU deadlock on exit	2024-09-28 05:20:37 -07:00
Blaise Tine	e38c2c1fba	xilinx xrt platforms configuration	2024-09-23 02:12:47 -07:00
Blaise Tine	b8199decf4	opaesim and xrtsim multi-bank memory support	2024-09-22 03:54:40 -07:00
Blaise Tine	a37309c6b0	xrtsim implementation	2024-09-19 04:24:20 -07:00
Blaise Tine	7823f5529c	minor update	2024-09-08 01:38:48 -07:00
Blaise Tine	8db77ea1cd	minor updates	2024-09-05 21:29:01 -07:00
Blaise Tine	37555b1208	minor update	2024-09-04 15:18:39 -07:00
Blaise Tine	fd5903fef1	minor update	2024-09-04 03:34:25 -07:00
sij814	e34e4b790a	forced memory bank change in opae	2024-08-16 16:53:18 -07:00
Blaise Tine	2bc8a881b6	fixed trace log formatting	2024-07-30 12:05:36 -07:00
Blaise Tine	c8455eb562	minor update	2024-07-27 01:35:07 -07:00
Blaise Tine	3de14dd8bf	Verilator crash workaround	2024-07-24 16:09:27 -07:00
Blaise Tine	24e8e91a94	DramSim fix	2024-07-22 03:37:10 -07:00
Blaise Tine	a5377d78ca	minor update	2024-07-21 14:50:59 -07:00
Blaise Tine	fb141ae522	Ramulator 2.0 with HBM 2.0 support ... Verilator 5.0 support SimX C++17 requirement	2024-07-21 06:57:13 -07:00
Blaise Tine	0dbcddcb54	minor update	2024-07-14 03:12:30 -07:00
Blaise Tine	3efced37c5	trace INSTANCE_ID refactoring	2024-07-09 13:33:17 -07:00
Blaise Tine	60107cf2b6	XRT runtime and simulation support for Vortex AFU (incomplete)	2024-05-11 17:43:49 -07:00
Blaise Tine	840ced22a9	simx refactoring - emulation vs simulation discrete separation	2024-03-12 00:23:42 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00

Renamed from sim/vlsim/opae_sim.cpp (Browse further)