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3373 commits 27 branches 9 tags 1.6 GiB
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45 commits

Author SHA1 Message Date
tinebp
704f525fd6 memory mem_coalescer miss perf counter 
RTL perf counters refactoring
 2024-12-26 08:00:36 -08:00
tinebp
86f20b27dd SimX multi-ports memory fixes 2024-12-04 21:11:51 -08:00
tinebp
3ace9bbeda minor updates
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2024-12-04 06:00:19 -08:00
tinebp
3b454efd56 fixes to SimX's multiports memory support 2024-12-02 17:51:42 -08:00
jaewon-lee-github
bbc02cc013 merged with master 2024-10-03 13:44:39 -04:00
Jaewon Lee
4a606061d2
Merge branch 'develop' into tensor-core 2024-09-30 16:48:47 -04:00
Jaewon Lee
e91eb4aed4 merge from master branch 2024-09-12 10:32:02 -04:00
Hanran Wu
ea9560b33b merge 2024-08-23 17:44:24 -04:00
Blaise Tine
2bc8a881b6 fixed trace log formatting 2024-07-30 12:05:36 -07:00
Blaise Tine
95f59d23a8 simx memory coalescer bug fix 2024-07-23 00:02:43 -07:00
Blaise Tine
578c3d33d2 cumulative fixes 2024-07-15 10:13:57 -07:00
Blaise Tine
a2307a28dc perf counters update 2024-07-12 19:02:43 -07:00
Blaise Tine
42f3d55e15 SimX operands collector optimization 2024-07-12 04:54:44 -07:00
Jaewon Lee
02091f3d44 Merge Vortex 2.2 2024-06-22 23:55:01 -04:00
Jaewon Lee
cfcece940e Merge Austin's code (Preliminary) 2024-06-19 01:36:26 -04:00
Varsha Singhania
99c6a1af5a Tensor cores in Vortex 2024-06-17 04:28:51 -04:00
Blaise Tine
717b2e9ba1 enable barrier and spawn skip mode if N=1 2024-05-08 04:23:38 -07:00
Blaise Tine
189990e351 minor update 2024-05-06 00:54:07 -07:00
Blaise Tine
e84f978502 minor update 2024-05-01 00:02:52 -07:00
Blaise Tine
daf1360d83 minor single-thread fix 2024-04-20 22:32:28 -07:00
Blaise Tine
135cc4f5a7 minor update 2024-04-09 01:58:04 -07:00
Blaise Tine
402c911991 simx mem_coalescer 2024-03-24 20:31:36 -07:00
Blaise Tine
f1522e68f8 simx memory coalescing support 2024-03-14 12:20:39 -07:00
Blaise Tine
840ced22a9 simx refactoring - emulation vs simulation discrete separation 2024-03-12 00:23:42 -07:00
Blaise Tine
ff6f33acff simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_ 2024-03-11 15:39:49 -07:00
Blaise Tine
26d45ed9db renamed shared to local memory 2024-02-29 01:04:52 -08:00
Blaise Tine
b0b7cd2b1e minor updates 2024-02-03 19:09:53 -08:00
Blaise Tine
e217bc2c23 adding tracking for SFU stalls 2023-12-28 12:12:11 -08:00
Blaise Tine
c7a81d1493 adding sockets support to simx and cache subsystem refactoring 
minor update

minor update

minor updates
 2023-12-20 15:16:12 -08:00
Blaise Tine
e04e026a14 profiling update 
minor updates
 2023-12-18 04:43:44 -08:00
Blaise Tine
4b68235389 fixed simx dispatcher bug 2023-11-27 04:50:55 -08:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Santosh Srivatsan
b7e5a83ba3 Merged branch xlen-parameterization into staging 2022-02-05 13:47:42 -05:00
Blaise Tine
5fbace9fa0 fixed several bugs and refactor memory access 2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Santosh Srivatsan
836c777680 XLEN parameterization for simx 2022-02-03 15:19:31 -05:00
Blaise Tine
a06812f93f minor updates 2022-02-01 22:51:33 -05:00
Santosh Srivatsan
ad92c09f5b Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile 2022-01-22 13:47:44 -05:00
Blaise Tine
29df0da8b5 minor warning fixes 2022-01-10 20:33:37 -05:00
Santosh Srivatsan
4abfca4cb2 Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI 2021-12-13 19:55:02 -05:00
Santosh Srivatsan
885bb58ca9 Merged RV64IMFD extensions to master branch 2021-12-11 17:06:29 -05:00
Blaise Tine
5825b7c15a dram simulator fix 2021-12-07 22:44:06 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
092ff42ab4 simx multicore fix 2021-12-01 00:12:16 -05:00
Blaise Tine
2a7a4df342 simx directory name fix 2021-11-30 07:17:58 -05:00
Renamed from sim/simX/core.cpp (Browse further)