44 commits

Author	SHA1	Message	Date
MichaelJSr	0d04423074	Readded the ecall and ebreak instruction traps so that the riscv-vector tests run properly	2024-10-14 10:12:33 -07:00
jaewon-lee-github	bbc02cc013	merged with master	2024-10-03 13:44:39 -04:00
jaewon-lee-github	d1175a03c9	update the code accessing registers in obsoleted way	2024-10-02 14:16:57 -04:00
Jaewon Lee	4a606061d2	Merge branch 'develop' into tensor-core	2024-09-30 16:48:47 -04:00
Jaewon Lee	e91eb4aed4	merge from master branch	2024-09-12 10:32:02 -04:00
Blaise Tine	c4df7221c6	Merge branch 'master' of https://github.com/vortexgpgpu/vortex into develop	2024-09-02 04:13:35 -07:00
Blaise Tine	a38960674e	SimX split.N fix	2024-08-28 21:10:05 -07:00
Blaise Tine	41e41c9688	adjust SimX's split/join to match RTL.	2024-08-28 18:46:30 -07:00
Hanran Wu	ea9560b33b	merge	2024-08-23 17:44:24 -04:00
sij814	ea34239b43	changes made for initial feedback	2024-08-13 16:52:27 -07:00
sij814	de81baaabf	hbm for vortex 2.2	2024-08-12 02:52:47 -07:00
Blaise Tine	2bc8a881b6	fixed trace log formatting	2024-07-30 12:05:36 -07:00
Blaise Tine	e34f824bf9	minor update	2024-07-29 03:56:08 -07:00
Blaise Tine	2e060faaf4	reverting uuid format to ease file diff	2024-07-29 00:05:51 -07:00
Blaise Tine	48b1ab7494	fixed uuid format	2024-07-28 18:03:34 -07:00
Blaise Tine	382b686d59	reset GRPs only in debug mode	2024-07-28 17:40:03 -07:00
Blaise Tine	160c428ef5	fixed uuid format	2024-07-28 17:29:15 -07:00
Blaise Tine	578c3d33d2	cumulative fixes	2024-07-15 10:13:57 -07:00
Blaise Tine	a2307a28dc	perf counters update	2024-07-12 19:02:43 -07:00
Blaise Tine	42f3d55e15	SimX operands collector optimization	2024-07-12 04:54:44 -07:00
Blaise Tine	3efced37c5	trace INSTANCE_ID refactoring	2024-07-09 13:33:17 -07:00
Jaewon Lee	d531fa6b26	64bit support	2024-06-29 17:43:20 -04:00
Nayan Sivakumar Nair	5b0fc8cbd4	Fixes for PR	2024-06-25 03:18:50 -04:00
Jaewon Lee	02091f3d44	Merge Vortex 2.2	2024-06-22 23:55:01 -04:00
Nayan Sivakumar Nair	a378aed67c	Moved tc_num, tc_size param to makefile args	2024-06-21 22:23:24 -04:00
Jaewon Lee	862997fc94	Virtual Memory Support	2024-06-19 01:52:22 -04:00
Jaewon Lee	cfcece940e	Merge Austin's code (Preliminary)	2024-06-19 01:36:26 -04:00
Varsha Singhania	99c6a1af5a	Tensor cores in Vortex	2024-06-17 04:28:51 -04:00
Blaise Tine	e38187acb5	minor update	2024-06-08 02:47:31 -07:00
Blaise Tine	99eaaf6189	uuid_gen cleanup	2024-06-08 01:57:38 -07:00
Blaise Tine	6c56edf65d	minor update	2024-06-04 14:28:30 -07:00
Blaise Tine	f8ef570778	riscv tests refactoring	2024-05-28 10:46:31 -07:00
Blaise Tine	4e7bc9654b	wspawn fix	2024-05-10 21:42:20 -07:00
Blaise Tine	717b2e9ba1	enable barrier and spawn skip mode if N=1	2024-05-08 04:23:38 -07:00
Blaise Tine	badfb24e01	CSRs update	2024-05-06 00:51:38 -07:00
Blaise Tine	e84f978502	minor update	2024-05-01 00:02:52 -07:00
Blaise Tine	5ea10fd872	minor update	2024-04-30 22:47:59 -07:00
Blaise Tine	9df25ff48f	minor update	2024-04-28 04:42:22 -07:00
Blaise Tine	ac669a30ca	UUID refactoring	2024-04-14 22:01:03 -07:00
Blaise Tine	2488e4736c	minor update	2024-04-12 14:45:37 -07:00
Blaise Tine	25d0c76d14	enabling explicit kernel address and arguments allocation	2024-04-12 06:58:42 -07:00
Blaise Tine	7784dfe9b7	CSR 32-bit/64-bit refactoring	2024-04-09 02:00:34 -07:00
Blaise Tine	100eb49201	minor update	2024-03-14 12:57:02 -07:00
Blaise Tine	840ced22a9	simx refactoring - emulation vs simulation discrete separation	2024-03-12 00:23:42 -07:00