github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-20 20:11:24 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
3130 commits 27 branches 9 tags 1.6 GiB
Commit graph

264 commits

Author SHA1 Message Date
MalikBurton
7fc7bc0cab Runtime tests and riscv tests are runnable 2020-07-28 16:04:27 -04:00
Blaise Tine
7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
MalikBurton
e0f729e11e Deleted nativevecadd test as it's no longer compatible 2020-07-21 17:26:47 -04:00
MalikBurton
ccad86ff6d Makefile of vecadd along with the edited main files of working runtime tests 2020-07-21 13:15:17 -04:00
Blaise Tine
dc7efbcfb4 pipeline refactoring 2020-07-21 05:22:47 -04:00
MalikBurton
9b69cd430d Moved runtime/tests/vector_test directory to miscs/rvvector 2020-07-15 14:26:22 -04:00
MalikBurton
6df7181c74 Updated Makefiles of runtime/tests ,dev, hello, and nlTest 2020-07-14 19:18:01 -04:00
Blaise Tine
b7541a3172 adding built kernels 2020-06-29 02:01:51 -04:00
Blaise Tine
bc75147921 minor update 2020-06-27 15:34:59 -04:00
Blaise Tine
8a306de02d runtime static library 2020-06-27 14:13:13 -04:00
Blaise Tine
c9c34cb71a merge fixes 2020-06-23 14:40:29 -07:00
Blaise Tine
d1103733f5 merge fixes 2020-06-23 14:34:23 -07:00
Blaise Tine
b56fb31a6a fpga_synthesis merge 2020-06-23 12:41:26 -07:00
Blaise Tine
106d707024 verilator suppor for opae (partial) 2020-06-03 06:22:49 -04:00
Blaise Tine
611ceb000a fixed warp_sched lock bug 2020-05-28 08:52:20 -04:00
Blaise Tine
9e5885b820 adding dram writeenable support + scheduler bug fixes 2020-05-27 19:00:23 -04:00
Blaise Tine
d6c87dbb0a added debug print states or rtl 2020-05-16 14:19:17 -04:00
Blaise Tine
fcf3800d5d snooping response handling fix 2020-05-12 13:35:18 -04:00
Blaise Tine
cc84e0691c multicore fix 2020-05-10 08:30:04 -04:00
Blaise Tine
b1fdf0a947 fix rtl gpr zero 2020-05-06 05:25:20 -04:00
Blaise Tine
f142afac80 rtl refactoring 2020-05-04 20:12:05 -04:00
Blaise Tine
69f607b73e rtl refactoring 2020-05-03 17:10:02 -04:00
Blaise Tine
a1dc90b951 rtl cache refactory 2020-04-30 17:12:18 -04:00
Blaise Tine
81745f08c9 added config.vh 2020-04-16 07:49:19 -04:00
Blaise Tine
12dc4d6874 refactoring fixes 2020-04-14 19:39:59 -04:00
Blaise Tine
fc155e1223 project directories reorganization 2020-04-14 06:35:20 -04:00
Blaise Tine
6753f8e1b5 POCL llvm path settings via env 2020-04-06 10:30:38 -04:00
felsabbagh3
8c1b72691f Updated head location to 9-a 2020-04-02 19:41:53 -07:00
felsabbagh3
ba8bc95c90 Newlib update 2020-03-30 23:08:38 -07:00
felsabbagh3
d31b607e01 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis 2020-03-28 21:43:51 -07:00
felsabbagh3
313a8e3b4b All cache bugs fixed - Handshaking 2020-03-28 21:43:02 -07:00
Blaise Tine
c8a6470595 redesigned driver demo, fixed startup code, removed --cpu from simx, 2020-03-29 00:38:17 -04:00
felsabbagh3
5dc9493c61 ALL tests passing - handshake 2020-03-27 21:34:49 -07:00
Blaise Tine
f7e0d1e491 missing runtime changes from OPAE 2020-03-27 22:51:54 -04:00
Blaise Tine
96e960fa69 missing runtime changes from OPAE 2020-03-27 22:51:54 -04:00
Blaise Tine
5a5c9f3981 merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
Blaise Tine
9b1b8789ac merging changes from OPAE branch making this branch 2020-03-27 20:19:16 -04:00
felsabbagh3
614797e52f Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
felsabbagh3
39516a6f98 Migrating fpga_synthesis_temp to main 2020-03-27 13:15:23 -07:00
wgulian3
3b74f071a7 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
f126a23114 Generate define overrides based on env vars for C and Verilog. 
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
 2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
wgulian3
123fb17723 Remove VX_define.h and *_synth and runtime/config.h 2020-03-26 04:07:17 -04:00
felsabbagh3
4e6de0dc38 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
5372c07b01 Fixed most of the cache issues, mat_add left 2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
felsabbagh3
82ea79c680 Fix for Single-Threaded 2020-03-22 14:44:46 -07:00
Blaise Tine
8b4397f0ec fixed runtime Makefile 2020-03-16 14:58:02 -04:00
Blaise Tine
36547821fc temp files cleanup 2020-03-09 10:18:11 -04:00
Blaise Tine
717a75ade8 fixed opencl benchmarks 2020-03-09 09:55:16 -04:00