MichaelJSr
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91429e600f
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Added an option for generating riscv vector tests during regression testing
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2025-02-18 03:37:09 -08:00 |
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tinebp
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b59b30c75b
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minor udpate
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2025-02-03 22:40:33 -08:00 |
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tinebp
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22398c991d
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ramulator memory addressing bug fix + platform memory refactoring
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2025-01-26 06:28:51 -08:00 |
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tinebp
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4819891a5e
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minor update
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2024-12-17 18:06:52 -08:00 |
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tinebp
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066ab105eb
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multiports fixes
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2024-12-17 16:23:08 -08:00 |
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tinebp
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461f2cbbc9
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Intel Opae AFU support for multiport
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2024-12-13 21:20:38 -08:00 |
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tinebp
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7975a5a38c
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fixed AXI adapter
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2024-12-12 20:52:45 -08:00 |
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tinebp
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70ade222b1
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multiport
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2024-12-10 23:25:05 -08:00 |
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tinebp
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115ff2b599
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minor fixes
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2024-12-05 22:38:04 -08:00 |
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tinebp
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6b23d290c3
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vector ISA updates
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2024-12-05 14:43:51 -08:00 |
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tinebp
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5891a1e592
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Merge branch 'master' into riscv-vector-isa-simx-clean
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2024-12-05 10:17:05 -08:00 |
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tinebp
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3ace9bbeda
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minor updates
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2024-12-04 06:00:19 -08:00 |
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MichaelJSr
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073e0ddd10
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Adds the riscv vector extension into simx
Added vector regression test to ci.yml
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2024-11-27 23:22:22 -08:00 |
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tinebp
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5844de8c4d
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Merge branch 'rtl_cache'
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2024-11-13 22:27:11 -08:00 |
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Udit Subramanya
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667fa1662d
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update docker for micro apptainer
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2024-11-01 14:46:38 -04:00 |
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Blaise Tine
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5971158f43
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minor update
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2024-10-16 20:22:42 -07:00 |
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Blaise Tine
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e06333b3c0
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minor update
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2024-10-15 11:28:33 -07:00 |
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Blaise Tine
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2a2fc2ae39
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minor update
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2024-10-13 23:25:41 -07:00 |
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Blaise Tine
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28bf27e951
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rtl cache redesign to support xilinx bram types
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2024-10-13 03:40:45 -07:00 |
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Blaise Tine
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2eeb2ac532
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fixed memory flags propagation through the cache hierarchy
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2024-10-05 13:46:10 -07:00 |
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jaewon-lee-github
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5cf6797bd3
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- Change STARTUP_ADDR to use the same 0x80000000 address
- Fix environment variable for vortex kernel directories
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2024-10-03 15:19:39 -04:00 |
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jaewon-lee-github
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bbc02cc013
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merged with master
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2024-10-03 13:44:39 -04:00 |
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Jaewon Lee
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4a606061d2
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Merge branch 'develop' into tensor-core
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2024-09-30 16:48:47 -04:00 |
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Blaise Tine
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a3031922ce
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minor update
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2024-09-29 09:07:45 -07:00 |
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Blaise Tine
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5c694a997c
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update scope tap testing
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2024-09-29 00:09:25 -07:00 |
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Blaise Tine
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30571d716c
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updated scope CI test
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2024-09-28 21:37:48 -07:00 |
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Blaise Tine
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0e3206747a
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scope_tap bug fix
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2024-09-24 21:46:26 -07:00 |
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Blaise Tine
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818522f7e4
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CI scripts update
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2024-09-23 05:57:08 -07:00 |
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Blaise Tine
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030071571d
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test memory bank interleaving
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2024-09-23 04:30:28 -07:00 |
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Blaise Tine
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e5e9a5c2e9
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build fix
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2024-09-23 04:03:04 -07:00 |
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Blaise Tine
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406583c0bd
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build fix
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2024-09-23 04:00:23 -07:00 |
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Blaise Tine
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e38c2c1fba
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xilinx xrt platforms configuration
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2024-09-23 02:12:47 -07:00 |
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Blaise Tine
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b8199decf4
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opaesim and xrtsim multi-bank memory support
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2024-09-22 03:54:40 -07:00 |
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jaewon-lee-github
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4383631543
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Add BARE mode test and print out VM info
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2024-09-20 09:58:50 -04:00 |
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jaewon-lee-github
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9cc0010835
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change verilator path
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2024-09-20 09:19:17 -04:00 |
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jaewon-lee-github
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9902856221
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VERILATOR
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2024-09-20 09:05:54 -04:00 |
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jaewon-lee-github
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e5f2442353
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Update Virtual Memory testing
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2024-09-20 08:58:11 -04:00 |
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Blaise Tine
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63cce35c1a
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scope taps annotation
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2024-09-19 23:33:23 -07:00 |
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Blaise Tine
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a37309c6b0
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xrtsim implementation
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2024-09-19 04:24:20 -07:00 |
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Jaewon Lee
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e91eb4aed4
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merge from master branch
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2024-09-12 10:32:02 -04:00 |
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Blaise Tine
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fa11d4c502
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TRACING refactoring to support vivado/quartus simulators
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2024-09-08 05:26:00 -07:00 |
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Blaise Tine
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aa1489d8eb
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fixed trace.vcd copy
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2024-09-07 03:45:23 -07:00 |
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Blaise Tine
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8d1baf677d
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minor update
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2024-09-04 18:17:27 -07:00 |
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Blaise Tine
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37555b1208
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minor update
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2024-09-04 15:18:39 -07:00 |
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Blaise Tine
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19d6142023
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fixed fpu serialization
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2024-09-03 04:54:29 -07:00 |
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Blaise Tine
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fc5bb387a2
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minor update
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2024-08-29 03:02:50 -07:00 |
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Blaise Tine
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b6879b25e3
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switching to python3 dependency
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2024-08-24 20:46:25 -07:00 |
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Hanran Wu
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ea9560b33b
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merge
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2024-08-23 17:44:24 -04:00 |
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Blaise Tine
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5e241c153c
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Ci script update
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2024-08-19 18:36:37 -07:00 |
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Blaise Tine
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693a9f648d
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Ci script update
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2024-08-19 18:25:38 -07:00 |
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