Blaise Tine
|
4fa540575c
|
fixed gpr_ram bug + io bus arbitration
|
2020-06-13 05:26:29 -07:00 |
|
Blaise Tine
|
d6b0ef2b3c
|
scope refactoring + snoop invalidate
|
2020-06-12 00:04:31 -07:00 |
|
Blaise Tine
|
19f263c772
|
scope fixes
|
2020-06-09 20:49:36 -07:00 |
|
Blaise Tine
|
1688c65050
|
scope fixes
|
2020-06-09 10:19:28 -04:00 |
|
Blaise Tine
|
457783322b
|
scope fixes
|
2020-06-09 07:03:52 -07:00 |
|
Blaise Tine
|
9575fe9a51
|
scope fixes
|
2020-06-08 06:54:47 -07:00 |
|
Blaise Tine
|
170c88f295
|
scope fixes
|
2020-06-08 04:25:28 -07:00 |
|
Blaise Tine
|
9ae38433fb
|
VX_pipeline refactoring + logic analyzer
|
2020-06-06 01:52:44 -04:00 |
|
Blaise Tine
|
c4f2488dbe
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
t
# the commit.
|
2020-06-04 15:44:40 -07:00 |
|
Blaise Tine
|
4e0e710182
|
OPAE rtl fixes
|
2020-06-04 15:44:03 -07:00 |
|
Blaise Tine
|
171d46b501
|
fix l2 cache issues
|
2020-06-04 18:34:14 -04:00 |
|
Blaise Tine
|
ea890b457d
|
fixed msrq regression
|
2020-06-03 17:22:24 -04:00 |
|
Blaise Tine
|
9eb0389717
|
minor update
|
2020-06-03 06:40:25 -04:00 |
|
Blaise Tine
|
626a4f6fc1
|
merge
|
2020-06-03 06:25:34 -04:00 |
|
Blaise Tine
|
106d707024
|
verilator suppor for opae (partial)
|
2020-06-03 06:22:49 -04:00 |
|
Blaise Tine
|
04fc34b848
|
minor update
|
2020-06-03 03:05:45 -07:00 |
|
Blaise Tine
|
9b186dcc6e
|
fixed L2 cache
|
2020-06-02 05:32:50 -07:00 |
|
Blaise Tine
|
e01c411b20
|
opae rtl fixes
|
2020-06-01 23:06:13 -07:00 |
|
Blaise Tine
|
16d5a8a09c
|
opae rtl fixes
|
2020-05-31 14:51:42 -07:00 |
|
Blaise Tine
|
6a3b237054
|
minor update
|
2020-05-29 00:57:59 -04:00 |
|
felsabbagh3
|
033381ab6f
|
Force correct word selection when BANK_LINE_WORD=1
|
2020-05-28 20:39:39 -07:00 |
|
Blaise Tine
|
33b273b204
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-28 18:34:25 -04:00 |
|
Blaise Tine
|
b930a822ad
|
minor updates
|
2020-05-28 18:34:03 -04:00 |
|
Blaise Tine
|
611ceb000a
|
fixed warp_sched lock bug
|
2020-05-28 08:52:20 -04:00 |
|
Blaise Tine
|
9e5885b820
|
adding dram writeenable support + scheduler bug fixes
|
2020-05-27 19:00:23 -04:00 |
|
Blaise Tine
|
61231cd2af
|
OPAE rtl fixes
|
2020-05-24 02:42:56 -07:00 |
|
Blaise Tine
|
a9f896b4f3
|
fixed snoop forwarding bug and single bank support
|
2020-05-24 04:29:43 -04:00 |
|
Blaise Tine
|
47ed6b18ff
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-24 01:37:55 -04:00 |
|
felsabbagh3
|
a1e9b512b0
|
Added mrvq_recover_ready_state_st2 to optimize fills sent
|
2020-05-23 21:47:51 -07:00 |
|
felsabbagh3
|
0cd9bd689e
|
Added schedule_ptr to mrvq for speculative pops
|
2020-05-23 21:36:57 -07:00 |
|
Blaise Tine
|
3a9e79d979
|
revert byte_enable tag structure
|
2020-05-23 22:23:25 -04:00 |
|
Blaise Tine
|
c54fa50715
|
fixed snoop forwarder dequue to support out of order responses
|
2020-05-23 20:19:54 -04:00 |
|
Blaise Tine
|
507622f1a1
|
fixed simulator snoop handling
|
2020-05-23 19:26:59 -04:00 |
|
Blaise Tine
|
6882d88a62
|
removed fill_invalidator (not needed anymore)
|
2020-05-23 19:24:52 -04:00 |
|
Blaise Tine
|
f3b21aab8f
|
remove unsued cache parameter LLVQ_SIZE
|
2020-05-23 00:33:51 -04:00 |
|
Blaise Tine
|
70dadca9fe
|
fix scheduler rename_table X values - reverted valid bits
|
2020-05-23 00:22:56 -04:00 |
|
Blaise Tine
|
b02fc14da6
|
fill invalifator fix + refactoring
|
2020-05-21 20:38:55 -07:00 |
|
Blaise Tine
|
70c70407c9
|
minor update
|
2020-05-21 12:08:16 -07:00 |
|
Blaise Tine
|
3c8620e770
|
minor update
|
2020-05-21 14:51:56 -04:00 |
|
Blaise Tine
|
cf22ef2bf3
|
minor update
|
2020-05-21 13:42:08 -04:00 |
|
Blaise Tine
|
d12c40131e
|
optimize generic_queue to support simple model for smaller size queues
|
2020-05-21 04:04:27 -04:00 |
|
Blaise Tine
|
276fa5c919
|
optimize generic_queue to support simple model for smaller size queues
|
2020-05-21 03:34:03 -04:00 |
|
felsabbagh3
|
7e091b53f8
|
Added valid_table in scheduler and removed rename_table on reset
|
2020-05-20 23:02:41 -07:00 |
|
Blaise Tine
|
1102871180
|
force random values for unitialized signals
|
2020-05-20 20:57:15 -04:00 |
|
Blaise Tine
|
7e5fed3ec1
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
|
2020-05-20 18:27:20 -04:00 |
|
Blaise Tine
|
d4cb8b6f66
|
fixed renaem table reset logic
|
2020-05-20 18:24:09 -04:00 |
|
Blaise Tine
|
72d54c749c
|
fixed cache msrq reset logic
|
2020-05-20 18:11:31 -04:00 |
|
Blaise Tine
|
e1b4862f85
|
minor update
|
2020-05-20 14:14:29 -07:00 |
|
Blaise Tine
|
cefd0d85af
|
rtl refactoring
|
2020-05-20 16:59:14 -04:00 |
|
Blaise Tine
|
b5569dd525
|
OPAE rtl fixes
|
2020-05-20 12:08:10 -07:00 |
|