48 commits

Author	SHA1	Message	Date
Blaise Tine	a06812f93f	minor updates	2022-02-01 22:51:33 -05:00
Blaise Tine	18762dffce	fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,	2021-11-24 00:00:17 -05:00
Blaise Tine	bf72800676	debug tracing refactoring	2021-10-17 13:42:16 -07:00
Blaise Tine	58a2140b92	merge update	2021-10-15 19:58:13 -07:00
Blaise Tine	e380ded5e1	Merge branch 'master' into graphics	2021-10-15 19:32:11 -07:00
Blaise Tine	1cd833d2c4	minor fixes	2021-10-11 19:02:13 -07:00
Blaise Tine	28e26f3130	minor update	2021-10-09 13:19:46 -07:00
Blaise Tine	54bddeee9c	simulation framework refactoring	2021-10-09 10:20:42 -04:00
Blaise Tine	9f34b2944c	code refactoring for Vivado, sv2v, and yosys compatibility	2021-09-27 08:55:10 -04:00
Blaise Tine	9b04f3d9d6	Updated README and synthesis scripts	2021-09-22 07:50:47 -07:00
Blaise Tine	26e94dde44	cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores	2021-08-26 12:27:38 -07:00
Blaise Tine	2a27bfbfd5	LKG Build (reset network update -fmax=236 mhz 4c)	2021-08-23 01:59:22 -07:00
Blaise Tine	bb1ceffadd	rebase master update	2021-07-30 21:03:14 -07:00
Blaise Tine	0319283ea7	minor update	2021-07-20 21:42:22 -07:00
Blaise Tine	6b641ceb21	minor update	2021-07-17 15:26:04 -07:00
Blaise Tine	ff5ec3adc8	minor update	2021-07-17 07:23:35 -07:00
Blaise Tine	5c58f7eec6	minor update	2021-07-16 12:57:50 -07:00
Blaise Tine	f84c8a0b5d	instr_sched => ibuffer	2021-06-27 19:36:43 -07:00
Blaise Tine	57143f5889	synthesis optimizations	2021-06-17 16:43:43 -07:00
Blaise Tine	47c3234659	minor update	2021-06-13 10:58:48 -07:00
Blaise Tine	3cc1190cd7	CSRs I/O refactoring	2021-06-11 03:08:07 -07:00
Blaise Tine	adf033b0aa	non-cacheable memory address critical paths optimizations	2021-06-10 12:47:18 -07:00
Blaise Tine	b14825c8b9	update fpga build settings	2021-06-04 20:45:56 -07:00
Blaise Tine	7095a46066	minor update	2021-05-18 11:15:36 -07:00
Blaise Tine	bde6a69ea0	adding support for multi-banks memory bus	2021-05-04 07:32:03 -07:00
Blaise Tine	ba16e88eab	stress test update	2021-05-03 12:24:41 -07:00
Blaise Tine	d504adb236	afu mem controller refactoring	2021-05-01 08:39:52 -07:00
Blaise Tine	95f057bc2e	fpga build refactoring	2021-04-29 06:17:28 -07:00
Blaise Tine	0910f95616	code refactoring	2021-04-26 02:35:50 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	aff5903a22	minor ibuffer critical path optimization.	2021-04-19 20:53:13 -07:00
Blaise Tine	9f1b84e144	minor update	2021-04-04 23:46:07 -07:00
Blaise Tine	9aa4168def	build scripts update	2021-04-05 02:30:08 -04:00
Blaise Tine	0ea22a059c	minor updates	2021-04-04 22:54:07 -07:00
Blaise Tine	2ce6dbb495	minor update	2021-04-04 17:57:35 -07:00
Blaise Tine	a84a6fe8a9	minor update	2021-03-30 13:18:32 -07:00
Blaise Tine	1f0be84eea	16 core specific json file	2021-03-29 23:41:48 -07:00
Blaise Tine	817bc711c8	fixed startix10 build configuration	2021-03-23 08:34:35 -07:00
Blaise Tine	c8af5a8f45	minor update	2021-03-01 02:56:58 -08:00
Blaise Tine	a9cb0b4ec1	minor update - asesim fix	2021-02-28 17:30:21 -08:00
Blaise Tine	3e961c4e6e	minor update	2021-02-21 15:14:46 -08:00
Blaise Tine	258eb633a6	minor update	2021-02-20 13:16:25 -08:00
Blaise Tine	05f93fac20	minor update	2021-02-20 13:15:15 -08:00
Blaise Tine	31b3e380dc	minor update	2021-02-15 09:23:40 -08:00
Blaise Tine	073964fdf7	minor update	2021-02-12 08:52:06 -08:00
Blaise Tine	665b97b810	multi-ported cache support for streaming	2021-02-08 16:13:32 -08:00
Blaise Tine	fd1726197b	cache merge optimization	2021-02-07 07:33:39 -08:00
Blaise Tine	de2e118cc2	move opae to /hw/syn/	2021-01-25 02:32:49 -08:00