mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
First Commit: Cloned grlib-gpl-2017.2-b4194
This commit is contained in:
lcbcFoo
commit
39dd8da4f8
2819 changed files with 2075921 additions and 0 deletions
2
Makefile
Normal file
2
Makefile
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|
@ -0,0 +1,2 @@
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|||
include bin/Makefile
|
||||
|
||||
1852
bin/Makefile
Normal file
1852
bin/Makefile
Normal file
File diff suppressed because it is too large
Load diff
135
bin/Makefile.config
Normal file
135
bin/Makefile.config
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|
|
@ -0,0 +1,135 @@
|
|||
CONFDEP = $(GRLIB)/lib/testgrouppolito/pr/pr.in \
|
||||
$(GRLIB)/lib/grlib/util/debug.in \
|
||||
$(GRLIB)/lib/grlib/amba/amba.in \
|
||||
$(GRLIB)/lib/esa/memoryctrl/mctrl.in \
|
||||
$(GRLIB)/lib/esa/pci/pci_arb.in \
|
||||
$(GRLIB)/lib/gaisler/leon3/leon3.in \
|
||||
$(GRLIB)/lib/gaisler/leon3/l3stat.in \
|
||||
$(GRLIB)/lib/gaisler/can/can_oc.in \
|
||||
$(GRLIB)/lib/gaisler/can/grcan.in \
|
||||
$(GRLIB)/lib/gaisler/can/can_mc.in \
|
||||
$(GRLIB)/lib/gaisler/spacewire/router.in \
|
||||
$(GRLIB)/lib/gaisler/spacewire/spacewire.in \
|
||||
$(GRLIB)/lib/gaisler/usb/grusb_dcl.in \
|
||||
$(GRLIB)/lib/gaisler/usb/grusbdc.in \
|
||||
$(GRLIB)/lib/gaisler/usb/grusbhc.in \
|
||||
$(GRLIB)/lib/gaisler/pci/pcitrace/pcitrace.in \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci2/grpci2.in \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci1/pci_mtf.in \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci1/pci_target.in \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci1/pci.in \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci1/pcidma.in \
|
||||
$(GRLIB)/lib/gaisler/misc/svgactrl.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ps2.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbstat.in \
|
||||
$(GRLIB)/lib/gaisler/misc/gptimer.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbrom.in \
|
||||
$(GRLIB)/lib/gaisler/misc/grgpio2.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ftahbram.in \
|
||||
$(GRLIB)/lib/gaisler/misc/gracectrl.in \
|
||||
$(GRLIB)/lib/gaisler/misc/grgpio.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ps2vga.in \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbram.in \
|
||||
$(GRLIB)/lib/gaisler/misc/grsysmon.in \
|
||||
$(GRLIB)/lib/gaisler/pcie/pcie.in \
|
||||
$(GRLIB)/lib/gaisler/gr1553b/gr1553b.in \
|
||||
$(GRLIB)/lib/gaisler/gr1553b/gr1553b_2.in \
|
||||
$(GRLIB)/lib/gaisler/uart/dcom.in \
|
||||
$(GRLIB)/lib/gaisler/uart/uart1.in \
|
||||
$(GRLIB)/lib/gaisler/uart/uart2.in \
|
||||
$(GRLIB)/lib/gaisler/jtag/bscan.in \
|
||||
$(GRLIB)/lib/gaisler/jtag/jtag.in \
|
||||
$(GRLIB)/lib/gaisler/jtag/jtag2.in \
|
||||
$(GRLIB)/lib/gaisler/spi/spimctrl.in \
|
||||
$(GRLIB)/lib/gaisler/spi/spi2ahb.in \
|
||||
$(GRLIB)/lib/gaisler/spi/spictrl.in \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2cslv.in \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2c.in \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2c2ahb.in \
|
||||
$(GRLIB)/lib/gaisler/irqmp/irqmp.in \
|
||||
$(GRLIB)/lib/gaisler/subsys/leon_dsu_stat_base.in \
|
||||
$(GRLIB)/lib/gaisler/net/edcl.in \
|
||||
$(GRLIB)/lib/gaisler/leon4/l4stat.in \
|
||||
$(GRLIB)/lib/gaisler/leon4/leon4.in \
|
||||
$(GRLIB)/lib/gaisler/greth/greth.in \
|
||||
$(GRLIB)/lib/gaisler/greth/greth2.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftsrctrl.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ssrctrl.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/srctrl.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftsdctrl.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftmctrl.in \
|
||||
$(GRLIB)/lib/gaisler/memctrl/sdctrl.in \
|
||||
$(GRLIB)/lib/gaisler/ddr/mig_7series.in \
|
||||
$(GRLIB)/lib/gaisler/ddr/mig.in \
|
||||
$(GRLIB)/lib/gaisler/ddr/ddr2sp.in \
|
||||
$(GRLIB)/lib/gaisler/ddr/ddrsp.in \
|
||||
$(GRLIB)/lib/gaisler/l2cache/l2c.in \
|
||||
$(GRLIB)/lib/techmap/clocks/clkgen.in \
|
||||
$(GRLIB)/lib/techmap/gencomp/tech.in \
|
||||
$(GRLIB)/lib/techmap/gencomp/clkgen.in \
|
||||
|
||||
HELPDEP = $(GRLIB)/lib/testgrouppolito/pr/pr.in.help \
|
||||
$(GRLIB)/lib/grlib/util/debug.in.help \
|
||||
$(GRLIB)/lib/grlib/amba/amba.in.help \
|
||||
$(GRLIB)/lib/esa/memoryctrl/mctrl.in.help \
|
||||
$(GRLIB)/lib/esa/pci/pci_arb.in.help \
|
||||
$(GRLIB)/lib/gaisler/leon3/leon3.in.help \
|
||||
$(GRLIB)/lib/gaisler/leon3/l3stat.in.help \
|
||||
$(GRLIB)/lib/gaisler/can/can_oc.in.help \
|
||||
$(GRLIB)/lib/gaisler/can/grcan.in.help \
|
||||
$(GRLIB)/lib/gaisler/can/can_mc.in.help \
|
||||
$(GRLIB)/lib/gaisler/spacewire/spacewire.in.help \
|
||||
$(GRLIB)/lib/gaisler/spacewire/router.in.help \
|
||||
$(GRLIB)/lib/gaisler/usb/grusbhc.in.help \
|
||||
$(GRLIB)/lib/gaisler/usb/grusb_dcl.in.help \
|
||||
$(GRLIB)/lib/gaisler/usb/grusbdc.in.help \
|
||||
$(GRLIB)/lib/gaisler/pci/pcitrace/pcitrace.in.help \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci2/grpci2.in.help \
|
||||
$(GRLIB)/lib/gaisler/pci/grpci1/pci.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/gptimer.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ps2vga.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbram.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/gracectrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbstat.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/grgpio2.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/svgactrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ps2.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/grsysmon.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/grgpio.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ftahbram.in.help \
|
||||
$(GRLIB)/lib/gaisler/misc/ahbrom.in.help \
|
||||
$(GRLIB)/lib/gaisler/pcie/pcie.in.help \
|
||||
$(GRLIB)/lib/gaisler/gr1553b/gr1553b_2.in.help \
|
||||
$(GRLIB)/lib/gaisler/gr1553b/gr1553b.in.help \
|
||||
$(GRLIB)/lib/gaisler/uart/uart2.in.help \
|
||||
$(GRLIB)/lib/gaisler/uart/uart1.in.help \
|
||||
$(GRLIB)/lib/gaisler/uart/dcom.in.help \
|
||||
$(GRLIB)/lib/gaisler/jtag/jtag2.in.help \
|
||||
$(GRLIB)/lib/gaisler/jtag/bscan.in.help \
|
||||
$(GRLIB)/lib/gaisler/jtag/jtag.in.help \
|
||||
$(GRLIB)/lib/gaisler/spi/spictrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/spi/spi2ahb.in.help \
|
||||
$(GRLIB)/lib/gaisler/spi/spimctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2c.in.help \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2cslv.in.help \
|
||||
$(GRLIB)/lib/gaisler/i2c/i2c2ahb.in.help \
|
||||
$(GRLIB)/lib/gaisler/irqmp/irqmp.in.help \
|
||||
$(GRLIB)/lib/gaisler/subsys/leon_dsu_stat_base.in.help \
|
||||
$(GRLIB)/lib/gaisler/net/edcl.in.help \
|
||||
$(GRLIB)/lib/gaisler/leon4/leon4.in.help \
|
||||
$(GRLIB)/lib/gaisler/leon4/l4stat.in.help \
|
||||
$(GRLIB)/lib/gaisler/greth/greth.in.help \
|
||||
$(GRLIB)/lib/gaisler/greth/greth2.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ssrctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/sdctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftsdctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftmctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/ftsrctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/memctrl/srctrl.in.help \
|
||||
$(GRLIB)/lib/gaisler/ddr/ddrsp.in.help \
|
||||
$(GRLIB)/lib/gaisler/ddr/ddr2sp.in.help \
|
||||
$(GRLIB)/lib/gaisler/l2cache/l2c.in.help \
|
||||
$(GRLIB)/lib/techmap/clocks/clkgen.in.help \
|
||||
$(GRLIB)/lib/techmap/gencomp/tech.in.help \
|
||||
$(GRLIB)/lib/techmap/gencomp/clkgen.in.help \
|
||||
|
||||
172
bin/ahbrom.c
Normal file
172
bin/ahbrom.c
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <unistd.h>
|
||||
#ifdef WIN32
|
||||
#include <winsock2.h>
|
||||
#endif
|
||||
|
||||
main (argc, argv)
|
||||
int argc; char **argv;
|
||||
{
|
||||
struct stat sbuf;
|
||||
unsigned char x[128];
|
||||
int i, j, res, fsize, abits, tmp, dbits, alow;
|
||||
FILE *fp, *wfp;
|
||||
char *suffix = "";
|
||||
char *xgeneric = "";
|
||||
|
||||
if (argc < 3) exit(1);
|
||||
res = stat(argv[1], &sbuf);
|
||||
if (res < 0) exit(2);
|
||||
fsize = sbuf.st_size;
|
||||
fp = fopen(argv[1], "rb");
|
||||
wfp = fopen(argv[2], "w+");
|
||||
if (fp == NULL) exit(2);
|
||||
if (wfp == NULL) exit(2);
|
||||
dbits = 32;
|
||||
if (argc > 3) {
|
||||
dbits = atoi(argv[3]);
|
||||
}
|
||||
if (dbits != 32 && dbits != 64 && dbits != 128) exit(3);
|
||||
if (dbits == 64) suffix="64"; else if (dbits == 128) suffix="128";
|
||||
if (dbits != 32) xgeneric=";\n wideonly: integer := 0";
|
||||
|
||||
tmp = fsize; abits = 0;
|
||||
while (tmp) {tmp >>= 1; abits++;}
|
||||
tmp = (dbits >> 4); alow = 0;
|
||||
while (tmp) {tmp >>= 1; alow++; }
|
||||
printf("Creating %s : file size: %d bytes, address bits %d, data width %d\n", argv[2], fsize, abits, dbits);
|
||||
fprintf(wfp, "\n\
|
||||
----------------------------------------------------------------------------\n\
|
||||
-- This file is a part of the GRLIB VHDL IP LIBRARY\n\
|
||||
-- Copyright (C) 2010 Aeroflex Gaisler\n\
|
||||
----------------------------------------------------------------------------\n\
|
||||
-- Entity: ahbrom%s\n\
|
||||
-- File: ahbrom%s.vhd\n\
|
||||
-- Author: Jiri Gaisler - Gaisler Research\n\
|
||||
-- Modified Alen Bardizbanyan - Cobham Gaisler (pipelined impl.)\n\
|
||||
-- Description: AHB rom. 0/1-waitstate read\n\
|
||||
----------------------------------------------------------------------------\n\
|
||||
library ieee;\n\
|
||||
use ieee.std_logic_1164.all;\n\
|
||||
library grlib;\n\
|
||||
use grlib.amba.all;\n\
|
||||
use grlib.stdlib.all;\n\
|
||||
use grlib.devices.all;\n\
|
||||
use grlib.config_types.all;\n\
|
||||
use grlib.config.all;\n\
|
||||
\n\
|
||||
entity ahbrom%s is\n\
|
||||
generic (\n\
|
||||
hindex : integer := 0;\n\
|
||||
haddr : integer := 0;\n\
|
||||
hmask : integer := 16#fff#;\n\
|
||||
pipe : integer := 0;\n\
|
||||
tech : integer := 0;\n\
|
||||
kbytes : integer := 1%s);\n\
|
||||
port (\n\
|
||||
rst : in std_ulogic;\n\
|
||||
clk : in std_ulogic;\n\
|
||||
ahbsi : in ahb_slv_in_type;\n\
|
||||
ahbso : out ahb_slv_out_type\n\
|
||||
);\n\
|
||||
end;\n\
|
||||
\n\
|
||||
architecture rtl of ahbrom%s is\n\
|
||||
constant abits : integer := %d;\n\
|
||||
constant bytes : integer := %d;\n\
|
||||
constant dbits : integer := %d;\n\
|
||||
\n\
|
||||
constant hconfig : ahb_config_type := (\n\
|
||||
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),\n\
|
||||
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);\n\
|
||||
\n\
|
||||
signal romdata : std_logic_vector(dbits-1 downto 0);\n\
|
||||
signal romdatas : std_logic_vector(AHBDW-1 downto 0);\n\
|
||||
signal addr : std_logic_vector(abits-1 downto 2);\n\
|
||||
signal hsize : std_logic_vector(2 downto 0);\n\
|
||||
signal romaddr : std_logic_vector(abits-1 downto log2(dbits/8));\n\
|
||||
signal hready, active : std_ulogic;\n\
|
||||
\n\
|
||||
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;\n\
|
||||
\n\
|
||||
begin\n\
|
||||
\n\
|
||||
ahbso.hresp <= \"00\";\n\
|
||||
ahbso.hsplit <= (others => '0');\n\
|
||||
ahbso.hirq <= (others => '0');\n\
|
||||
ahbso.hconfig <= hconfig;\n\
|
||||
ahbso.hindex <= hindex;\n\
|
||||
\n\
|
||||
reg : process (clk)\n\
|
||||
begin\n\
|
||||
if rising_edge(clk) then\n\
|
||||
addr <= ahbsi.haddr(abits-1 downto 2);\n\
|
||||
hsize <= ahbsi.hsize;\n\
|
||||
if RESET_ALL and rst='0' then addr <= (others => '0'); hsize <= \"000\"; end if;\n\
|
||||
end if;\n\
|
||||
end process;\n\
|
||||
\n\
|
||||
p0 : if pipe = 0 generate\n\
|
||||
ahbso.hrdata <= romdatas;\n\
|
||||
ahbso.hready <= '1';\n\
|
||||
hready <= '0';\n\
|
||||
end generate;\n\
|
||||
\n\
|
||||
active <= ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready;\n\
|
||||
p1 : if pipe = 1 generate\n\
|
||||
ahbso.hready <= hready;\n\
|
||||
reg2 : process (clk)\n\
|
||||
begin\n\
|
||||
if rising_edge(clk) then\n\
|
||||
hready <= (not rst) or (not active) or (not(hready));\n\
|
||||
ahbso.hrdata <= romdatas;\n\
|
||||
if RESET_ALL and rst='0' then hready <= '1'; ahbso.hrdata <= (others => '0'); end if;\n\
|
||||
end if;\n\
|
||||
end process;\n\
|
||||
end generate;\n\
|
||||
\n\
|
||||
romaddr <= addr(abits-1 downto log2(dbits/8));\n\
|
||||
", suffix, suffix, suffix, xgeneric, suffix, abits, fsize, dbits);
|
||||
if (dbits < 64) {
|
||||
fprintf(wfp, " romdatas <= ahbdrivedata(romdata);\n");
|
||||
} else {
|
||||
fprintf(wfp, "\
|
||||
romdatas <= ahbdrivedata(romdata) when wideonly/=0 or CORE_ACDM=1 else \n\
|
||||
ahbselectdata(ahbdrivedata(romdata),addr(4 downto 2),hsize);\n\
|
||||
");
|
||||
}
|
||||
fprintf(wfp, "\n\
|
||||
comb : process (romaddr)\n\
|
||||
begin\n\
|
||||
case conv_integer(romaddr) is\n\
|
||||
");
|
||||
i = 0;
|
||||
while (!feof(fp)) {
|
||||
memset(x,0,dbits/8);
|
||||
fread(x, 1, dbits/8, fp);
|
||||
fprintf(wfp, " when 16#%05X# => romdata <= X\"", i++);
|
||||
for (j=0; j<dbits/8; j++)
|
||||
fprintf(wfp, "%02x",x[j]);
|
||||
fprintf(wfp,"\";\n");
|
||||
}
|
||||
fprintf(wfp, "\
|
||||
when others => romdata <= (others => '-');\n\
|
||||
end case;\n\
|
||||
end process;\n\
|
||||
-- pragma translate_off\n\
|
||||
bootmsg : report_version\n\
|
||||
generic map (\"ahbrom%s%s\" & tost(hindex) &\n\
|
||||
\": %d-bit AHB ROM Module, \" & tost(bytes/(dbits/8)) & \" words, \" & tost(abits-log2(dbits/8)) & \" address bits\" );\n\
|
||||
-- pragma translate_on\n\
|
||||
end;\n\
|
||||
",suffix,(dbits>32)?"_":"",dbits);
|
||||
|
||||
fclose (wfp);
|
||||
fclose (fp);
|
||||
return(0);
|
||||
exit(0);
|
||||
}
|
||||
39
bin/aldec/riviera_ws_map_xilinx_libs.do
Normal file
39
bin/aldec/riviera_ws_map_xilinx_libs.do
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
workspace.open riviera_ws/riviera_ws.rwsp
|
||||
workspace.design.setactive techmap
|
||||
amap secureip_ver ../xilinx_lib/secureip
|
||||
amap secureip ../xilinx_lib/secureip
|
||||
amap axi_bfm ../xilinx_lib/secureip
|
||||
amap unisims_ver ../xilinx_lib/unisims_ver
|
||||
amap unisim ../xilinx_lib/unisim
|
||||
amap unimacro_ver ../xilinx_lib/unimacro_ver
|
||||
amap unimacro ../xilinx_lib/unimacro
|
||||
amap simprim_ver ../xilinx_lib/simprims_ver
|
||||
amap simprim ../xilinx_lib/simprims
|
||||
amap unifast_ver ../xilinx_lib/unifast_ver
|
||||
amap unifast ../xilinx_lib/unifast_ver
|
||||
# Do the map for gaisler lib as well since mig is compiled into it
|
||||
workspace.design.setactive gaisler
|
||||
amap secureip_ver ../xilinx_lib/secureip
|
||||
amap secureip ../xilinx_lib/secureip
|
||||
amap axi_bfm ../xilinx_lib/secureip
|
||||
amap unisims_ver ../xilinx_lib/unisims_ver
|
||||
amap unisim ../xilinx_lib/unisim
|
||||
amap unimacro_ver ../xilinx_lib/unimacro_ver
|
||||
amap unimacro ../xilinx_lib/unimacro
|
||||
amap simprim_ver ../xilinx_lib/simprims_ver
|
||||
amap simprim ../xilinx_lib/simprims
|
||||
amap unifast_ver ../xilinx_lib/unifast_ver
|
||||
amap unifast ../xilinx_lib/unifast_ver
|
||||
workspace.design.setactive work
|
||||
amap secureip_ver ../xilinx_lib/secureip
|
||||
amap secureip ../xilinx_lib/secureip
|
||||
amap axi_bfm ../xilinx_lib/secureip
|
||||
amap unisims_ver ../xilinx_lib/unisims_ver
|
||||
amap unisim ../xilinx_lib/unisim
|
||||
amap unimacro_ver ../xilinx_lib/unimacro_ver
|
||||
amap unimacro ../xilinx_lib/unimacro
|
||||
amap simprim_ver ../xilinx_lib/simprims_ver
|
||||
amap simprim ../xilinx_lib/simprims
|
||||
amap unifast_ver ../xilinx_lib/unifast_ver
|
||||
amap unifast ../xilinx_lib/unifast_ver
|
||||
quit
|
||||
77
bin/altera/altera_mf.vhd
Normal file
77
bin/altera/altera_mf.vhd
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
-- Dummy sld_virtual_jtag - ModelSim crashes on default one
|
||||
|
||||
entity sld_virtual_jtag is
|
||||
|
||||
generic (
|
||||
lpm_type : string := "SLD_VIRTUAL_JTAG";
|
||||
-- required by coding standard
|
||||
lpm_hint : string := "SLD_VIRTUAL_JTAG"; -- required by coding standard
|
||||
sld_auto_instance_index : string := "NO";
|
||||
-- Yes of auto index is desired and no otherwise
|
||||
sld_instance_index : integer := 0;
|
||||
-- Index to be used if SLD_AUTO_INSTANCE_INDEX is no
|
||||
sld_ir_width : integer := 1;
|
||||
-- the width of the IR register
|
||||
sld_sim_n_scan : integer := 0;
|
||||
-- the number of scans in the simulation model
|
||||
sld_sim_total_length : integer := 0;
|
||||
-- the total bit width of all DR scan values
|
||||
sld_sim_action : string := "");
|
||||
-- the actions to be simulated in a format specified by the documentation
|
||||
port (
|
||||
tdo : in std_logic := '0'; -- tdo signal into megafunction
|
||||
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
|
||||
-- parallel ir data into megafunction
|
||||
tck : out std_logic; -- tck signal from megafunction
|
||||
tdi : out std_logic; -- tdi signal from megafunction
|
||||
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
|
||||
-- paraller ir data from megafunction
|
||||
virtual_state_cdr : out std_logic; -- cdr state signal of megafunction
|
||||
virtual_state_sdr : out std_logic; -- sdr state signal of megafunction
|
||||
virtual_state_e1dr : out std_logic;
|
||||
-- e1dr state signal of megafunction
|
||||
virtual_state_pdr : out std_logic; -- pdr state signal of megafunction
|
||||
virtual_state_e2dr : out std_logic;
|
||||
-- e2dr state signal of megafunction
|
||||
virtual_state_udr : out std_logic; -- udr state signal of megafunction
|
||||
virtual_state_cir : out std_logic; -- cir state signal of megafunction
|
||||
virtual_state_uir : out std_logic; -- uir state signal of megafunction
|
||||
jtag_state_tlr : out std_logic; -- Test, Logic, Reset state
|
||||
jtag_state_rti : out std_logic; -- Run, Test, Idle state
|
||||
jtag_state_sdrs : out std_logic; -- Select DR scan state
|
||||
jtag_state_cdr : out std_logic; -- capture DR state
|
||||
jtag_state_sdr : out std_logic; -- Shift DR state
|
||||
jtag_state_e1dr : out std_logic; -- exit 1 dr state
|
||||
jtag_state_pdr : out std_logic; -- pause dr state
|
||||
jtag_state_e2dr : out std_logic; -- exit 2 dr state
|
||||
jtag_state_udr : out std_logic; -- update dr state
|
||||
jtag_state_sirs : out std_logic; -- Select IR scan state
|
||||
jtag_state_cir : out std_logic; -- capture IR state
|
||||
jtag_state_sir : out std_logic; -- shift IR state
|
||||
jtag_state_e1ir : out std_logic; -- exit 1 IR state
|
||||
jtag_state_pir : out std_logic; -- pause IR state
|
||||
jtag_state_e2ir : out std_logic; -- exit 2 IR state
|
||||
jtag_state_uir : out std_logic; -- update IR state
|
||||
tms : out std_logic); -- tms signal
|
||||
end sld_virtual_jtag;
|
||||
|
||||
architecture structural of sld_virtual_jtag is
|
||||
|
||||
|
||||
begin -- structural
|
||||
|
||||
-- dummy drivers to avoid modelsim warnings
|
||||
|
||||
tck <= '0';
|
||||
tdi <= '0';
|
||||
ir_in <= (others => '0');
|
||||
virtual_state_cdr <= '0';
|
||||
virtual_state_sdr <= '0';
|
||||
virtual_state_udr <= '0';
|
||||
|
||||
end structural;
|
||||
|
||||
1
bin/atc_run_multi.tcl
Executable file
1
bin/atc_run_multi.tcl
Executable file
|
|
@ -0,0 +1 @@
|
|||
acttclsh /usr/local/actel/libero73/Libero/scripts/extended_run_shell.tcl -adb leon3mp.adb -effort_level 5 -timing_driven -n 20 -save_all
|
||||
1
bin/cds.lib
Normal file
1
bin/cds.lib
Normal file
|
|
@ -0,0 +1 @@
|
|||
include $CDS_INST_DIR/tools/inca/files/cds.lib
|
||||
2
bin/def.npl
Normal file
2
bin/def.npl
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
DEVSIMULATOR Modelsim
|
||||
DEVGENERATEDSIMULATIONMODEL VHDL
|
||||
1
bin/echo.bat
Executable file
1
bin/echo.bat
Executable file
|
|
@ -0,0 +1 @@
|
|||
echo "$@"
|
||||
31
bin/editise.txt
Normal file
31
bin/editise.txt
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
How to read and/or edit the new ".ise" Project Navigator project file
|
||||
---------------------------------------------------------------------
|
||||
|
||||
In the "%Xilinx%\data\projnav" directory there is a script file named "iseEdit.tcl." This script was created to import and export ISE file content.
|
||||
|
||||
Usage:
|
||||
xtclsh iseEdit.tcl [export|import] [client=<client_name>] [datafile=<datafile_name>] [<projectname.ise>]
|
||||
|
||||
Valid options are:
|
||||
help : Displays this help message
|
||||
export : Exports contents of the client registry section to a datafile
|
||||
import : Imports contents from a data file to the client registry section
|
||||
(Note: Either the -export or -import option must be specified, but not both)
|
||||
|
||||
client=<clientname> : Optionally specify the client to use. If not specified,
|
||||
'ProjectNavigator' is used as the default client
|
||||
|
||||
datafile=<datafile_name> : Optionally specify the data file to use for export or import
|
||||
|
||||
<projectname.ise> : ISE Project file name to use for export only. This must be
|
||||
specified for export but should not be specified for import
|
||||
|
||||
Examples:
|
||||
xtclsh iseEdit.tcl export watchvhd.ise
|
||||
xtclsh iseEdit.tcl import
|
||||
|
||||
xtclsh iseEdit.tcl export datafile=pndata.txt watchvhd.ise
|
||||
xtclsh iseEdit.tcl export client=ProjectNavigator datafile=pndata.txt watchvhd.ise
|
||||
xtclsh iseEdit.tcl import datafile=pndata.txt
|
||||
|
||||
xtclsh iseEdit.tcl import client=ProjectNavigator datafile=pndata.txt
|
||||
146
bin/ex_cmds.tcl
Normal file
146
bin/ex_cmds.tcl
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
|
||||
###############################################################
|
||||
#
|
||||
# eX command script, (C) 2007 eASIC Corp.
|
||||
# Automatically generated by CDB
|
||||
#
|
||||
# $Id: etools_fe.pm,v 1.17 2008/04/04 13:37:18 richard Exp $
|
||||
###############################################################
|
||||
|
||||
set my_home $env(EX_HOME)
|
||||
source ../../../env.tcl
|
||||
source $my_home/scripts/genDesignDataFile.tcl
|
||||
source $my_home/scripts/genLibMap.tcl
|
||||
|
||||
logging attach console
|
||||
logging attach file ex.log
|
||||
logging level set drc.rtlentry.eclkgateimpl INFO
|
||||
logging setmsgcount --logname=udesign.tclscript --maxcount=5000
|
||||
logging setmsgcount --logname=drc.all.gendd.warn --maxcount=5000
|
||||
logging setmsgcount --logname=drc.all.portpropagation --maxcount=5000
|
||||
logging setmsgcount --logname=drc.all.undrivennet --maxcount=5000
|
||||
|
||||
puts "############### Starting project file add ###############"
|
||||
project new ${design}
|
||||
if [info exists verilogList] {
|
||||
project hdloptions -verilog -v $my_home/data/dw_comp.v
|
||||
foreach f $verilogList { eval project file add -rtl_verilog $f }
|
||||
}
|
||||
if [info exists vhdlList] {
|
||||
# HMS - modification to simplify the usage of VHDL libraries
|
||||
file delete -force work
|
||||
file mkdir work
|
||||
foreach f $vhdlList {
|
||||
set libspace [string first " " $f]
|
||||
if {$libspace == -1} {
|
||||
eval project file add $f
|
||||
} else {
|
||||
set lib [string range $f 0 [expr $libspace - 1]]
|
||||
file delete -force $lib
|
||||
file mkdir $lib
|
||||
eval project file add -libmap $f
|
||||
}
|
||||
}
|
||||
|
||||
#automatically handle VHDL packages
|
||||
# set revised {}
|
||||
# ::easic::ex_libmap $vhdlList revised
|
||||
# set num [llength $revised]
|
||||
# set cnt [expr $num - 1]
|
||||
# for {set i 0} {$i < $cnt} {incr i} {
|
||||
# set libfs [lindex $revised $i]
|
||||
# set lib [lindex $libfs 0]
|
||||
# set fs [lindex $libfs 1]
|
||||
# file delete -force $lib
|
||||
# file mkdir $lib
|
||||
# eval project file add -libmap $lib $fs
|
||||
# }
|
||||
# set nonlibfs [lindex $revised $cnt]
|
||||
# foreach f $nonlibfs { eval project file add -rtl_vhdl $f }
|
||||
}
|
||||
|
||||
# eASIC Library
|
||||
if {[file exists $env(ETOOLS_HOME)/ip_lib]} {
|
||||
foreach lib [glob -nocomplain $env(ETOOLS_HOME)/ip_lib/*] {
|
||||
if {[file isdirectory $lib]} {
|
||||
foreach macro [glob -nocomplain $lib/*] {
|
||||
#add macro design files
|
||||
if {[file exists $macro/src/rtl/verilog]} {
|
||||
eval project hdloptions -verilog -y $macro/src/rtl/verilog +libext+.v+
|
||||
}
|
||||
if {[file exists $macro/src/rtl/vhdl]} {
|
||||
#VHDL not supported yet, so this really is a placeholder
|
||||
# HMS - removed since it caused errors
|
||||
# eval project hdloptions -vhdl -y $macro/src/rtl/vhdl
|
||||
}
|
||||
} ;#next macro
|
||||
}
|
||||
} ;#next lib
|
||||
}
|
||||
|
||||
# Include files
|
||||
if [info exists defineList] {
|
||||
foreach def $defineList { eval project hdloptions -verilog +define+${def}+ }
|
||||
}
|
||||
if [info exists includeList] {
|
||||
foreach inc $includeList { eval project hdloptions -verilog +incdir+${inc}+ }
|
||||
}
|
||||
|
||||
if {$top_hdl == "vhdl"} {
|
||||
# attempt to sort VHDL files in the right order
|
||||
# caution: this is not guaranteed to always work
|
||||
project hdloptions -$top_hdl -sort
|
||||
}
|
||||
|
||||
puts "############### Starting prepare syn ###############"
|
||||
project nomdata flat
|
||||
prepare syn -disable_memory_detect -top $design
|
||||
puts "############### Finished prepare syn ###############\n"
|
||||
|
||||
puts "############### Starting export ewizard ###############"
|
||||
set top [lindex [nomdata proplist FLAT_TOPNAME] 0]
|
||||
set filename ../../out/${design}.dd
|
||||
set fileId [open $filename "w"]
|
||||
generateInterFile $top $fileId
|
||||
#close $fileId
|
||||
puts "############### Finished export ewizard ###############\n"
|
||||
|
||||
puts "############### Starting report netlist ###############"
|
||||
report netlist -file ../rpt/ex_premap_netlist.rpt
|
||||
puts "############### Finished report netlist ###############\n"
|
||||
|
||||
puts "############### Starting export verilog ###############"
|
||||
export verilog ../../out/ex_${design}.v
|
||||
puts "############### Finished export verilog ###############\n"
|
||||
|
||||
puts "############### Starting report clock ###############"
|
||||
report clock --format=xml --file=../rpt/ex_clock.xml
|
||||
puts "############### Finished report clock ###############\n"
|
||||
|
||||
puts "############### Starting report memory ###############"
|
||||
#report memory --format=xml -file ../rpt/ex_memory.xml
|
||||
#report memory -file ../rpt/ex_memory.rpt
|
||||
puts "############### Finished report memory ###############\n"
|
||||
|
||||
puts "############### Starting report netlist ###############"
|
||||
report netlist -file ../rpt/ex_netlist.rpt
|
||||
puts "############### Finished report netlist ###############\n"
|
||||
|
||||
puts "############### Starting checks ###############"
|
||||
logging attach file --format=xml ../rpt/ex_log.xml
|
||||
check
|
||||
logging detach file ../rpt/ex_log.xml
|
||||
puts "############### Finished checks ###############\n"
|
||||
|
||||
#puts "############### Starting eSyn ###############"
|
||||
#esyn map
|
||||
#report netlist -file ../rpt/ex_map_netlist.rpt
|
||||
#puts "############### Finished eSyn ###############\n"
|
||||
|
||||
puts "
|
||||
===========================
|
||||
eX finished
|
||||
===========================
|
||||
"
|
||||
|
||||
exit
|
||||
19
bin/gpl.sed
Normal file
19
bin/gpl.sed
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
s/--GAISLER_LICENSE/------------------------------------------------------------------------------\
|
||||
-- This file is a part of the GRLIB VHDL IP LIBRARY\
|
||||
-- Copyright (C) 2003 - 2008, Gaisler Research\
|
||||
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler\
|
||||
-- Copyright (C) 2015 - 2017, Cobham Gaisler\
|
||||
--\
|
||||
-- This program is free software\; you can redistribute it and\/or modify\
|
||||
-- it under the terms of the GNU General Public License as published by\
|
||||
-- the Free Software Foundation;\ either version 2 of the License, or\
|
||||
-- (at your option) any later version.\
|
||||
--\
|
||||
-- This program is distributed in the hope that it will be useful,\
|
||||
-- but WITHOUT ANY WARRANTY;\ without even the implied warranty of\
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\
|
||||
-- GNU General Public License for more details.\
|
||||
--\
|
||||
-- You should have received a copy of the GNU General Public License\
|
||||
-- along with this program;\ if not, write to the Free Software\
|
||||
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\ /
|
||||
8
bin/gr.sed
Normal file
8
bin/gr.sed
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
s/--GAISLER_LICENSE/------------------------------------------------------------------------------\
|
||||
-- This file is a part of the GRLIB VHDL IP LIBRARY\
|
||||
-- Copyright (C) 2017, Cobham Gaisler AB - all rights reserved.\
|
||||
--\
|
||||
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN \
|
||||
-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED \
|
||||
-- IN ADVANCE IN WRITING.\ /
|
||||
|
||||
15
bin/head.xise
Normal file
15
bin/head.xise
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by GRLIB script generator -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
|
||||
|
||||
0
bin/libs.txt
Normal file
0
bin/libs.txt
Normal file
215
bin/modelsim.ini
Normal file
215
bin/modelsim.ini
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
std = $MODEL_TECH/../std
|
||||
ieee = $MODEL_TECH/../ieee
|
||||
vital2000 = $MODEL_TECH/../vital2000
|
||||
verilog = $MODEL_TECH/../verilog
|
||||
arithmetic = $MODEL_TECH/../arithmetic
|
||||
mgc_portable = $MODEL_TECH/../mgc_portable
|
||||
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||
synopsys = $MODEL_TECH/../synopsys
|
||||
|
||||
[vcom]
|
||||
; Turn on VHDL-1993 as the default. Normally is off.
|
||||
VHDL93 = 1
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = false
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units. Default is to include.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units. Default is to include.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
[vsim]
|
||||
|
||||
; vopt flow
|
||||
; Set to turn on automatic optimization of a design.
|
||||
; Default is off (pre-6.0 flow without vopt).
|
||||
VoptFlow = 0
|
||||
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = 1ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
UserTimeUnit = ns
|
||||
|
||||
; Default run length
|
||||
RunLength = 100
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after an assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
||||
; for Verilog, PathSeparator = .
|
||||
PathSeparator = /
|
||||
|
||||
; Disable assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, or deposit
|
||||
; or in other terms, fixed, wired or charged.
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated
|
||||
; else open files on first read or write
|
||||
; DelayFileOpen = 0
|
||||
|
||||
; Control VHDL files opened for write
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Specify whether WLF file logging can use threads on multi-processor machines
|
||||
; if 0, no threads will be used, if 1, threads will be used if the system has
|
||||
; more than one processor
|
||||
WLFUseThreads = 1
|
||||
|
||||
; This controls the number of characters of a signal name
|
||||
; shown in the waveform window and the postscript plot.
|
||||
; The default value or a value of zero tells VSIM to display
|
||||
; the full name.
|
||||
; WaveSignalNameWidth = 10
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit
|
||||
; packages.
|
||||
NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of a generate statement label. Don't quote it.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is to be compressed.
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
[lmc]
|
||||
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
|
||||
libsm = $MODEL_TECH/libsm.sl
|
||||
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libsm = $MODEL_TECH/libsm.dll
|
||||
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
||||
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
||||
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
||||
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
||||
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
||||
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
||||
; Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
|
||||
; do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
|
||||
; and run "vsim.swift".
|
||||
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
||||
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
||||
|
||||
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
|
||||
libhm = $MODEL_TECH/libhm.sl
|
||||
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
||||
; libhm = $MODEL_TECH/libhm.dll
|
||||
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
||||
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
|
||||
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
||||
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
|
||||
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
||||
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
|
||||
; Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
|
||||
; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
|
||||
; Logic Modeling's hardware modeler SFI software (Window NT)
|
||||
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
|
||||
14
bin/mt1.mpf
Normal file
14
bin/mt1.mpf
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
VHDL_DoubleClick = Edit
|
||||
VERILOG_DoubleClick = Edit
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
TCL_DoubleClick = Edit
|
||||
TEXT_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_CustomDoubleClick =
|
||||
TEXT_CustomDoubleClick =
|
||||
ForceSoftPaths = 0
|
||||
77
bin/padsrec.tcl
Executable file
77
bin/padsrec.tcl
Executable file
|
|
@ -0,0 +1,77 @@
|
|||
#! /usr/bin/tclsh
|
||||
#
|
||||
# Utility to pad SREC to multiple of 16 bytes
|
||||
# Copyright 2010, Aeroflex Gaisler AB.
|
||||
#
|
||||
# Usage: tclsh padsrec.tcl <in.srec >out.srec
|
||||
#
|
||||
# Limitations:
|
||||
# - Each line except the last of the SREC must contain a multiple of 8 bytes of data
|
||||
# - Records other than S1-3 are passed on unchanged
|
||||
# - SREC checksums are not correct
|
||||
#
|
||||
# Revision history:
|
||||
# 2011-08-12, MH, First version (based on ftddrcb.tcl)
|
||||
#
|
||||
|
||||
|
||||
|
||||
# -------------------------------------------------------------
|
||||
# SREC processing
|
||||
|
||||
set valtable { 0 1 2 3 4 5 6 7 8 9 A B C D E F }
|
||||
for { set i 0 } { $i < 16 } { incr i } {
|
||||
set symval([lindex $valtable $i]) $i
|
||||
}
|
||||
|
||||
proc hex2int { h } {
|
||||
global symval
|
||||
set l [string length $h]
|
||||
set r 0
|
||||
for {set i 0} {$i < $l} {incr i} {
|
||||
set r [expr {($r << 4) + $symval([string index $h $i])}]
|
||||
}
|
||||
return $r;
|
||||
}
|
||||
|
||||
proc int2hex { i l } {
|
||||
global valtable
|
||||
set r ""
|
||||
set ol 0
|
||||
while { $i > 0 || $ol < $l || $ol < 1 } {
|
||||
set r [ format "%s%s" [lindex $valtable [ expr { $i & 15 } ] ] $r ]
|
||||
set i [ expr { $i >> 4 } ]
|
||||
incr ol
|
||||
}
|
||||
return $r
|
||||
}
|
||||
|
||||
set lineno 0
|
||||
while { ! [eof stdin] } {
|
||||
set l [gets stdin]
|
||||
incr lineno
|
||||
set llen [string length $l]
|
||||
if { $llen == 0 } then continue
|
||||
set rt [string index $l 1 ]
|
||||
if { $rt > 0 && $rt < 4 } then {
|
||||
# Byte count and data position
|
||||
set bc [expr { [hex2int [string range $l 2 3]] - 2 - $rt } ]
|
||||
set dp [expr {6 + $rt*2}]
|
||||
|
||||
if { [expr {$bc & 7}] != 0 } then {
|
||||
# puts stderr "Warning: Padding line $lineno to even multiple of 8 bytes"
|
||||
while { [expr {$bc & 7}] != 0 } {
|
||||
set l0 [ string range $l 4 [expr {$llen-3}] ]
|
||||
set l1 [ string range $l [expr {$llen-2}] $llen ]
|
||||
incr bc
|
||||
set l [format "S%s%s%s%s%s" $rt [int2hex [expr {$bc+2+$rt}] 2] $l0 "00" $l1]
|
||||
incr llen
|
||||
incr llen
|
||||
}
|
||||
# puts stderr "Became: $l"
|
||||
}
|
||||
}
|
||||
puts $l
|
||||
}
|
||||
|
||||
|
||||
7
bin/quartus.qpf
Executable file
7
bin/quartus.qpf
Executable file
|
|
@ -0,0 +1,7 @@
|
|||
#QUARTUS_VERSION = "4.1"
|
||||
#DATE = "17:39:37 December 03, 2004"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
|
||||
9
bin/quartus.qsf_head
Executable file
9
bin/quartus.qsf_head
Executable file
|
|
@ -0,0 +1,9 @@
|
|||
# Project-Wide Assignments
|
||||
# ========================
|
||||
#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
|
||||
#set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:13:08 DECEMBER 01, 2004"
|
||||
|
||||
# Explicitly disable TimeQuest since the GRLIB flow invokes the classical
|
||||
# timing analyzer and USE_TIMEQUEST_TIMING_ANALYZER defaults to "ON"
|
||||
# set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER "OFF"
|
||||
|
||||
15
bin/route
Executable file
15
bin/route
Executable file
|
|
@ -0,0 +1,15 @@
|
|||
#!/bin/sh
|
||||
# route entity ucf-file device effort bitgen-file path map-options
|
||||
rm $1.ngd $1.ncd
|
||||
echo edif2ngd $6/$1.edf
|
||||
edif2ngd $6/$1.edf
|
||||
echo ngdbuild $1.ngo -aul -uc $2 -p $3 -sd $7
|
||||
ngdbuild $1.ngo -aul -uc $2 -p $3 -sd $7
|
||||
echo map -pr b -ol $4 -p $3 $1 $8
|
||||
map -pr b -ol $4 -p $3 $1 $8
|
||||
echo par -ol $4 -w $1 $1.ncd
|
||||
par -ol $4 -w $1 $1.ncd
|
||||
echo trce -v 25 $1.ncd $1.pcf
|
||||
trce -v 25 $1.ncd $1.pcf
|
||||
echo bitgen $1 -d -m -w -f $5
|
||||
bitgen $1 -d -m -w -f $5
|
||||
19
bin/route_lattice
Executable file
19
bin/route_lattice
Executable file
|
|
@ -0,0 +1,19 @@
|
|||
#!/bin/sh
|
||||
# route entity ucf-file device path isplib package
|
||||
echo edif2ngd -l $5 -d $3 $4/$1.edf
|
||||
edif2ngd -l $5 -d $3 $4/$1.edf
|
||||
echo ngdbuild -a $5 -d $3 $1.ngo $1.ngd
|
||||
ngdbuild -a $5 -d $3 $1.ngo $1.ngd
|
||||
echo map -a $5 -p $3 -t $6 -s 5 $1.ngd -o $1.ncd
|
||||
map -a $5 -p $3 -t $6 -s 5 $1.ngd -o $1.ncd
|
||||
#par -cs 1 -w $1 $1.ncd $2
|
||||
#par -e 1 -i 10 -w $1 $1.ncd $2
|
||||
echo par -cs 1 -e 1 -i 10 -w $1 $1.ncd
|
||||
par -cs 1 -e 1 -i 10 -w $1 $1.ncd
|
||||
#trce -v 1 $1.ncd $2
|
||||
echo trce -v 1 $1.ncd
|
||||
trce -v 1 $1.ncd
|
||||
#bitgen -f $7 -w $1.ncd $2
|
||||
echo bitgen -f $7 -w $1.ncd
|
||||
bitgen -f $7 -w $1.ncd
|
||||
#synsvf -exe $ISPVM_DIR/ispufw -prj $1 -op p -if $1.bit -oft -int -of $1.mcs
|
||||
15
bin/route_ngc
Executable file
15
bin/route_ngc
Executable file
|
|
@ -0,0 +1,15 @@
|
|||
#!/bin/sh
|
||||
# route entity ucf-file device effort bitgen path map-options
|
||||
#ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6
|
||||
rm $1.ngd
|
||||
echo ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6
|
||||
ngdbuild $1.ngc -aul -uc $2 -p $3 -sd $6
|
||||
#ngdbuild $1.ngc -aul -uc $2 -p $3
|
||||
echo map -w -pr b -ol $4 -p $3 $1 $7
|
||||
map -w -pr b -ol $4 -p $3 $1 $7
|
||||
echo par -ol $4 -w $1 $1.ncd
|
||||
par -ol $4 -w $1 $1.ncd
|
||||
echo trce -v 25 $1.ncd $1.pcf
|
||||
trce -v 25 $1.ncd $1.pcf
|
||||
echo bitgen $1 -l -m -w -d -f $5
|
||||
bitgen $1 -l -m -w -d -f $5
|
||||
3
bin/runvsim.do
Normal file
3
bin/runvsim.do
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
run -all
|
||||
quit
|
||||
|
||||
139
bin/scriptgen/README.txt
Normal file
139
bin/scriptgen/README.txt
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
Manual for scriptgen
|
||||
|
||||
scriptgenwork
|
||||
If this directory is not present in the directory calling 'make scripts', it
|
||||
will be copied to that directory (this happens in dependencies.tcl). The directory
|
||||
will be coped from scriptgencfg if that directory exists in the template
|
||||
design or otherwise from bin/scriptgen/scripgencfg/. A local copy in the
|
||||
template design can be made to contain files that can be altered by the user.
|
||||
Note that "make distclean" will remove scriptgen/work.
|
||||
|
||||
scriptgenwork/tools.tcl
|
||||
Specifies which tools are going to be used for generating a project. This file
|
||||
is sourced to main.tcl, dependencies.tcl and targets.tcl in order to only
|
||||
generate files specific to the needed tools. The main part of the tcl program is
|
||||
located in $GRLIB/bin/scriptgen.
|
||||
|
||||
scriptgenwork/extrafiles.tcl
|
||||
If files are to be included that are not found through scanning in
|
||||
generatefilelists in database.tcl they may be specified here.
|
||||
|
||||
Guide to adding extra files in scriptgenwork/extrafiles.tcl:
|
||||
Each file and lib added must be added to both the extrafiletree and
|
||||
extrafileinfo dicts. extrafiletree must follow the same structure as filetree
|
||||
does in generatefilelists.
|
||||
|
||||
The structure of filetree is:
|
||||
Filetree is a dict.
|
||||
An entry in the dict has a lib(key) and a dict(value).
|
||||
An entry in the nested dict has a dir(key) and a list(value).
|
||||
The list consists of files which are present within that dir.
|
||||
|
||||
Each lib and file added to the filetree also has to be added to the
|
||||
extrafileinfo dict.
|
||||
|
||||
The structure of fileinfo is:
|
||||
Fileinfo is a dict.
|
||||
An entry in the dict has a lib/file(key) and a dict(value).
|
||||
The nested dict has different entries depending on if it's a lib or a file.
|
||||
|
||||
Entries in the nested dict for a lib are:
|
||||
key : value
|
||||
-------------------------------------
|
||||
bn : lib's basename
|
||||
k_real : real path for that lib
|
||||
|
||||
Entries in the nested dict for a file are:
|
||||
key : value
|
||||
-------------------------------------
|
||||
bn : lib's basename
|
||||
l : parent directory dir
|
||||
i : the type of the file
|
||||
q : the filename
|
||||
|
||||
See scripgencfg-examples/extrafiles for an example of added files.
|
||||
|
||||
scriptgenwork/filebuild
|
||||
If an extra tool has been added, database.tcl will try to source $tool.tcl from
|
||||
this folder in order to create configuration files specific to that tool.
|
||||
A skeleton of a $tool.tcl file called newtool.tcl can be found in
|
||||
$GRLIB/bin/scriptgen/scriptgencfg-examples.
|
||||
|
||||
|
||||
|
||||
|
||||
Documentation of main program always located in $GRLIB/bin/scriptgen:
|
||||
|
||||
|
||||
dependencies.tcl
|
||||
If scriptgencfg is not present in the directory calling 'make scripts'
|
||||
it will be copied from $GRLIB/bin/scriptgen/scriptgencfg to the calling
|
||||
directory. depencencies.tcl then generates a string of files depending on which
|
||||
tools are used to create the correct dependencies in the script: section in
|
||||
$GRLIB/bin/Makefile.
|
||||
|
||||
targets.tcl
|
||||
Generates a string of files depending on which tools are used to create the
|
||||
correct targets in the script: section in $GRLIB/bin/Makefile.
|
||||
|
||||
main.tcl
|
||||
The program which starts the filegeneration. main.tcl sources the user specific
|
||||
files scriptgenwork/extrafiles.tcl and scriptgenwork/tools.tcl and then
|
||||
starts database.tcl.
|
||||
|
||||
database.tcl
|
||||
The procs lsearchmatch, listtrim, listinfile and rmvlinebreak are help methods
|
||||
for commonly used functions.
|
||||
|
||||
parseenv is a proc for parsing the information contained in an environmental
|
||||
variable. When environmental variables are exported from the Makefile to tcl,
|
||||
white space and "|" are changed to “:” in order to export them. parseenv splits
|
||||
the information when “:” is encountered and puts the information back together
|
||||
and returns it.
|
||||
|
||||
librarieslist and generatefilelists are procs used for scanning the filesystem
|
||||
for available libs, dirs and files. librarieslist just creates the upper-most
|
||||
layer of the filesystem. generatefilelists generates through scanning, a dict
|
||||
for the filetree (libs, dirs and files) called filetree, a dict for information
|
||||
regarding each lib/file called fileinfo. Files optionally added in
|
||||
$VHDLSYNFILES $VHDLOPTSYNFILES $VHDLSIMFILES $VERILOGOPTSYNFILES
|
||||
$VERILOGSYNFILES $VERILOGSIMFILES (in the specific designs Makefile) are then
|
||||
added to the filetree/fileinfo dicts. generatefilelists also echoes settings
|
||||
and each lib/dir scanned.
|
||||
|
||||
mergefiletrees and mergefileinfos are procs used for merging the filetree and
|
||||
fileinfo dicts generated in genereatefilelists with the user specified
|
||||
extrafiletree and extrafileinfo in scriptgenwork/extrafiles.
|
||||
|
||||
The main portion of database.tcl sets the environmentals variables needed in
|
||||
the beginning, parses them and sets them as variables. These variables are used
|
||||
in several proc’s in conjunction with the global command in order to fetch the
|
||||
value.
|
||||
|
||||
The program then calls generatefilelists mergefiletrees and mergefileinfos to
|
||||
set the filetree and fileinfo dicts.
|
||||
|
||||
In the last part of the program each tools creation file is sourced, that tcl
|
||||
file is located in $GRLIB/bin/scriptgen/filebuild/$tool.tcl, if a user
|
||||
specified tool is present it will be sourced from scriptgenwork/filebuild.
|
||||
|
||||
filebuild/$tool.tcl
|
||||
The $tool.tcl file has the same basic structure. This works in such a way that
|
||||
a string in a specific buildfile (e.g. ghdl_make.tcl) is available (name is the
|
||||
outputfilename e.g. make_ghdl_contents) and appended by each method called
|
||||
(create, append or eof).
|
||||
|
||||
Basic structure:
|
||||
Sources each of the tools buildfiles
|
||||
Calls the buildfiles create method
|
||||
Scans libs, dirs and files. In libs it calls append_lib proc for some
|
||||
buildfiles, and in files it calls the append_file proc for some buildfiles
|
||||
After the scanning it calls eof proc of most buildfiles.
|
||||
|
||||
Makefile
|
||||
The make scripts section in the Makefile calls dependencies.tcl and targets.tcl
|
||||
in order to correctly set dependencies and targets depending on tools specified
|
||||
in tools.tcl. The makefile then exports parsed environmental variables
|
||||
(whitespace and "|" is changed to ":") and starts main.tcl. The reason
|
||||
environmental variables are exported instead of used as arguments is to easily
|
||||
access them in tcl.
|
||||
327
bin/scriptgen/database.tcl
Normal file
327
bin/scriptgen/database.tcl
Normal file
|
|
@ -0,0 +1,327 @@
|
|||
if { [catch {source scriptgen_variable_values.tcl}] } {
|
||||
puts stderr "File scriptgen_variable_values.tcl hasn't been generated"
|
||||
puts stderr "\n"
|
||||
}
|
||||
|
||||
#Enables wildcards in lsearch
|
||||
proc lsearchmatch {list pattern} {
|
||||
set i 0
|
||||
foreach a $list {
|
||||
if {[string match $a $pattern]} {
|
||||
return $i
|
||||
}
|
||||
incr i
|
||||
}
|
||||
return -1
|
||||
}
|
||||
|
||||
|
||||
#Trims entries in a list
|
||||
proc listtrim {inputlist} {
|
||||
set newlist [list]
|
||||
foreach listentry $inputlist {
|
||||
set newentry [string trim $listentry]
|
||||
if {[expr ![expr [string equal $newentry ""] || [string equal [string index $newentry 0] "#" ] ] ] } {
|
||||
lappend newlist $newentry
|
||||
}
|
||||
}
|
||||
return $newlist
|
||||
}
|
||||
|
||||
#Extracts a list from a file for genereatefilelists
|
||||
proc listinfile {filename} {
|
||||
set infofile [open $filename r]
|
||||
set info [split [read $infofile] "\n" ]
|
||||
set newinfo {}
|
||||
foreach i $info {
|
||||
if { [string first " " $i] > -1 } {
|
||||
set newinfo [concat $newinfo [split $i " "] ]
|
||||
} else {
|
||||
lappend newinfo $i
|
||||
}
|
||||
}
|
||||
set info $newinfo
|
||||
set info [listtrim $info]
|
||||
close $infofile
|
||||
return $info
|
||||
}
|
||||
|
||||
proc rmvlinebreak {information} {
|
||||
if {[string length $information] > 0} {
|
||||
set information [string range $information 0 end-1]
|
||||
}
|
||||
return $information
|
||||
}
|
||||
|
||||
#Generates the top level of the filesystem in which generetefilelists scans
|
||||
proc librarieslist {} {
|
||||
global XTECHLIBS GRLIB LIBADD EXTRALIBS LIBADD
|
||||
set liblist {grlib}
|
||||
set liblist [concat $liblist $XTECHLIBS]
|
||||
set arrayfile [open "$GRLIB/lib/libs.txt" r]
|
||||
set liblist [concat $liblist [split [read $arrayfile] "\n"] ]
|
||||
close $arrayfile
|
||||
foreach lib [glob -nocomplain -type f $GRLIB/lib/*/libs.txt] {
|
||||
set arrayfile [open $lib r]
|
||||
set liblist [concat $liblist [split [read $arrayfile] "\n" ] ]
|
||||
close $arrayfile
|
||||
}
|
||||
set extralib [expr {[string equal [glob -nocomplain "$EXTRALIBS/libs.txt"]\
|
||||
"$EXTRALIBS/libs.txt" ] ? "$EXTRALIBS/libs.txt" : "$GRLIB/bin/libs.txt" }]
|
||||
set arrayfile [open $extralib r]
|
||||
set liblist [concat $liblist [split [read $arrayfile] "\n"] ]
|
||||
close $arrayfile
|
||||
set liblist [concat $liblist $LIBADD]
|
||||
lappend liblist work
|
||||
set liblist [listtrim $liblist]
|
||||
return $liblist
|
||||
}
|
||||
|
||||
#Scans filesystem for available libs dirs and files, then creates a dict for
|
||||
#the filetree and fileinfo, a dict that stores information about each library/file.
|
||||
#Files optionally added by the user, e.g. "VHDLOPTSYNFILES" are added in the
|
||||
#back of the filetree/fileinfo dicts
|
||||
#Also echoes to the user the settings and each library/directory scanned.
|
||||
proc generatefilelists {filetree fileinfo} {
|
||||
global GRLIB EXTRALIBS DIRADD TECHLIBS XLIBSKIP GRLIB_LEON3_VERSION XDIRSKIP\
|
||||
FILEADD XFILESKIP GRLIB_CONFIG VHDLSYNFILES VHDLOPTSYNFILES VHDLSIMFILES\
|
||||
VERILOGSYNFILES VERILOGOPTSYNFILES VERILOGSIMFILES GRLIB_SIMULATOR TOP SIMTOP
|
||||
upvar $filetree ft
|
||||
upvar $fileinfo fi
|
||||
|
||||
puts "GRLIB settings:"
|
||||
puts {\n}
|
||||
puts " GRLIB = $GRLIB"
|
||||
puts {\n}
|
||||
if {[string equal $GRLIB_CONFIG "dummy"]} {
|
||||
puts " GRLIB_CONFIG is library default"
|
||||
} else {
|
||||
puts " GRLIB_CONFIG = $GRLIB_CONFIG"
|
||||
}
|
||||
puts {\n}
|
||||
puts " GRLIB_SIMULATOR = $GRLIB_SIMULATOR"
|
||||
puts {\n}
|
||||
puts " TECHLIBS setting = $TECHLIBS"
|
||||
puts {\n}
|
||||
puts " Top-level design = $TOP"
|
||||
puts {\n}
|
||||
puts " Simulation top-level = $SIMTOP"
|
||||
puts {\n}
|
||||
puts "Scanning libraries:"
|
||||
|
||||
set GRLIB_real [file normalize $GRLIB]
|
||||
set GRLIB_CONFIG_real [file normalize $GRLIB_CONFIG]
|
||||
|
||||
foreach j [librarieslist] {
|
||||
set bn [exec basename $j]
|
||||
set k "$GRLIB/lib/$j"
|
||||
set k_real "$GRLIB_real/lib/$j"
|
||||
set k [expr {[string equal [glob -nocomplain $k] $k ] ? $k : "$EXTRALIBS/$j" } ]
|
||||
set tdirs [expr {[string equal $bn "techmap" ] ? "$TECHLIBS maps" : $DIRADD } ]
|
||||
if {[lsearch $XLIBSKIP $bn] < 0 && [string equal [glob -nocomplain "$k/dirs.txt"] "$k/dirs.txt" ] } {
|
||||
puts {\n}
|
||||
puts " $bn:"
|
||||
set libtree [dict create]
|
||||
foreach l [concat [listinfile $k/dirs.txt] $tdirs] {
|
||||
set l [expr {[expr [string equal $l "leon3" ] && [expr\
|
||||
![string equal $GRLIB_LEON3_VERSION "3"] ] ] ? "leon3pkgv1v2" : $l } ]
|
||||
if {[lsearch $XDIRSKIP $l] < 0 } {
|
||||
set flist {}
|
||||
foreach i {vlogsyn vhdlsyn svlogsyn vhdlmtie vhdlsynpe vhdldce vhdlcdse vhdlxile vhdlprec \
|
||||
vhdlprec vhdlfpro vhdlp1735 vlogsim vhdlsim svlogsim } {
|
||||
set m $k/$l/$i
|
||||
if {[string equal [glob -nocomplain "$m.txt" ] "$m.txt" ] && ![string equal $m ""] } {
|
||||
foreach q [concat [listinfile $m.txt] $FILEADD ] {
|
||||
set f $k/$l/$q
|
||||
set fx $l/$q
|
||||
set f_real $k_real/$l/$q
|
||||
if { [string equal $bn "grlib"] && [string equal $l "stdlib"] && \
|
||||
[string equal $q "config.vhd"] && ![string equal $GRLIB_CONFIG "dummy"] } {
|
||||
set f $GRLIB_CONFIG
|
||||
set f_real $GRLIB_CONFIG_real
|
||||
set grcfg $f
|
||||
}
|
||||
if {[lsearch $XFILESKIP $q ] < 0 && [string equal [glob -nocomplain $f] $f ] \
|
||||
&& ![string equal $f ""] } {
|
||||
set conffiledict [dict create bn $bn f_real $f_real q $q l $l i $i k $k]
|
||||
lappend flist $f
|
||||
dict set fi $f $conffiledict
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {[string equal [glob -nocomplain "$k/$l" ] "$k/$l" ] } {
|
||||
puts "$l"
|
||||
dict set libtree $l $flist
|
||||
}
|
||||
}
|
||||
}
|
||||
set libdict [dict create k_real $k_real bn $bn]
|
||||
dict set ft $k $libtree
|
||||
dict set fi $k $libdict
|
||||
}
|
||||
}
|
||||
|
||||
puts {\n}
|
||||
|
||||
set flist {}
|
||||
foreach f [concat $VHDLOPTSYNFILES $VHDLSYNFILES] {
|
||||
if {[file exists $f] } {
|
||||
lappend flist $f
|
||||
set conffiledict [dict create bn "work" l "local" i "vhdlsyn" q $f]
|
||||
dict set fi $f $conffiledict
|
||||
}
|
||||
}
|
||||
|
||||
foreach f $VHDLSIMFILES {
|
||||
if {[file exists $f] } {
|
||||
lappend flist $f
|
||||
set conffiledict [dict create bn "work" l "local" i "vhdlsim" q $f]
|
||||
dict set fi $f $conffiledict
|
||||
}
|
||||
}
|
||||
|
||||
foreach f [concat $VERILOGOPTSYNFILES $VERILOGSYNFILES] {
|
||||
if {[file exists $f] } {
|
||||
lappend flist $f
|
||||
set conffiledict [dict create bn "work" l "local" i "vlogsyn" q $f]
|
||||
dict set fi $f $conffiledict
|
||||
}
|
||||
}
|
||||
|
||||
foreach f $VERILOGSIMFILES {
|
||||
if {[file exists $f] } {
|
||||
lappend flist $f
|
||||
set conffiledict [dict create bn "work" l "local" i "vlogsim" q $f]
|
||||
dict set fi $f $conffiledict
|
||||
}
|
||||
}
|
||||
|
||||
if {[dict exists $ft "$GRLIB/lib/work" ] } {
|
||||
set worklibdict [dict get $ft "$GRLIB/lib/work"]
|
||||
} else {
|
||||
set worklibdict [dict create]
|
||||
set libdict [dict create k_real "$GRLIB_real/lib/work" bn "work"]
|
||||
dict set fi "$GRLIB/lib/work" $libdict
|
||||
}
|
||||
|
||||
dict set worklibdict "local" $flist
|
||||
set ft [dict remove $ft "work"]
|
||||
dict set ft "$GRLIB/lib/work" $worklibdict
|
||||
|
||||
}
|
||||
|
||||
proc mergefiletrees {filetree extrafiletree} {
|
||||
foreach extralib [dict keys $extrafiletree] {
|
||||
set foundlib 0
|
||||
foreach lib [dict keys $filetree] {
|
||||
if {[string equal $lib $extralib]} {
|
||||
set foundlib 1
|
||||
foreach extradir [dict keys [dict get $extrafiletree $lib] ] {
|
||||
set founddir 0
|
||||
foreach dir [dict keys [dict get $filetree $lib] ] {
|
||||
if {[string equal $dir $extradir] } {
|
||||
set founddir 1
|
||||
foreach extrafile [dict get [dict get $extrafiletree $extralib] $extradir] {
|
||||
set foundfile 0
|
||||
foreach regularfile [dict get [dict get $filetree $lib] $dir] {
|
||||
if {[string equal $regularfile $extrafile] } {
|
||||
set foundfile 1
|
||||
break
|
||||
}
|
||||
}
|
||||
if {!$foundfile} {
|
||||
set libdict [dict get $filetree $lib]
|
||||
set dirlist [dict get $libdict $dir]
|
||||
lappend dirlist $extrafile
|
||||
set libdict [dict remove $libdict $dir]
|
||||
dict set libdict $dir $dirlist
|
||||
set filetree [dict remove $filetree $lib]
|
||||
dict set filetree $lib $libdict
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
if {!$founddir} {
|
||||
set libdict [dict get $filetree $lib]
|
||||
dict set libdict $extradir [dict get [dict get $extrafiletree $extralib] $extradir]
|
||||
set filetree [dict remove $filetree $lib]
|
||||
dict set filetree $lib $libdict
|
||||
}
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
if {!$foundlib} {
|
||||
dict set filetree $extralib [dict get $extrafiletree $extralib]
|
||||
}
|
||||
}
|
||||
return $filetree
|
||||
}
|
||||
|
||||
proc mergefileinfos {fileinfo extrafileinfo} {
|
||||
foreach extrafile [dict keys $extrafileinfo] {
|
||||
set found 0
|
||||
foreach regularfile [dict keys $fileinfo] {
|
||||
if {[string equal $regularfile $extrafile] } {
|
||||
set fileinfo [dict remove $fileinfo $extrafile]
|
||||
dict set fileinfo $extrafile [dict get $extrafileinfo $extrafile]
|
||||
set found 1
|
||||
}
|
||||
}
|
||||
if {!$found} {
|
||||
dict set fileinfo $extrafile [dict get $extrafileinfo $extrafile]
|
||||
}
|
||||
}
|
||||
return $fileinfo
|
||||
}
|
||||
|
||||
set varfile [open "$GRLIB/bin/scriptgen/scriptgen_variables.txt" r]
|
||||
set envvars [split [read $varfile] "\n" ]
|
||||
|
||||
foreach envvar $envvars {
|
||||
if {$envvar != "" && ![info exists $envvar]} {
|
||||
puts "No value found for $envvar, setting it to {}"
|
||||
puts {\n}
|
||||
set $envvar {}
|
||||
}
|
||||
}
|
||||
|
||||
set filetree [dict create]
|
||||
set fileinfo [dict create]
|
||||
set GRLIB [file dirname $GRLIB/bin]
|
||||
generatefilelists filetree fileinfo
|
||||
set filetree [mergefiletrees $filetree $extrafiletree]
|
||||
set fileinfo [mergefileinfos $fileinfo $extrafileinfo]
|
||||
|
||||
|
||||
|
||||
set basenames {}
|
||||
foreach f [dict keys $filetree] {
|
||||
lappend basenames [dict get [dict get $fileinfo $f] bn]
|
||||
}
|
||||
set libtxtfile [open "libs.txt" w]
|
||||
puts $libtxtfile "$basenames "
|
||||
close $libtxtfile
|
||||
|
||||
foreach tool $tools {
|
||||
switch $tool {
|
||||
"actel" - "aldec" - "altera" - "cdns" - "ghdl" -
|
||||
"lattice" - "mentor" - "microsemi" - "snps" -
|
||||
"xlnx" {
|
||||
if { [ file exists "$GRLIB/bin/scriptgen/filebuild/$tool.tcl" ] } {
|
||||
source "$GRLIB/bin/scriptgen/filebuild/$tool.tcl"
|
||||
}
|
||||
continue
|
||||
}
|
||||
default {
|
||||
if { [catch {source "scriptgenwork/filebuild/$tool.tcl"} fid] } {
|
||||
puts stderr "Error with added tool: \"$tool\"!"
|
||||
puts stderr "$fid\n"
|
||||
puts stderr "Continuing:\n"
|
||||
}
|
||||
continue
|
||||
}
|
||||
}
|
||||
}
|
||||
78
bin/scriptgen/dependencies.tcl
Normal file
78
bin/scriptgen/dependencies.tcl
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
|
||||
set toolsstring ""
|
||||
|
||||
if {[info exists ::env(TOP)]} {
|
||||
set TOP $::env(TOP)
|
||||
}
|
||||
if {[info exists ::env(GRLIB)]} {
|
||||
set GRLIB $::env(GRLIB)
|
||||
}
|
||||
|
||||
if {[expr ![string equal [glob -nocomplain -type d scriptgenwork] scriptgenwork ] ] } {
|
||||
if {[expr ![string equal [glob -nocomplain -type d scriptgencfg] scriptgencfg ] ] } {
|
||||
file copy $GRLIB/bin/scriptgen/scriptgencfg scriptgenwork
|
||||
} else {
|
||||
file copy scriptgencfg scriptgenwork
|
||||
}
|
||||
}
|
||||
|
||||
source "scriptgenwork/tools.tcl"
|
||||
foreach tool $tools {
|
||||
switch $tool {
|
||||
"aldec" {
|
||||
append toolsstring "compile.asim "
|
||||
append toolsstring "make.riviera "
|
||||
append toolsstring "riviera_ws_create.do "
|
||||
continue
|
||||
}
|
||||
"altera" {
|
||||
append toolsstring "$TOP\_quartus.qsf "
|
||||
continue
|
||||
}
|
||||
"cdns" {
|
||||
append toolsstring "compile.ncsim "
|
||||
append toolsstring "compile.rc "
|
||||
append toolsstring "$TOP\.rc "
|
||||
continue
|
||||
}
|
||||
"ghdl" {
|
||||
append toolsstring "make.ghdl "
|
||||
continue
|
||||
}
|
||||
"lattice" {
|
||||
append toolsstring "$TOP\.ldf "
|
||||
continue
|
||||
}
|
||||
"mentor" {
|
||||
append toolsstring "compile.vsim "
|
||||
append toolsstring "modelsim.ini "
|
||||
append toolsstring "$TOP\_rtl_fpro.fl "
|
||||
continue
|
||||
}
|
||||
"microsemi" {
|
||||
append toolsstring "$TOP\_designer.tcl "
|
||||
append toolsstring "$TOP\_libero.prj "
|
||||
continue
|
||||
}
|
||||
"snps" {
|
||||
append toolsstring "compile.simv "
|
||||
append toolsstring "synopsys_sim.setup "
|
||||
append toolsstring "compile.dc "
|
||||
append toolsstring "compile.synp "
|
||||
append toolsstring "$TOP\_synplify.prj "
|
||||
append toolsstring "$TOP\_dc.tcl "
|
||||
continue
|
||||
}
|
||||
"xlnx" {
|
||||
append toolsstring "vivado/$TOP\_vivado.tcl "
|
||||
append toolsstring "planahead/$TOP\_planAhead.tcl "
|
||||
append toolsstring "compile.xst "
|
||||
append toolsstring "$TOP.xst "
|
||||
append toolsstring "$TOP.npl "
|
||||
append toolsstring "$TOP\_ise.tcl "
|
||||
continue
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
puts $toolsstring
|
||||
83
bin/scriptgen/filebuild/actel.tcl
Normal file
83
bin/scriptgen/filebuild/actel.tcl
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
proc actel_create_tool { } {
|
||||
global DESIGNER_LAYOUT_OPT DESIGNER_PACKAGE DESIGNER_PART DESIGNER_PINS DESIGNER_RADEXP DESIGNER_TECHNOLOGY DESIGNER_TEMPR DESIGNER_VOLTAGE DESIGNER_VOLTRANGE GRLIB PDC PDC_EXTRA SDC SDC_EXTRA SPEED TECHNOLOGY TOP
|
||||
|
||||
set configinfo "new_design -name \"$TOP\" -family \"$DESIGNER_TECHNOLOGY\"\n"
|
||||
if {[string equal $DESIGNER_RADEXP "" ] } {
|
||||
append configinfo "set_device -die \"$DESIGNER_PART\" -package \"$DESIGNER_PINS $DESIGNER_PACKAGE\" -speed \"$SPEED\" -voltage \"$DESIGNER_VOLTAGE\" -iostd \"LVTTL\" -jtag \"yes\" -probe \"yes\" -trst \"yes\" -temprange \"$DESIGNER_TEMPR\" -voltrange \"$DESIGNER_VOLTRANGE\"\n"
|
||||
} else {
|
||||
append configinfo "set_device -die \"$DESIGNER_PART\" -package \"$DESIGNER_PINS $DESIGNER_PACKAGE\" -speed \"$SPEED\" -voltage \"$DESIGNER_VOLTAGE\" -iostd \"LVTTL\" -jtag \"yes\" -probe \"yes\" -trst \"yes\" -temprange \"$DESIGNER_TEMPR\" -voltrange \"$DESIGNER_VOLTRANGE\" -radexp \"$DESIGNER_RADEXP\"\n"
|
||||
}
|
||||
append configinfo "if {\[file exist $TOP.pdc\]} {\n"
|
||||
append configinfo "import_source -format \"edif\" -edif_flavor \"GENERIC\" -merge_physical \"no\" -merge_timing \"no\" {synplify/$TOP.edf} -format \"pdc\" -abort_on_error \"no\" {$TOP.pdc}\n"
|
||||
append configinfo "} else {\n"
|
||||
append configinfo "import_source -format \"edif\" -edif_flavor \"GENERIC\" -merge_physical \"no\" -merge_timing \"no\" {synplify/$TOP.edf}\n"
|
||||
append configinfo "}\n"
|
||||
set designer_act_file [open "$TOP\_designer_act.tcl" w]
|
||||
|
||||
puts $designer_act_file $configinfo
|
||||
puts $designer_act_file "save_design {$TOP.adb}\n"
|
||||
close $designer_act_file
|
||||
|
||||
append configinfo "compile -combine_register 1\n"
|
||||
if {![string equal $PDC ""] } {
|
||||
append configinfo "if {\[file exists $PDC\]} {\n"
|
||||
append configinfo " import_aux -format \"pdc\" -abort_on_error \"no\" {$PDC}\n"
|
||||
append configinfo " pin_commit\n"
|
||||
append configinfo "} else {\n"
|
||||
append configinfo " puts \"WARNING: No PDC file imported.\"\n"
|
||||
append configinfo "}\n"
|
||||
} else {
|
||||
append configinfo "puts \"WARNING: No PDC file imported.\"\n"
|
||||
}
|
||||
if {![string equal $PDC_EXTRA ""] } {
|
||||
append configinfo "if {\[file exists $PDC_EXTRA\]} {\n"
|
||||
append configinfo " import_aux -format \"pdc\" -abort_on_error \"no\" {$PDC_EXTRA}\n"
|
||||
append configinfo " pin_commit\n"
|
||||
append configinfo "} else {\n"
|
||||
append configinfo " puts \"WARNING: No PDC_EXTRA file imported.\"\n"
|
||||
append configinfo "}\n"
|
||||
}
|
||||
if {![string equal $SDC ""] } {
|
||||
append configinfo "if {\[file exists $SDC\]} {\n"
|
||||
append configinfo " import_aux -format \"sdc\" -merge_timing \"no\" {$SDC}\n"
|
||||
append configinfo "} else {\n"
|
||||
append configinfo " puts \"WARNING: No SDC file imported.\"\n"
|
||||
append configinfo "}\n"
|
||||
} else {
|
||||
append configinfo "puts \"WARNING: No SDC file imported.\"\n"
|
||||
}
|
||||
if {![string equal $SDC_EXTRA ""] } {
|
||||
append configinfo "if {\[file exists $SDC_EXTRA\]} {\n"
|
||||
append configinfo " import_aux -format \"sdc\" -merge_timing \"yes\" {$SDC_EXTRA}\n"
|
||||
append configinfo "} else {\n"
|
||||
append configinfo " puts \"WARNING: No SDC_EXTRA file imported.\"\n"
|
||||
append configinfo "}\n"
|
||||
}
|
||||
append configinfo "save_design {$TOP.adb}\n"
|
||||
append configinfo "report -type status {./actel/report_status_pre.log}\n"
|
||||
append configinfo "layout $DESIGNER_LAYOUT_OPT\n"
|
||||
append configinfo "save_design {$TOP.adb}\n"
|
||||
append configinfo "backannotate -dir {./actel} -name \"$TOP\" -format \"SDF\" -language \"VHDL93\" -netlist\n"
|
||||
append configinfo "report -type \"timer\" -analysis \"max\" -print_summary \"yes\" -use_slack_threshold \"no\" -print_paths \"yes\" -max_paths 100 -max_expanded_paths 5 -include_user_sets \"yes\" -include_pin_to_pin \"yes\" -select_clock_domains \"no\" {./actel/report_timer_max.txt}\n"
|
||||
append configinfo "report -type \"timer\" -analysis \"min\" -print_summary \"yes\" -use_slack_threshold \"no\" -print_paths \"yes\" -max_paths 100 -max_expanded_paths 5 -include_user_sets \"yes\" -include_pin_to_pin \"yes\" -select_clock_domains \"no\" {./actel/report_timer_min.txt}\n"
|
||||
append configinfo "report -type \"pin\" -listby \"name\" {./actel/report_pin_name.log}\n"
|
||||
append configinfo "report -type \"pin\" -listby \"number\" {./actel/report_pin_number.log}\n"
|
||||
append configinfo "report -type \"datasheet\" {./actel/report_datasheet.txt}\n"
|
||||
if {[string equal $TECHNOLOGY "Axcelerator" ] } {
|
||||
append configinfo "export -format \"AFM-APS2\" -trstb_pullup \"yes\" -global_set_fuse \"reset\" -axprg_set_algo \"UMA\" {./actel/$TOP.afm}\n"
|
||||
append configinfo "export -format \"prb\" {./actel/$TOP.prb}\n"
|
||||
} else {
|
||||
append configinfo "export -format \"pdb\" -feature \"prog_fpga\" -io_state \"Tri-State\" {./actel/$TOP.pdb}\n"
|
||||
}
|
||||
append configinfo "export -format log -diagnostic {./actel/report_log.log}\n"
|
||||
append configinfo "report -type status {./actel/report_status_post.log}\n"
|
||||
append configinfo "save_design {$TOP.adb}\n"
|
||||
|
||||
set libfile [open "$TOP\_designer.tcl" w]
|
||||
puts $libfile $configinfo
|
||||
close $libfile
|
||||
}
|
||||
|
||||
|
||||
actel_create_tool
|
||||
return
|
||||
58
bin/scriptgen/filebuild/aldec.tcl
Normal file
58
bin/scriptgen/filebuild/aldec.tcl
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
#Note: Special fixes are present to maintain a sequential make.riviera
|
||||
proc aldec_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
|
||||
source "$GRLIB/bin/scriptgen/filebuild/aldec_alibs.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/aldec_asim.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/aldec_make_riv.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/aldec_riv_create.tcl"
|
||||
|
||||
create_aldec_make_riv
|
||||
create_aldec_riv_create
|
||||
|
||||
set riv_path ""
|
||||
set riv_bn {}
|
||||
set riv_fs ""
|
||||
set previ ""
|
||||
set reachedoptfiles 0
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_aldec_alibs $k $kinfo
|
||||
append_lib_aldec_riv_create $k $kinfo riv_bn
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
if {!$reachedoptfiles && [string equal $bn "work"] && [string equal $l "local"] } {
|
||||
append_special_aldec_make_riv
|
||||
set reachedoptfiles 1
|
||||
}
|
||||
if {![string equal $i $previ] && ![string equal "" $previ] } {
|
||||
if {[string length $riv_fs] > 0 } {
|
||||
append_type_aldec_make_riv $k $kinfo $previ $riv_fs
|
||||
}
|
||||
set riv_fs ""
|
||||
}
|
||||
append_file_aldec_riv_create $f $finfo riv_fs $riv_path
|
||||
append_file_aldec_asim $f $finfo
|
||||
append_file_aldec_make_riv $f $finfo
|
||||
set previ $i
|
||||
}
|
||||
if {[string length $riv_fs] > 0 } {
|
||||
append_type_aldec_make_riv $k $kinfo $previ $riv_fs
|
||||
}
|
||||
set riv_fs ""
|
||||
set previ ""
|
||||
}
|
||||
}
|
||||
eof_aldec_alibs
|
||||
eof_aldec_asim
|
||||
eof_aldec_make_riv
|
||||
eof_aldec_riv_create
|
||||
}
|
||||
|
||||
aldec_create_tool $filetree $fileinfo
|
||||
return
|
||||
16
bin/scriptgen/filebuild/aldec_alibs.tcl
Normal file
16
bin/scriptgen/filebuild/aldec_alibs.tcl
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
set alibs_do_contents ""
|
||||
proc append_lib_aldec_alibs {k kinfo } {
|
||||
upvar alibs_do_contents adc
|
||||
set bn [dict get $kinfo bn]
|
||||
append adc "\nalib $bn $bn.lib "
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_aldec_alibs {} {
|
||||
upvar alibs_do_contents adc
|
||||
set alibfile [open "alibs.do" w]
|
||||
puts $alibfile $adc
|
||||
puts $alibfile "\ncd ../../"
|
||||
close $alibfile
|
||||
return
|
||||
}
|
||||
126
bin/scriptgen/filebuild/aldec_asim.tcl
Normal file
126
bin/scriptgen/filebuild/aldec_asim.tcl
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
set make_asim_addfile_contents ""
|
||||
set make_asim_contents ""
|
||||
set compile_asim_contents ""
|
||||
proc append_file_aldec_asim {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
global ACOM VHDLOPT
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ACOM $VHDLOPT $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_asim_contents mac
|
||||
global ACOM VHDLOPT
|
||||
append mac "\n\t$ACOM $VHDLOPT $bn $f"
|
||||
upvar make_asim_addfile_contents maac
|
||||
append maac "\naddfile -vhdl $f"
|
||||
} else {
|
||||
global ACOM VHDLOPT
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ACOM $VHDLOPT $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
global ALOG
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_asim_contents mac
|
||||
append mac "\n\t$ALOG $bn $f"
|
||||
|
||||
} else {
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ALOG $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global ALOG
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ALOG $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global ACOM VHDLOPT
|
||||
upvar make_asim_contents mac
|
||||
append mac "\n\t$ACOM $VHDLOPT $bn $f"
|
||||
upvar make_asim_addfile_contents maac
|
||||
append maac "\naddfile -vhdl $f"
|
||||
} else {
|
||||
upvar compile_asim_contents cac
|
||||
global ACOM VHDLOPT
|
||||
append cac "\t$ACOM $VHDLOPT $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
global ALOG
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_asim_contents mac
|
||||
append mac "\n\t$ALOG $bn $f"
|
||||
} else {
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ALOG $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global ALOG
|
||||
upvar compile_asim_contents cac
|
||||
append cac "\t$ALOG $bn $f\n"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_aldec_asim {} {
|
||||
upvar make_asim_contents mac
|
||||
upvar compile_asim_contents cac
|
||||
upvar make_asim_addfile_contents maac
|
||||
set compfile [open "compile.asim" w]
|
||||
if {[string length $cac] > 0 } {
|
||||
set cac [string range $cac 0 end-1]
|
||||
}
|
||||
puts $compfile $cac
|
||||
close $compfile
|
||||
set temp $cac
|
||||
append temp $mac
|
||||
set mac $temp
|
||||
set makefile [open "make.asim" w]
|
||||
puts $makefile $temp
|
||||
close $makefile
|
||||
set addfile [open "make.asim-addfile" w]
|
||||
puts $addfile $maac
|
||||
close $addfile
|
||||
return
|
||||
}
|
||||
116
bin/scriptgen/filebuild/aldec_make_riv.tcl
Normal file
116
bin/scriptgen/filebuild/aldec_make_riv.tcl
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
set make_riviera_contents ""
|
||||
proc create_aldec_make_riv {} {
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "all: \n"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_aldec_make_riv {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP VCOM VHDLOPT
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "\n\t$VCOM $VHDLOPT -work $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP VLOG
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "\n\t$VLOG -work $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP VCOM VHDLOPT
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "\n\t$VCOM $VHDLOPT -work $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP VLOG
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "\n\t$VLOG -work $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_special_aldec_make_riv {} {
|
||||
global GRLIB
|
||||
upvar make_riviera_contents mrc
|
||||
append mrc "\t@if test -r $GRLIB/lib/tech/secureip/ise/mcb_001.vp && test\
|
||||
-r modelsim/secureip; then vlog -quiet -novopt -work secureip\
|
||||
$GRLIB/lib/tech/secureip/ise/mcb_*.vp; fi"
|
||||
}
|
||||
|
||||
proc append_type_aldec_make_riv {k kinfo i riv_fs} {
|
||||
if {[string equal $i "vhdlsim"] || [string equal $i "vhdlsyn"] || [string equal $i "vhdlmtie"] || [string equal $i "vhdlp1735"] } {
|
||||
global VCOM
|
||||
upvar make_riviera_contents mrc
|
||||
set bn [dict get $kinfo bn]
|
||||
append mrc "\t$VCOM -work $bn $riv_fs\n"
|
||||
} elseif {[string equal $i "vlogsim"] || [string equal $i "vlogsyn"] } {
|
||||
global VLOG
|
||||
upvar make_riviera_contents mrc
|
||||
set bn [dict get $kinfo bn]
|
||||
append mrc "\t$VLOG -work $bn $riv_fs\n"
|
||||
} elseif {[string equal $i "svlogsim"] || [string equal $i "svlogsyn"] } {
|
||||
global SVLOG
|
||||
upvar make_riviera_contents mrc
|
||||
set bn [dict get $kinfo bn]
|
||||
append mrc "\t$SVLOG -work $bn $riv_fs\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_aldec_make_riv {} {
|
||||
upvar make_riviera_contents mrc
|
||||
global GRLIB
|
||||
set makefile [open "make.riviera" w]
|
||||
puts $makefile $mrc
|
||||
close $makefile
|
||||
}
|
||||
156
bin/scriptgen/filebuild/aldec_riv_create.tcl
Normal file
156
bin/scriptgen/filebuild/aldec_riv_create.tcl
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
set riviera_ws_create_do_contents ""
|
||||
proc create_aldec_riv_create {} {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
append rwcdc "workspace.create riviera_ws ."
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_aldec_riv_create {k kdict riv_bn} {
|
||||
upvar $riv_bn rivbn
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set bn [dict get $kdict bn]
|
||||
append rwcdc "\nworkspace.design.create $bn . "
|
||||
append rwcdc "\nworkspace.design.setactive $bn "
|
||||
foreach riv_bn_map $rivbn {
|
||||
append rwcdc "\nworkspace.dependencies.add $bn $riv_bn_map "
|
||||
}
|
||||
lappend rivbn $bn
|
||||
foreach riv_bn_map $rivbn {
|
||||
append rwcdc "\namap $riv_bn_map $riv_bn_map/$riv_bn_map/$riv_bn_map.lib "
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_aldec_riv_create {f finfo riv_fs riv_path} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
upvar $riv_fs rivfs
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
upvar $riv_fs rivfs
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
if {[string equal [glob -nocomplain "/$f"] "/$f" ] } {
|
||||
append rwcdc "\ndesign.file.add $f"
|
||||
} else {
|
||||
append rwcdc "\ndesign.file.add ../$f"
|
||||
}
|
||||
} else {
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
if {[string equal [glob -nocomplain "/$f"] "/$f" ] } {
|
||||
append rwcdc "\ndesign.file.add $f"
|
||||
} else {
|
||||
append rwcdc "\ndesign.file.add ../$f"
|
||||
}
|
||||
} else {
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
if {[string equal [glob -nocomplain "/$f"] "/$f" ] } {
|
||||
append rwcdc "\ndesign.file.add $f"
|
||||
} else {
|
||||
append rwcdc "\ndesign.file.add ../$f"
|
||||
}
|
||||
} else {
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
if {[string equal [glob -nocomplain "/$f"] "/$f" ] } {
|
||||
append rwcdc "\ndesign.file.add $f"
|
||||
} else {
|
||||
append rwcdc "\ndesign.file.add ../$f"
|
||||
}
|
||||
} else {
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
upvar $riv_fs rivfs
|
||||
set rivfs "$rivfs $f"
|
||||
set f_real [dict get $finfo f_real]
|
||||
append rwcdc "\ndesign.file.add $riv_path$f_real"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_aldec_riv_create {} {
|
||||
upvar riviera_ws_create_do_contents rwcdc
|
||||
set rivierafile [open "riviera_ws_create.do" w]
|
||||
puts $rivierafile $rwcdc
|
||||
close $rivierafile
|
||||
return
|
||||
}
|
||||
26
bin/scriptgen/filebuild/altera.tcl
Normal file
26
bin/scriptgen/filebuild/altera.tcl
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
proc altera_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/altera_quartus.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/altera_synplify.tcl"
|
||||
|
||||
create_altera_quartus
|
||||
create_altera_synplify
|
||||
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_altera_quartus $f $finfo
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_altera_quartus
|
||||
eof_altera_synplify
|
||||
}
|
||||
|
||||
altera_create_tool $filetree $fileinfo
|
||||
return
|
||||
112
bin/scriptgen/filebuild/altera_quartus.tcl
Normal file
112
bin/scriptgen/filebuild/altera_quartus.tcl
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
set TOP_quartus_qsf_contents ""
|
||||
set TOP_quartus_qpf_contents ""
|
||||
|
||||
proc create_altera_quartus {} {
|
||||
global GRLIB TOP
|
||||
upvar TOP_quartus_qsf_contents tqsc
|
||||
upvar TOP_quartus_qpf_contents tqpc
|
||||
set readfile [open "$GRLIB/bin/quartus.qsf_head" r]
|
||||
append tqsc [read $readfile]
|
||||
close $readfile
|
||||
set readfile [open "$GRLIB/bin/quartus.qpf" r]
|
||||
append tqpc [read $readfile]
|
||||
close $readfile
|
||||
append tqpc "PROJECT_REVISION = $TOP"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_altera_quartus {f finfo } {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global TOP
|
||||
upvar TOP_quartus_qsf_contents tqsc
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
append tqsc "set_global_assignment -name VHDL_FILE $f\n"
|
||||
} else {
|
||||
global QUARTUSLIBSKIP QDIRSKIP QUARTUSSKIP
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $QUARTUSLIBSKIP $bn] < 0 && [lsearchmatch $QDIRSKIP $l] < 0 && [lsearchmatch $QUARTUSSKIP $q] < 0 } {
|
||||
append tqsc "set_global_assignment -name VHDL_FILE $f -library $bn\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global TOP
|
||||
upvar TOP_quartus_qsf_contents tqsc
|
||||
append tqsc "set_global_assignment -name VERILOG_FILE $f -library $bn\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global TOP
|
||||
upvar TOP_quartus_qsf_contents tqsc
|
||||
append tqsc "set_global_assignment -name VERILOG_FILE $f -library $bn\n"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_altera_quartus {} {
|
||||
global TOP QSF QSF_APPEND
|
||||
upvar TOP_quartus_qsf_contents tqsc
|
||||
upvar TOP_quartus_qpf_contents tqpc
|
||||
append tqsc "\nset_global_assignment -name TOP_LEVEL_ENTITY \"$TOP\""
|
||||
if {[string equal [glob -nocomplain "$QSF"] $QSF ] } {
|
||||
set readfile [open "$QSF" r]
|
||||
append tqsc "\n[read $readfile]"
|
||||
close $readfile
|
||||
}
|
||||
if {[string equal [glob -nocomplain "$QSF_APPEND"] $QSF_APPEND ] } {
|
||||
set readfile [open "$QSF_APPEND" r]
|
||||
append tqsc "\n[read $readfile]"
|
||||
close $readfile
|
||||
}
|
||||
set qsffile [open "$TOP\_quartus.qsf" w]
|
||||
puts $qsffile $tqsc
|
||||
close $qsffile
|
||||
set qpffile [open "$TOP\_quartus.qpf" w]
|
||||
puts $qpffile $tqpc
|
||||
close $qpffile
|
||||
return
|
||||
}
|
||||
37
bin/scriptgen/filebuild/altera_synplify.tcl
Normal file
37
bin/scriptgen/filebuild/altera_synplify.tcl
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
set TOP_synplify_qsf_contents ""
|
||||
set TOP_synplify_qpf_contents ""
|
||||
|
||||
proc create_altera_synplify {} {
|
||||
global GRLIB TOP QSF
|
||||
upvar TOP_synplify_qsf_contents tssc
|
||||
upvar TOP_synplify_qpf_contents tspc
|
||||
set readfile [open "$GRLIB/bin/quartus.qsf_head" r]
|
||||
append tssc [read $readfile]
|
||||
close $readfile
|
||||
append tssc "set_global_assignment -name VQM_FILE synplify/$TOP.edf"
|
||||
if {[file exists $QSF] } {
|
||||
append tssc "\n"
|
||||
set readfile [open "$QSF" r]
|
||||
append tssc [read $readfile]
|
||||
close $readfile
|
||||
}
|
||||
set readfile [open "$GRLIB/bin/quartus.qpf" r]
|
||||
append tspc [read $readfile]
|
||||
close $readfile
|
||||
append tspc "PROJECT_REVISION = $TOP\_synplify"
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_altera_synplify {} {
|
||||
global TOP
|
||||
upvar TOP_synplify_qsf_contents tssc
|
||||
upvar TOP_synplify_qpf_contents tspc
|
||||
set qsffile [open "$TOP\_synplify.qsf" w]
|
||||
append tssc "\n\nset_global_assignment -name TOP_LEVEL_ENTITY \"$TOP\""
|
||||
puts $qsffile $tssc
|
||||
close $qsffile
|
||||
set qpffile [open "$TOP\_synplify.qpf" w]
|
||||
puts $qpffile $tspc
|
||||
close $qpffile
|
||||
return
|
||||
}
|
||||
33
bin/scriptgen/filebuild/cdns.tcl
Normal file
33
bin/scriptgen/filebuild/cdns.tcl
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
proc cdns_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/cdns_cds.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/cdns_hdl.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/cdns_ncsim.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/cdns_rc.tcl"
|
||||
|
||||
create_cdns_cds
|
||||
create_cdns_hdl
|
||||
create_cdns_ncsim
|
||||
create_cdns_rc
|
||||
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_cdns_cds $k $kinfo
|
||||
append_lib_cdns_ncsim $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_cdns_ncsim $f $finfo
|
||||
append_file_cdns_rc $f $finfo
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_cdns_cds
|
||||
eof_cdns_ncsim
|
||||
eof_cdns_rc
|
||||
}
|
||||
|
||||
cdns_create_tool $filetree $fileinfo
|
||||
return
|
||||
28
bin/scriptgen/filebuild/cdns_cds.tcl
Normal file
28
bin/scriptgen/filebuild/cdns_cds.tcl
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
set cds_lib_contents ""
|
||||
proc create_cdns_cds {} {
|
||||
upvar cds_lib_contents clc
|
||||
global GRLIB
|
||||
set readfile [open "$GRLIB/bin/cds.lib" r]
|
||||
append clc [read $readfile]
|
||||
close $readfile
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_cdns_cds {k kinfo} {
|
||||
upvar cds_lib_contents clc
|
||||
set bn [dict get $kinfo bn]
|
||||
append clc "DEFINE $bn xncsim/$bn \n"
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_cdns_cds {} {
|
||||
upvar cds_lib_contents clc
|
||||
if {[string length $clc] > 0 } {
|
||||
set clc [string range $clc 0 end-1]
|
||||
}
|
||||
set cdfile [open "cds.lib" a]
|
||||
puts $cdfile $clc
|
||||
close $cdfile
|
||||
return
|
||||
}
|
||||
|
||||
5
bin/scriptgen/filebuild/cdns_hdl.tcl
Normal file
5
bin/scriptgen/filebuild/cdns_hdl.tcl
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
proc create_cdns_hdl {} {
|
||||
set hdlfile [open "hdl.var" w]
|
||||
close $hdlfile
|
||||
return
|
||||
}
|
||||
145
bin/scriptgen/filebuild/cdns_ncsim.tcl
Normal file
145
bin/scriptgen/filebuild/cdns_ncsim.tcl
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
set compile_ncsim_contents ""
|
||||
set make_ncsim_contents ""
|
||||
|
||||
proc create_cdns_ncsim {} {
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\tmkdir xncsim"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_cdns_ncsim {k kinfo} {
|
||||
upvar compile_ncsim_contents cnc
|
||||
set bn [dict get $kinfo bn]
|
||||
append cnc "\n\tmkdir xncsim/$bn"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_cdns_ncsim {f finfo} {
|
||||
global VHDLOPT NCVHDL NCVLOG
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\n\t$NCVHDL $VHDLOPT $bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global NCVHDL VHDLOPT
|
||||
upvar make_ncsim_contents mnc
|
||||
append mnc "\n\t$NCVHDL $VHDLOPT $bn $f"
|
||||
} else {
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\n\t$NCVHDL $VHDLOPT $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global NCVLOG
|
||||
upvar make_ncsim_contents mnc
|
||||
append mnc "\n\t$NCVLOG $bn $f"
|
||||
} else {
|
||||
upvar compile_ncsim_contents cnc
|
||||
set k [dict get $finfo k]
|
||||
append cnc "\n\t$NCVLOG $bn -INCDIR $k/$l $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global NCVLOG
|
||||
upvar compile_ncsim_contents cnc
|
||||
set l [dict get $finfo l]
|
||||
set k [dict get $finfo k]
|
||||
append cnc "\n\t$NCVLOG $bn -INCDIR $k/$l $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global NCVHDL VHDLOPT
|
||||
upvar make_ncsim_contents mnc
|
||||
append mnc "\n\t$NCVHDL $VHDLOPT $bn $f"
|
||||
} else {
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\n\t$NCVHDL $VHDLOPT $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global NCVLOG
|
||||
upvar make_ncsim_contents mnc
|
||||
append mnc "\n\t$NCVLOG $bn $f"
|
||||
} else {
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\n\t$NCVLOG $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global NCVLOG
|
||||
upvar compile_ncsim_contents cnc
|
||||
append cnc "\n\t$NCVLOG $bn $f"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_cdns_ncsim {} {
|
||||
upvar compile_ncsim_contents cnc
|
||||
upvar make_ncsim_contents mnc
|
||||
global SIMTOP errorInfo
|
||||
set temp "ncsim:\n"
|
||||
append temp $cnc
|
||||
append temp $mnc
|
||||
set mnc $temp
|
||||
if {[string equal [glob -nocomplain "$SIMTOP.vhd"] "$SIMTOP.vhd" ] } {
|
||||
set goterr [catch {
|
||||
set arch [lindex [split [exec grep -i architecture $SIMTOP.vhd | grep -i $SIMTOP] ] 1]
|
||||
}]
|
||||
if { $goterr } {
|
||||
set arch "sim"
|
||||
puts stderr "cdns_ncsim: Failed to get test bench architecture, defaulting to $arch"
|
||||
puts stderr "cdns_ncsim: error_info: $errorInfo"
|
||||
}
|
||||
append mnc "\n\tncelab -timescale 10ps/10ps $SIMTOP:$arch"
|
||||
} else {
|
||||
if {[string equal [glob -nocomplain "$SIMTOP.v"] "$SIMTOP.v" ] } {
|
||||
append mnc "\n\tncelab -timescale 10ps/10ps $SIMTOP"
|
||||
}
|
||||
}
|
||||
set makefile [open "make.ncsim" w]
|
||||
puts $makefile $mnc
|
||||
close $makefile
|
||||
set compfile [open "compile.ncsim" w]
|
||||
puts $compfile $cnc
|
||||
close $compfile
|
||||
return
|
||||
}
|
||||
87
bin/scriptgen/filebuild/cdns_rc.tcl
Normal file
87
bin/scriptgen/filebuild/cdns_rc.tcl
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
set compile_rc_contents ""
|
||||
proc create_cdns_rc {} {
|
||||
upvar compile_rc_contents crc
|
||||
append crc "set_attribute input_pragma_keyword \"cadence synopsys get2chip g2c fast ambit pragma\""
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_cdns_rc {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
global RTLCVHDL VHDLOPT
|
||||
upvar compile_rc_contents crc
|
||||
append crc "\n$RTLCVHDL $VHDLOPT$bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global RTLCVHDL VHDLOPT XDCLIBSKIP XDCDIRSKIP DCSKIP
|
||||
upvar compile_rc_contents crc
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XDCLIBSKIP $bn] < 0 && [lsearchmatch $XDCDIRSKIP $l] < 0 && [lsearchmatch $DCSKIP $q] < 0 } {
|
||||
append crc "\n$RTLCVHDL $VHDLOPT$bn $f"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global RTLCVLOG
|
||||
upvar compile_rc_contents crc
|
||||
append crc "\n$RTLCVLOG $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global RTLCVLOG
|
||||
upvar compile_rc_contents crc
|
||||
append crc "\n$RTLCVLOG $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_cdns_rc {} {
|
||||
upvar compile_rc_contents crc
|
||||
set rcfile [open "compile.rc" w]
|
||||
puts $rcfile $crc
|
||||
close $rcfile
|
||||
}
|
||||
24
bin/scriptgen/filebuild/ghdl.tcl
Normal file
24
bin/scriptgen/filebuild/ghdl.tcl
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
proc ghdl_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/ghdl_make.tcl"
|
||||
create_ghdl_make
|
||||
set qpath "-Pgnu"
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
set bn [dict get $kinfo bn]
|
||||
set qpath "$qpath -Pgnu/$bn"
|
||||
append_lib_ghdl_make $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_ghdl_make $f $finfo $qpath
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_ghdl_make $qpath
|
||||
}
|
||||
|
||||
ghdl_create_tool $filetree $fileinfo
|
||||
return
|
||||
83
bin/scriptgen/filebuild/ghdl_make.tcl
Normal file
83
bin/scriptgen/filebuild/ghdl_make.tcl
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
set make_ghdl_contents ""
|
||||
proc create_ghdl_make {} {
|
||||
upvar make_ghdl_contents mgc
|
||||
append mgc "# Import files in libraries\n"
|
||||
append mgc ".PHONY: ghdl-import\n"
|
||||
append mgc "ghdl-import:\n"
|
||||
append mgc "\tmkdir -p gnu"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_ghdl_make {k kinfo} {
|
||||
upvar make_ghdl_contents mgc
|
||||
set bn [dict get $kinfo bn]
|
||||
append mgc "\n\tmkdir -p gnu/$bn"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_ghdl_make {f finfo qpath} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global GHDLI GHDLIOPT
|
||||
upvar make_ghdl_contents mgc
|
||||
append mgc "\n\t$GHDLI $GHDLIOPT --workdir=gnu/$bn --work=$bn $qpath $f"
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
global GHDLI GHDLIOPT
|
||||
upvar make_ghdl_contents mgc
|
||||
append mgc "\n\t$GHDLI $GHDLIOPT --workdir=gnu/$bn --work=$bn $qpath $f"
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_ghdl_make {qpath} {
|
||||
upvar make_ghdl_contents mgc
|
||||
set pathfile [open "ghdl.path" w]
|
||||
puts $pathfile $qpath
|
||||
close $pathfile
|
||||
set ghdlfile [open "make.ghdl" w]
|
||||
puts $ghdlfile $mgc
|
||||
close $ghdlfile
|
||||
return
|
||||
}
|
||||
29
bin/scriptgen/filebuild/lattice.tcl
Normal file
29
bin/scriptgen/filebuild/lattice.tcl
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
proc lattice_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/lattice_top_lct.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/lattice_top_ldf.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/lattice_top_syn.tcl"
|
||||
|
||||
if {[expr ![string equal [glob -nocomplain -type d lattice] lattice ] ] } {
|
||||
file mkdir lattice
|
||||
}
|
||||
|
||||
create_lattice_top_ldf
|
||||
create_lattice_top_lct
|
||||
create_lattice_top_syn
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_lattice_top_ldf $f $finfo
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_lattice_top_ldf
|
||||
}
|
||||
|
||||
lattice_create_tool $filetree $fileinfo
|
||||
return
|
||||
17
bin/scriptgen/filebuild/lattice_top_lct.tcl
Normal file
17
bin/scriptgen/filebuild/lattice_top_lct.tcl
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
proc create_lattice_top_lct {} {
|
||||
global ISPLIB PART SPEED PACKAGE ISPPACKAGE TOP
|
||||
set tlc ""
|
||||
append tlc "\[Device\]\n"
|
||||
append tlc "Family = $ISPLIB;\n"
|
||||
append tlc "PartNumber = $PART$SPEED$PACKAGE;\n"
|
||||
append tlc "Package = $ISPPACKAGE;\n"
|
||||
append tlc "PartType = $PART;\n"
|
||||
append tlc "Speed = $SPEED;\n"
|
||||
append tlc "Operating_condition = COM;\n"
|
||||
append tlc "Status = Production;"
|
||||
set lctfile [open "$TOP.lct" w]
|
||||
puts $lctfile $tlc
|
||||
close $lctfile
|
||||
return
|
||||
}
|
||||
|
||||
99
bin/scriptgen/filebuild/lattice_top_ldf.tcl
Normal file
99
bin/scriptgen/filebuild/lattice_top_ldf.tcl
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
set TOP_ldf_contents ""
|
||||
proc create_lattice_top_ldf {} {
|
||||
global TOP PART SPEED PACKAGE
|
||||
upvar TOP_ldf_contents tlc
|
||||
append tlc "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n"
|
||||
append tlc "<BaliProject version=\"1.3\" title=\"$TOP\" device=\"$PART$SPEED$PACKAGE\" default_implementation=\"$TOP\">\n"
|
||||
append tlc " <Options/>\n"
|
||||
append tlc " <Implementation title=\"$TOP\" dir=\"lattice\" description=\"$TOP\" default_strategy=\"Timing\">\n"
|
||||
append tlc " <Options/>\n"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_lattice_top_ldf {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set q [dict get $finfo q]
|
||||
set l [dict get $finfo l]
|
||||
global XSYNPLIBSKIP XSYNPDIRSKIP SYNPSKIP TOP
|
||||
if {[lsearchmatch $XSYNPLIBSKIP $bn] < 0 && [lsearchmatch $XSYNPDIRSKIP $l] < 0 && [lsearchmatch $SYNPSKIP $q] < 0 } {
|
||||
upvar TOP_ldf_contents tlc
|
||||
append tlc " <Source name=\"$f\" type=\"VHDL\" type_short=\"VHDL\">\n"
|
||||
if {[string equal $bn "work"] && [string equal $l "local" ] } {
|
||||
append tlc " <Options/>\n"
|
||||
} else {
|
||||
append tlc " <Options lib=\"$bn\"/>\n"
|
||||
}
|
||||
append tlc " </Source>\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global TOP
|
||||
upvar TOP_ldf_contents tlc
|
||||
append tlc " <Source name=\"$f\" type=\"VHDL\" type_short=\"VHDL\" syn_sim=\"SimOnly\" excluded=\"TRUE\" >\n"
|
||||
append tlc " <Options lib=\"$bn\"/>\n"
|
||||
append tlc " </Source>\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_lattice_top_ldf {} {
|
||||
global UCF SDCFILE TOP
|
||||
upvar TOP_ldf_contents tlc
|
||||
append tlc " <Source name=\"$UCF\" type=\"Logic Preference\" type_short=\"LPF\">\n"
|
||||
append tlc " <Options/>\n"
|
||||
append tlc " </Source>\n"
|
||||
append tlc " <Source name=\"$SDCFILE\" type=\"Synplify Design Constraints File\" type_short=\"SDC\">\n"
|
||||
append tlc " <Options/>\n"
|
||||
append tlc " </Source>\n"
|
||||
append tlc " </Implementation>\n"
|
||||
append tlc "</BaliProject>"
|
||||
set ldffile [open "$TOP.ldf" a]
|
||||
puts $ldffile $tlc
|
||||
close $ldffile
|
||||
}
|
||||
16
bin/scriptgen/filebuild/lattice_top_syn.tcl
Normal file
16
bin/scriptgen/filebuild/lattice_top_syn.tcl
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
proc create_lattice_top_syn {} {
|
||||
global PART SPEED PACKAGE TOP
|
||||
set tsc ""
|
||||
append tsc "JDF B\n"
|
||||
append tsc "PROJECT $TOP\n"
|
||||
append tsc "DESIGN $TOP Normal\n"
|
||||
append tsc "DEVKIT $PART$SPEED$PACKAGE\n"
|
||||
append tsc "ENTRY EDIF\n"
|
||||
append tsc "MODULE ./synplify/$TOP.edf\n"
|
||||
append tsc "MODSTYLE $TOP Normal"
|
||||
set lctfile [open "$TOP.syn" w]
|
||||
puts $lctfile $tsc
|
||||
close $lctfile
|
||||
return
|
||||
}
|
||||
|
||||
53
bin/scriptgen/filebuild/mentor.tcl
Normal file
53
bin/scriptgen/filebuild/mentor.tcl
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
proc mentor_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/mentor_modelsim.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/mentor_precision.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/mentor_top_fpro.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/mentor_vsim.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/mentor_simtop_mpf.tcl"
|
||||
|
||||
create_mentor_modelsim
|
||||
create_mentor_precision
|
||||
create_mentor_top_fpro
|
||||
|
||||
set nfiles 0
|
||||
set fpro_fs ""
|
||||
set previ ""
|
||||
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_mentor_modelsim $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
set i [dict get $finfo i]
|
||||
if {![string equal $i $previ] && ![string equal "" $previ]} {
|
||||
if {[string length $fpro_fs] > 0 } {
|
||||
append_type_mentor_top_fpro $k $kinfo $previ $fpro_fs
|
||||
}
|
||||
set fpro_fs ""
|
||||
}
|
||||
append_file_mentor_vsim $f $finfo
|
||||
append_file_mentor_simtop_mpf $f $finfo nfiles
|
||||
append_file_mentor_precision $f $finfo
|
||||
append_file_mentor_top_fpro $f $finfo fpro_fs
|
||||
set previ $i
|
||||
}
|
||||
if {[string length $fpro_fs] > 0 } {
|
||||
append_type_mentor_top_fpro $k $kinfo $previ $fpro_fs
|
||||
}
|
||||
set fpro_fs ""
|
||||
set previ ""
|
||||
}
|
||||
}
|
||||
eof_mentor_modelsim
|
||||
eof_mentor_simtop_mpf $nfiles
|
||||
eof_mentor_precision
|
||||
eof_mentor_top_fpro
|
||||
eof_mentor_vsim
|
||||
}
|
||||
|
||||
mentor_create_tool $filetree $fileinfo
|
||||
return
|
||||
35
bin/scriptgen/filebuild/mentor_modelsim.tcl
Normal file
35
bin/scriptgen/filebuild/mentor_modelsim.tcl
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
set libs_do_contents ""
|
||||
set modelsim_ini_contents ""
|
||||
proc create_mentor_modelsim {} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar modelsim_ini_contents mic
|
||||
append ldc "vlib modelsim"
|
||||
append mic {[Library]}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_mentor_modelsim {k kinfo} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar modelsim_ini_contents mic
|
||||
set bn [dict get $kinfo bn]
|
||||
append ldc "\nvlib modelsim/$bn "
|
||||
append mic "\n$bn = modelsim/$bn"
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_mentor_modelsim {} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar modelsim_ini_contents mic
|
||||
global GRLIB
|
||||
set libsfile [open "libs.do" w]
|
||||
puts $libsfile $ldc
|
||||
close $libsfile
|
||||
set readfile [open "$GRLIB/bin/modelsim.ini" r]
|
||||
set simfile [open "modelsim.ini" w]
|
||||
append mic "\n[read $readfile]"
|
||||
set mic [rmvlinebreak $mic]
|
||||
puts $simfile $mic
|
||||
close $readfile
|
||||
close $simfile
|
||||
return
|
||||
}
|
||||
103
bin/scriptgen/filebuild/mentor_precision.tcl
Normal file
103
bin/scriptgen/filebuild/mentor_precision.tcl
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
set TOP_precision_tcl_contents ""
|
||||
proc create_mentor_precision {} {
|
||||
global TOP PART MANUFACTURER MGCTECHNOLOGY MGCPART MGCPACKAGE SPEED
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
set configinfo "open_project ./$TOP.psp\n"
|
||||
append configinfo "compile\n"
|
||||
append configinfo "synthesize\n"
|
||||
append configinfo "save_impl"
|
||||
set precrunfile [open "$TOP\_precrun.tcl" w]
|
||||
puts $precrunfile $configinfo
|
||||
close $precrunfile
|
||||
append tptc "new_project -name $TOP -folder . -createimpl_name precision\n"
|
||||
append tptc "setup_design -manufacturer $MANUFACTURER -family\
|
||||
$MGCTECHNOLOGY -part $MGCPART -package $MGCPACKAGE -speed $SPEED\n"
|
||||
append tptc "set_input_dir .\n"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_mentor_precision {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
global TOP
|
||||
append tptc "add_input_file -format VHDL -work $bn -enc $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global PRECLIBSKIP PRECDIRSKIP PRECSKIP TOP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $PRECLIBSKIP $bn] < 0 && [lsearchmatch $PRECDIRSKIP $l] < 0 && [lsearchmatch $PRECSKIP $q] < 0 } {
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
append tptc "add_input_file -format VHDL -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global TOP
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
append tptc "add_input_file -format VERILOG -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global TOP
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
append tptc "add_input_file -format VERILOG -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_mentor_precision {} {
|
||||
global TOP SYNFREQ PRECOPT
|
||||
upvar TOP_precision_tcl_contents tptc
|
||||
append tptc "setup_design -design $TOP\n"
|
||||
append tptc "setup_design -retiming\n"
|
||||
append tptc "setup_design -vhdl\n"
|
||||
append tptc "setup_design -transformations=false\n"
|
||||
append tptc "setup_design -frequency=\"$SYNFREQ\"\n"
|
||||
append tptc "$PRECOPT\n"
|
||||
append tptc "save_impl"
|
||||
set precifile [open "$TOP\_precision.tcl" w]
|
||||
puts $precifile $tptc
|
||||
close $precifile
|
||||
return
|
||||
}
|
||||
174
bin/scriptgen/filebuild/mentor_simtop_mpf.tcl
Normal file
174
bin/scriptgen/filebuild/mentor_simtop_mpf.tcl
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
set SIMTOP_mpf_contents ""
|
||||
|
||||
proc append_file_mentor_simtop_mpf {f finfo nfiles} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vhdl_novitalcheck 0\
|
||||
file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0\
|
||||
vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0\
|
||||
vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1\
|
||||
vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $bn compile_order\
|
||||
$nf dont_compile 0 cover_stmt 1 vhdl_use93 93\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vhdl_novitalcheck 0\
|
||||
file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0\
|
||||
vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0\
|
||||
vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1\
|
||||
vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $bn compile_order\
|
||||
$nf dont_compile 0 cover_stmt 1 vhdl_use93 93\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vhdl_novitalcheck 0\
|
||||
file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0\
|
||||
vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0\
|
||||
vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1\
|
||||
vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $bn compile_order\
|
||||
$nf dont_compile 0 cover_stmt 1 vhdl_use93 93\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vlog_protect 0 file_type Verilog\
|
||||
group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0\
|
||||
last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1\
|
||||
compile_to $bn vlog_upper 0 vlog_options {} compile_order $nf dont_compile 0\n"
|
||||
incr nf
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vlog_protect 0 file_type Verilog\
|
||||
group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0\
|
||||
last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1\
|
||||
compile_to $bn vlog_upper 0 vlog_options {} compile_order $nf dont_compile 0\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vhdl_novitalcheck 0 file_type VHDL\
|
||||
group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level}\
|
||||
last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0\
|
||||
vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0\
|
||||
compile_to $bn compile_order $nf dont_compile 0 cover_stmt 1 vhdl_use93 93\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vlog_protect 0 file_type Verilog\
|
||||
group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0\
|
||||
last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1\
|
||||
compile_to $bn vlog_upper 0 vlog_options {} compile_order $nf dont_compile 0\n"
|
||||
incr nf
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global SIMTOP
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
upvar $nfiles nf
|
||||
append smc "Project_File_$nf = $f\n"
|
||||
append smc "Project_File_P_$nf = vlog_protect 0 file_type Verilog\
|
||||
group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0\
|
||||
last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1\
|
||||
compile_to $bn vlog_upper 0 vlog_options {} compile_order $nf dont_compile 0\n"
|
||||
incr nf
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_mentor_simtop_mpf {nfiles} {
|
||||
global SIMTOP GRLIB
|
||||
upvar SIMTOP_mpf_contents smc
|
||||
|
||||
set readfile [open "modelsim.ini" r]
|
||||
set temp [read $readfile]
|
||||
close $readfile
|
||||
|
||||
append temp "\[Project\]\n"
|
||||
append temp "Project_Version = 5\n"
|
||||
append temp "Project_DefaultLib = work\n"
|
||||
append temp "Project_SortMethod = unused\n"
|
||||
append temp "Project_Files_Count = $nfiles\n\n"
|
||||
|
||||
append temp $smc
|
||||
set smc $temp
|
||||
|
||||
append smc "Project_Sim_Count = 1\n"
|
||||
append smc "Project_Sim_0 = Simulation 1\n"
|
||||
append smc "Project_Sim_P_0 = Generics \{\} timing default -std_output \{\} +notimingchecks 0 -L \{\} selected_du \{\} -hazards 0 -sdf \{\} +acc \{\} ok 1 folder \{Top Level\} -absentisempty 0 +pulse_r \{\} OtherArgs \{\} -multisource_delay \{\} +pulse_e \{\} -coverage 0 -sdfnoerror 0 +plusarg \{\} -vital2.2b 0 -t ps additional_dus work.$SIMTOP -nofileshare 0 -noglitch 0 -wlf \{\} +no_pulse_msg 0 -assertfile \{\} -sdfnowarn 0 -Lf \{\} -std_input \{\}\n"
|
||||
|
||||
set readfile [open $GRLIB/bin/mt1.mpf r]
|
||||
append smc [read $readfile]
|
||||
close $readfile
|
||||
|
||||
if {[string length $smc] > 0 } {
|
||||
set smc [string range $smc 0 end-1]
|
||||
}
|
||||
|
||||
set mpffile [open "$SIMTOP.mpf" w]
|
||||
puts $mpffile $smc
|
||||
close $mpffile
|
||||
|
||||
return
|
||||
}
|
||||
97
bin/scriptgen/filebuild/mentor_top_fpro.tcl
Normal file
97
bin/scriptgen/filebuild/mentor_top_fpro.tcl
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
set TOP_rtl_fpro_fl_contents ""
|
||||
proc create_mentor_top_fpro {} {
|
||||
global TOP
|
||||
upvar TOP_rtl_fpro_fl_contents trffc
|
||||
append trffc "# FormalPro file list for $TOP design"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_mentor_top_fpro {f finfo fpro_fs} {
|
||||
set i [dict get $finfo i]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
upvar $fpro_fs fprofs
|
||||
set fprofs "$fprofs $f"
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set bn [dict get $finfo bn]
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP
|
||||
upvar TOP_rtl_fpro_fl_contents trffc
|
||||
append trffc "\n\t-work $bn $f"
|
||||
} else {
|
||||
upvar $fpro_fs fprofs
|
||||
set fprofs "$fprofs $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set bn [dict get $finfo bn]
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global TOP
|
||||
upvar TOP_rtl_fpro_fl_contents trffc
|
||||
append trffc "\n\t-work $bn $f"
|
||||
append trffc "\n\t-work $bn $f"
|
||||
} else {
|
||||
upvar $fpro_fs fprofs
|
||||
set fprofs "$fprofs $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
upvar $fpro_fs fprofs
|
||||
set fprofs "$fprofs $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_type_mentor_top_fpro {k kinfo i fpro_fs} {
|
||||
global TOP
|
||||
upvar TOP_rtl_fpro_fl_contents trffc
|
||||
set bn [dict get $kinfo bn]
|
||||
append trffc "\n\t-work $bn $fpro_fs"
|
||||
}
|
||||
|
||||
proc eof_mentor_top_fpro {} {
|
||||
global TOP
|
||||
upvar TOP_rtl_fpro_fl_contents trffc
|
||||
set fprofile [open "$TOP\_rtl_fpro.fl" a]
|
||||
puts $fprofile $trffc
|
||||
close $fprofile
|
||||
}
|
||||
|
||||
126
bin/scriptgen/filebuild/mentor_vsim.tcl
Normal file
126
bin/scriptgen/filebuild/mentor_vsim.tcl
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
set compile_vsim_contents ""
|
||||
set make_vsim_contents ""
|
||||
proc append_file_mentor_vsim {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
global VCOM VHDLOPT
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
global VCOM VHDLOPT
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global VCOM VHDLOPT
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_vsim_contents mvc
|
||||
append mvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
global VLOG
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_vsim_contents mvc
|
||||
append mvc "\t$VLOG -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_vsim_contents cvc
|
||||
set k [dict get $finfo k]
|
||||
set l [dict get $finfo l]
|
||||
append cvc "\t$VLOG -work $bn +incdir+$k/$l $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global SVLOG
|
||||
upvar compile_vsim_contents cvc
|
||||
set k [dict get $finfo k]
|
||||
set l [dict get $finfo l]
|
||||
append cvc "\t$SVLOG -sv -work $bn +incdir+$k/$l $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
global VCOM VHDLOPT
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_vsim_contents mvc
|
||||
append mvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VCOM $VHDLOPT -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
global VLOG
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_vsim_contents mvc
|
||||
append mvc "\t$VLOG -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VLOG -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global VLOG
|
||||
upvar compile_vsim_contents cvc
|
||||
append cvc "\t$VLOG -sv -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_mentor_vsim {} {
|
||||
global GRLIB
|
||||
upvar compile_vsim_contents cvc
|
||||
upvar make_vsim_contents mvc
|
||||
|
||||
set cvc [rmvlinebreak $cvc]
|
||||
set compfile [open "compile.vsim" w]
|
||||
puts $compfile $cvc
|
||||
close $compfile
|
||||
|
||||
set temp "vsim:\n"
|
||||
append temp $cvc
|
||||
append temp "\n# Work-around for stupid secureip bug ...\n"
|
||||
append temp "\t@if test -r $GRLIB/lib/tech/secureip/ise/mcb_001.vp && test -r modelsim/secureip; then vlog -quiet -novopt -work secureip $GRLIB/lib/tech/secureip/ise/mcb_*.vp; fi\n"
|
||||
append temp $mvc
|
||||
set mvc $temp
|
||||
set mvc [rmvlinebreak $mvc]
|
||||
set makefile [open "make.vsim" w]
|
||||
puts $makefile $mvc
|
||||
close $makefile
|
||||
return
|
||||
}
|
||||
37
bin/scriptgen/filebuild/snps.tcl
Normal file
37
bin/scriptgen/filebuild/snps.tcl
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
proc snps_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/snps_vcs.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/snps_dc.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/snps_fmref.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/snps_synp.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/snps_simv.tcl"
|
||||
|
||||
create_snps_vcs
|
||||
create_snps_dc
|
||||
create_snps_fmref
|
||||
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_snps_dc $k $kinfo
|
||||
append_lib_snps_vcs $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_snps_simv $f $finfo
|
||||
append_file_snps_dc $f $finfo
|
||||
append_file_snps_synp $f $finfo
|
||||
append_file_snps_fmref $f $finfo
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_snps_dc
|
||||
eof_snps_fmref
|
||||
eof_snps_synp
|
||||
eof_snps_vcs
|
||||
eof_snps_simv
|
||||
}
|
||||
|
||||
snps_create_tool $filetree $fileinfo
|
||||
return
|
||||
102
bin/scriptgen/filebuild/snps_dc.tcl
Normal file
102
bin/scriptgen/filebuild/snps_dc.tcl
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
set compile_dc_contents ""
|
||||
proc create_snps_dc {} {
|
||||
upvar compile_dc_contents cdc
|
||||
append cdc "catch {sh mkdir synopsys}"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_snps_dc {k kinfo} {
|
||||
global SNPS_HOME
|
||||
upvar compile_dc_contents cdc
|
||||
set bn [dict get $kinfo bn]
|
||||
if {[string equal $bn "dware"] } {
|
||||
append cdc "\n#define_design_lib $bn -path $SNPS_HOME/packages/dware/lib/DWARE "
|
||||
} else {
|
||||
append cdc "\ncatch \{sh mkdir synopsys/$bn\} "
|
||||
append cdc "\ndefine_design_lib $bn -path synopsys/$bn "
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_snps_dc {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
global DCVHDL VHDLOPT
|
||||
upvar compile_dc_contents cdc
|
||||
append cdc "\n$DCVHDL $bn $VHDLOPT$f"
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global XDCLIBSKIP XDCDIRSKIP DCSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XDCLIBSKIP $bn] < 0 && [lsearchmatch $XDCDIRSKIP $l] < 0 && [lsearchmatch $DCSKIP $q] < 0 } {
|
||||
global DCVHDL VHDLOPT
|
||||
upvar compile_dc_contents cdc
|
||||
append cdc "\n$DCVHDL $bn $VHDLOPT$f"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global DCVLOG
|
||||
upvar compile_dc_contents cdc
|
||||
append cdc "\n$DCVLOG $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global DCVLOG
|
||||
upvar compile_dc_contents cdc
|
||||
append cdc "\n$DCVLOG $bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_snps_dc {} {
|
||||
upvar compile_dc_contents cdc
|
||||
set dcfile [open "compile.dc" w]
|
||||
puts $dcfile $cdc
|
||||
close $dcfile
|
||||
}
|
||||
|
||||
86
bin/scriptgen/filebuild/snps_fmref.tcl
Normal file
86
bin/scriptgen/filebuild/snps_fmref.tcl
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
set fmref_tcl_contents ""
|
||||
proc create_snps_fmref {} {
|
||||
upvar fmref_tcl_contents ftc
|
||||
append ftc "# Formality script to read reference design"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_snps_fmref {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
global FMVHDL FMVHDLOPT
|
||||
upvar fmref_tcl_contents ftc
|
||||
append ftc "\n$FMVHDL $bn $FMVHDLOPT$f"
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global XDCLIBSKIP XDCDIRSKIP DCSKIP
|
||||
upvar fmref_tcl_contents ftc
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XDCLIBSKIP $bn] < 0 && [lsearchmatch $XDCDIRSKIP $l] < 0 && [lsearchmatch $DCSKIP $q] < 0 } {
|
||||
global FMVHDL FMVHDLOPT
|
||||
append ftc "\n$FMVHDL $bn $FMVHDLOPT$f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global FMVLOG
|
||||
upvar fmref_tcl_contents ftc
|
||||
append ftc "\n$FMVLOG $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global FMVLOG
|
||||
upvar fmref_tcl_contents ftc
|
||||
append ftc "\n$FMVLOG $bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_snps_fmref {} {
|
||||
upvar fmref_tcl_contents ftc
|
||||
set fmfile [open "fmref.tcl" w]
|
||||
puts $fmfile $ftc
|
||||
close $fmfile
|
||||
return
|
||||
}
|
||||
|
||||
125
bin/scriptgen/filebuild/snps_simv.tcl
Normal file
125
bin/scriptgen/filebuild/snps_simv.tcl
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
set compile_simv_contents ""
|
||||
set make_simv_contents ""
|
||||
proc append_file_snps_simv {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
global VHDLAN VHDLANOPT
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
global VHDLAN VHDLANOPT
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global VHDLAN VHDLANOPT
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_simv_contents mvc
|
||||
append mvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
global VLOGAN
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_simv_contents mvc
|
||||
append mvc "\tvlogan -nc -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_simv_contents cvc
|
||||
set k [dict get $finfo k]
|
||||
set l [dict get $finfo l]
|
||||
append cvc "\tvlogan -nc -work $bn +incdir+$k/$l $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global VLOGAN
|
||||
upvar compile_simv_contents cvc
|
||||
set k [dict get $finfo k]
|
||||
set l [dict get $finfo l]
|
||||
append cvc "\tvlogan -nc -sverilog -work $bn +incdir+$k/$l $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
global VHDLAN VHDLANOPT
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_simv_contents mvc
|
||||
append mvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvhdlan -nc $VHDLANOPT -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
global VLOGAN
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
upvar make_simv_contents mvc
|
||||
append mvc "\tvlogan -nc -work $bn $f\n"
|
||||
} else {
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvlogan -nc -work $bn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global VLOGAN
|
||||
upvar compile_simv_contents cvc
|
||||
append cvc "\tvlogan -nc -sverilog -work $bn $f\n"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_snps_simv {} {
|
||||
global GRLIB
|
||||
upvar compile_simv_contents cvc
|
||||
upvar make_simv_contents mvc
|
||||
|
||||
set cvc [rmvlinebreak $cvc]
|
||||
set compfile [open "compile.simv" w]
|
||||
puts $compfile $cvc
|
||||
close $compfile
|
||||
|
||||
set temp "simv:\n"
|
||||
append temp $cvc
|
||||
append temp "\n"
|
||||
append temp $mvc
|
||||
set mvc $temp
|
||||
set mvc [rmvlinebreak $mvc]
|
||||
set makefile [open "make.simv" w]
|
||||
puts $makefile $mvc
|
||||
close $makefile
|
||||
return
|
||||
}
|
||||
67
bin/scriptgen/filebuild/snps_synp.tcl
Normal file
67
bin/scriptgen/filebuild/snps_synp.tcl
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
set compile_synp_contents ""
|
||||
proc append_file_snps_synp {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
global SYNPVHDL VHDLOPT
|
||||
upvar compile_synp_contents csc
|
||||
append csc "$SYNPVHDL $VHDLOPT$bn $f\n"
|
||||
}
|
||||
"vhdlmtie" {
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
global SYNPVHDL VHDLOPT
|
||||
upvar compile_synp_contents csc
|
||||
append csc "$SYNPVHDL $VHDLOPT$bn $f\n"
|
||||
}
|
||||
"vhdldce" {
|
||||
}
|
||||
"vhdlcdse" {
|
||||
}
|
||||
"vhdlxile" {
|
||||
}
|
||||
"vhdlfpro" {
|
||||
}
|
||||
"vhdlprec" {
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global SYNPVHDL VHDLOPT
|
||||
upvar compile_synp_contents csc
|
||||
append csc "$SYNPVHDL $VHDLOPT$bn $f\n"
|
||||
}
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global SYNPVLOG
|
||||
upvar compile_synp_contents csc
|
||||
append csc "$SYNPVLOG $f\n"
|
||||
}
|
||||
}
|
||||
"svlogsyn" {
|
||||
global SYNPVLOG
|
||||
upvar compile_synp_contents csc
|
||||
append csc "$SYNPVLOG -vlog_std sysv $f\n"
|
||||
}
|
||||
"vhdlsim" {
|
||||
}
|
||||
"vlogsim" {
|
||||
}
|
||||
"svlogsim" {
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_snps_synp {} {
|
||||
upvar compile_synp_contents csc
|
||||
set csc [rmvlinebreak $csc]
|
||||
set compfile [open "compile.synp" w]
|
||||
puts $compfile $csc
|
||||
close $compfile
|
||||
}
|
||||
34
bin/scriptgen/filebuild/snps_vcs.tcl
Normal file
34
bin/scriptgen/filebuild/snps_vcs.tcl
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
set libs_do_contents ""
|
||||
set vcs_ini_contents ""
|
||||
proc create_snps_vcs {} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar vcs_ini_contents mic
|
||||
append ldc "mkdir -p vcs"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_snps_vcs {k kinfo} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar vcs_ini_contents mic
|
||||
set bn [dict get $kinfo bn]
|
||||
append ldc "\nmkdir -p vcs/$bn "
|
||||
append mic "\n$bn : vcs/$bn"
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_snps_vcs {} {
|
||||
upvar libs_do_contents ldc
|
||||
upvar vcs_ini_contents mic
|
||||
global GRLIB
|
||||
set libsfile [open "vcs_libs" w]
|
||||
puts $libsfile $ldc
|
||||
close $libsfile
|
||||
set readfile [open "$GRLIB/bin/synopsys_sim.setup" r]
|
||||
set simfile [open "synopsys_sim.setup" w]
|
||||
append mic "\n[read $readfile]"
|
||||
set mic [rmvlinebreak $mic]
|
||||
puts $simfile $mic
|
||||
close $readfile
|
||||
close $simfile
|
||||
return
|
||||
}
|
||||
57
bin/scriptgen/filebuild/xlnx.tcl
Normal file
57
bin/scriptgen/filebuild/xlnx.tcl
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
proc xlnx_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_ise.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_planAhead.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_top.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_top_files.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_top_xise.tcl"
|
||||
source "$GRLIB/bin/scriptgen/filebuild/xlnx_vivado.tcl"
|
||||
global VHDLSYNFILES VHDLOPTSYNFILES
|
||||
set tmpnplinfo ""
|
||||
foreach synfile [concat $VHDLOPTSYNFILES $VHDLSYNFILES] {
|
||||
if {[string equal [glob -nocomplain $synfile] $synfile ] } {
|
||||
append tmpnplinfo "SOURCE $synfile\n"
|
||||
}
|
||||
}
|
||||
|
||||
create_xlnx_vivado
|
||||
create_xlnx_planAhead
|
||||
create_xlnx_top
|
||||
create_xlnx_ise
|
||||
create_xlnx_top_xise
|
||||
|
||||
set fend 0
|
||||
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_xlnx_top $k $kinfo
|
||||
append_lib_xlnx_ise $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
set bn [dict get $finfo bn]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] && !$fend } {
|
||||
append_ucf_xlnx_ise
|
||||
set fend 1
|
||||
}
|
||||
append_file_xlnx_ise $f $finfo
|
||||
append_file_xlnx_top $f $finfo
|
||||
append_file_top_xise $f $finfo
|
||||
append_file_top_files $f $finfo
|
||||
append_file_xlnx_vivado $f $finfo
|
||||
append_file_xlnx_planAhead $f $finfo
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_xlnx_ise
|
||||
eof_xlnx_planAhead
|
||||
eof_xlnx_xise
|
||||
eof_xlnx_top
|
||||
eof_xlnx_top_files
|
||||
eof_xlnx_vivado
|
||||
}
|
||||
|
||||
xlnx_create_tool $filetree $fileinfo
|
||||
return
|
||||
157
bin/scriptgen/filebuild/xlnx_ise.tcl
Normal file
157
bin/scriptgen/filebuild/xlnx_ise.tcl
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
set TOP_ise_tcl_contents ""
|
||||
set compile_xst_contents ""
|
||||
proc create_xlnx_ise {} {
|
||||
global TOP PART SPEED PACKAGE ISETECH
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
append titc "project new $TOP.ise\n"
|
||||
append titc "project set family \"$ISETECH\"\n"
|
||||
append titc "project set device $PART\n"
|
||||
append titc "project set speed $SPEED\n"
|
||||
append titc "project set package $PACKAGE\n"
|
||||
append titc "puts \"Adding files to project\"\n"
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_xlnx_ise {k kinfo} {
|
||||
global TOP XSTLIBSKIP
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
set bn [dict get $kinfo bn]
|
||||
if {[lsearch $XSTLIBSKIP $bn] < 0 } {
|
||||
append titc "lib_vhdl new $bn\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_xlnx_ise {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
upvar compile_xst_contents cxc
|
||||
global XSTVHDL VHDLOPT TOP
|
||||
append titc "xfile add \"$f\" -lib_vhdl $bn\n"
|
||||
append titc "puts \"$f\"\n"
|
||||
append cxc "$XSTVHDL $VHDLOPT$bn -ifn $f\n"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
global XSTVHDL VHDLOPT TOP
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
upvar compile_xst_contents cxc
|
||||
append titc "xfile add \"$f\" -lib_vhdl $bn\n"
|
||||
append titc "puts \"$f\"\n"
|
||||
if {![string equal $l "local"] || ![string equal $bn "work"] } {
|
||||
append cxc "$XSTVHDL $VHDLOPT$bn -ifn $f\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
global XSTVLOG TOP
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
upvar compile_xst_contents cxc
|
||||
append titc "xfile add \"$f\" $bn\n"
|
||||
append titc "puts \"$f\"\n"
|
||||
append cxc "$XSTVLOG $bn -ifn $f\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
global XSTVHDL VHDLOPT XSTVLOG TOP
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
upvar compile_xst_contents cxc
|
||||
append titc "xfile add \"$f\" $bn\n"
|
||||
append titc "puts \"$f\"\n"
|
||||
append cxc "$XSTVLOG $bn -ifn $f\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_ucf_xlnx_ise {} {
|
||||
global TOP UCF
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
foreach f $UCF {
|
||||
append titc "xfile add \"$f\"\n"
|
||||
}
|
||||
}
|
||||
|
||||
proc eof_xlnx_ise {} {
|
||||
global TOP SYNPVLOGDEFS XSTOPT NETLISTTECH GRLIB \
|
||||
GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs ISEMAPOPT
|
||||
upvar TOP_ise_tcl_contents titc
|
||||
upvar compile_xst_contents cxc
|
||||
append titc "project set top \"rtl\" \"$TOP\"\n"
|
||||
append titc "project set \"Bus Delimiter\" ()\n"
|
||||
append titc "project set \"FSM Encoding Algorithm\" None\n"
|
||||
append titc "project set \"Pack I/O Registers into IOBs\" yes\n"
|
||||
append titc "project set \"Verilog Macros\" \"$SYNPVLOGDEFS\"\n"
|
||||
append titc "project set \"Other XST Command Line Options\" \"$XSTOPT\" -process \"Synthesize - XST\"\n"
|
||||
append titc "project set \"Allow Unmatched LOC Constraints\" true -process \"Translate\"\n"
|
||||
append titc "project set \"Macro Search Path\" \"$GRLIB/netlists/xilinx/$NETLISTTECH\" -process \"Translate\"\n"
|
||||
append titc "project set \"Pack I/O Registers/Latches into IOBs\" \{$GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs\}\n"
|
||||
append titc "project set \"Other MAP Command Line Options\" \"$ISEMAPOPT\" -process Map\n"
|
||||
append titc "project set \"Drive Done Pin High\" true -process \"Generate Programming File\"\n"
|
||||
append titc "project set \"Create ReadBack Data Files\" true -process \"Generate Programming File\"\n"
|
||||
append titc "project set \"Create Mask File\" true -process \"Generate Programming File\"\n"
|
||||
append titc "project set \"Run Design Rules Checker (DRC)\" false -process \"Generate Programming File\"\n"
|
||||
append titc "project close\n"
|
||||
append titc "exit"
|
||||
set isetclfile [open "$TOP\_ise.tcl" w]
|
||||
puts $isetclfile $titc
|
||||
close $isetclfile
|
||||
set cxc [rmvlinebreak $cxc]
|
||||
set compfile [open "compile.xst" w]
|
||||
puts $compfile $cxc
|
||||
close $compfile
|
||||
}
|
||||
186
bin/scriptgen/filebuild/xlnx_planAhead.tcl
Normal file
186
bin/scriptgen/filebuild/xlnx_planAhead.tcl
Normal file
|
|
@ -0,0 +1,186 @@
|
|||
set planAhead_contents ""
|
||||
proc create_xlnx_planAhead {} {
|
||||
global TOP DESIGN DEVICE PLANAHEAD_SIMSET GRLIB_XIL_PlanAhead_Simulator SIMTOP PROTOBOARD
|
||||
upvar planAhead_contents pc
|
||||
|
||||
file mkdir "planahead"
|
||||
|
||||
append pc "# Xilinx planAhead script for LEON/GRLIB"
|
||||
append pc "\n# Create a new project"
|
||||
append pc "\ncreate_project $DESIGN ./planahead/$DESIGN -part $DEVICE -force"
|
||||
if {![string equal $PLANAHEAD_SIMSET "sim_1"]} {
|
||||
append pc "\ncreate_fileset -simset $PLANAHEAD_SIMSET"
|
||||
}
|
||||
append pc "\n# Board, part and design properties"
|
||||
append pc "\nset_property target_simulator $GRLIB_XIL_PlanAhead_Simulator \[current_project\]"
|
||||
append pc "\nset_property top_lib work \[current_fileset\]"
|
||||
append pc "\nset_property top_arch rtl \[current_fileset\]"
|
||||
append pc "\nset_property top $TOP \[current_fileset\]"
|
||||
append pc "\nset_property target_language VHDL \[current_project\]"
|
||||
if {![string equal $PROTOBOARD ""]} {
|
||||
append pc "\nset_property board $PROTOBOARD \[current_project\]"
|
||||
}
|
||||
append pc "\n# Use manual compile order"
|
||||
append pc "\n#set_property source_mgmt_mode DisplayOnly \[current_project\]"
|
||||
append pc "\n# Disable option: Include all design sources for simulation"
|
||||
append pc "\n#set_property SOURCE_SET \{\} \[get_filesets $PLANAHEAD_SIMSET\]"
|
||||
append pc "\n# Add files for simulation and synthesis"
|
||||
append pc "\nset_property top $SIMTOP \[get_filesets $PLANAHEAD_SIMSET\]"
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_xlnx_planAhead {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
global VIVADOVHDL
|
||||
upvar planAhead_contents pc
|
||||
append pc "\n$VIVADOVHDL $bn $f"
|
||||
append pc "\nset_property file_type VHDL \[get_files $f\]"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOVHDL
|
||||
upvar planAhead_contents pc
|
||||
append pc "\n$VIVADOVHDL $bn $f"
|
||||
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOVLOG
|
||||
upvar planAhead_contents pc
|
||||
append pc "\n$VIVADOVLOG $bn $f"
|
||||
append pc "\nset_property file_type Verilog \[get_files $f\]"
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global VIVADOVLOG
|
||||
upvar planAhead_contents pc
|
||||
append pc "\n$VIVADOVLOG $bn -sv $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOLIBSKIP VIVADODIRSKIP VIVADOSKIP PLANAHEAD_SIMSET
|
||||
upvar planAhead_contents pc
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $VIVADOLIBSKIP $bn] < 0 && [lsearchmatch $VIVADODIRSKIP $l] < 0 && [lsearchmatch $VIVADOSKIP $q] < 0 } {
|
||||
append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
|
||||
append pc "\nset_property library $bn \[get_files $f\]"
|
||||
append pc "\nset_property file_type VHDL \[get_files $f\]"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
set l [dict get $finfo l]
|
||||
global PLANAHEAD_SIMSET
|
||||
upvar planAhead_contents pc
|
||||
append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
|
||||
append pc "\nset_property library $bn \[get_files $f\]"
|
||||
append pc "\nset_property file_type Verilog \[get_files $f\]"
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
global PLANAHEAD_SIMSET
|
||||
upvar planAhead_contents pc
|
||||
append pc "\nadd_files -fileset $PLANAHEAD_SIMSET -norecurse $f"
|
||||
append pc "\nset_property library $bn \[get_files $f\]"
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_xlnx_planAhead {} {
|
||||
global GRLIB NETLISTTECH PLANAHEAD_SIMSET GRLIB_XIL_PlanAhead_sim_verilog_define \
|
||||
UCF_PLANAHEAD PLANAHEAD_SYNTH_STRATEGY PLANAHEAD_IMPL_STRATEGY PLANAHEAD_BITGEN PROTOBOARD \
|
||||
CONFIG_MIG_DDR2 TOP
|
||||
upvar planAhead_contents pc
|
||||
|
||||
append pc "\nadd_files -fileset $PLANAHEAD_SIMSET prom.srec ram.srec"
|
||||
if {![string equal $GRLIB_XIL_PlanAhead_sim_verilog_define ""]} {
|
||||
append pc "\nset_property verilog_define \{$GRLIB_XIL_PlanAhead_sim_verilog_define\} \[get_filesets $PLANAHEAD_SIMSET\]"
|
||||
}
|
||||
if {[file isdirectory $GRLIB/netlists/xilinx/$NETLISTTECH ]} {
|
||||
append pc "\nimport_files $GRLIB/netlists/xilinx/$NETLISTTECH"
|
||||
}
|
||||
if {[string equal $PROTOBOARD "zedBoard"]} {
|
||||
file mkdir "planahead/xps_files"
|
||||
file copy "./edk_files/leon3_zedboard" "planAhead/xps_files/"
|
||||
append pc "\n# Add Leon3 PS Zedboard Design"
|
||||
append pc "\nadd_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp"
|
||||
append pc "\nmake_wrapper -files \[get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp\] -top -fileset \[get_filesets sources_1\] -import"
|
||||
append pc "\nupdate_compile_order -fileset sources_1"
|
||||
}
|
||||
append pc "\n# Read board specific constraints"
|
||||
foreach i $UCF_PLANAHEAD {
|
||||
if {[file exists $i]} {
|
||||
append pc "\nread_ucf $i"
|
||||
}
|
||||
}
|
||||
if {[string equal $CONFIG_MIG_DDR2 "y"]} {
|
||||
if {[file exists "mig/user_design/par/mig.ucf"]} {
|
||||
append pc "\nread_ucf mig/user_design/par/mig.ucf"
|
||||
}
|
||||
|
||||
}
|
||||
# append pc "create_run synth_$(DESIGN) -flow {$(PLANAHEAD_SYNTH_FLOW)} -strategy {$(PLANAHEAD_SYNTH_STRATEGY)}"
|
||||
append pc "\nset_property steps.xst.args.netlist_hierarchy as_optimized \[get_runs synth_1\]"
|
||||
append pc "\nset_property strategy $PLANAHEAD_SYNTH_STRATEGY \[get_runs synth_1\]"
|
||||
set phfile [open "planahead/$TOP\_planAhead.tcl" w]
|
||||
puts $phfile $pc
|
||||
close $phfile
|
||||
|
||||
set pc "# Elaborate design to be able to apply SDC to top level"
|
||||
append pc "\nlaunch_runs -jobs 1 synth_1"
|
||||
append pc "\nwait_on_run -timeout 120 synth_1"
|
||||
append pc "\n# Launch place and route"
|
||||
append pc "\nset_property strategy $PLANAHEAD_IMPL_STRATEGY \[get_runs impl_1\]"
|
||||
append pc "\n#set_property steps.map.args.mt on \[get_runs impl_1\]"
|
||||
append pc "\n#set_property steps.par.args.mt 4 \[get_runs impl_1\]"
|
||||
append pc "\nset_property steps.bitgen.args.m true \[get_runs impl_1\]"
|
||||
if {![string equal $PLANAHEAD_BITGEN ""]} {
|
||||
append pc "\nset_property {steps.bitgen.args.More Options} \{ $PLANAHEAD_BITGEN \} \[get_runs impl_1\]"
|
||||
}
|
||||
append pc "\nlaunch_runs -jobs 1 impl_1 -to_step Bitgen"
|
||||
append pc "\nwait_on_run -timeout 120 impl_1"
|
||||
if {[string equal $PROTOBOARD "zedBoard"]} {
|
||||
append pc "\nexport_hardware \[get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp\] \[get_runs impl_1\] -bitstream"
|
||||
}
|
||||
set phfile [open "planahead/$TOP\_planAhead_run.tcl" w]
|
||||
puts $phfile $pc
|
||||
close $phfile
|
||||
|
||||
set phfile [open "planahead/$TOP\_planAhead_end.tcl" w]
|
||||
puts $phfile "exit\n"
|
||||
close $phfile
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
181
bin/scriptgen/filebuild/xlnx_top.tcl
Normal file
181
bin/scriptgen/filebuild/xlnx_top.tcl
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
set TOP_npl_contents ""
|
||||
set TOP_synplify_npl_contents ""
|
||||
set tmp_npl_contents ""
|
||||
proc create_xlnx_top {} {
|
||||
global TOP TECHNOLOGY PART SPEED PACKAGE GRLIB
|
||||
upvar TOP_npl_contents tnc
|
||||
upvar TOP_synplify_npl_contents tsnc
|
||||
set temp "JDF G\n"
|
||||
append temp "PROJECT $TOP\n"
|
||||
append temp "DESIGN $TOP\n"
|
||||
append temp "DEVFAM $TECHNOLOGY\n"
|
||||
append temp "DEVICE $PART\n"
|
||||
append temp "DEVSPEED $SPEED\n"
|
||||
append temp "DEVPKG $PACKAGE\n"
|
||||
append tnc $temp
|
||||
append tsnc $temp
|
||||
append tnc "DEVTOPLEVELMODULETYPE HDL\n"
|
||||
append tsnc "DEVTOPLEVELMODULETYPE EDIF\n"
|
||||
set readfile [open "$GRLIB/bin/def.npl" r]
|
||||
set readinfo [read $readfile]
|
||||
append tsnc $readinfo
|
||||
set readinfo [rmvlinebreak $readinfo]
|
||||
append tnc $readinfo
|
||||
return
|
||||
}
|
||||
|
||||
proc append_lib_xlnx_top {k kinfo} {
|
||||
upvar tmp_npl_contents mnc
|
||||
global XSTLIBSKIP
|
||||
set bn [dict get $kinfo bn]
|
||||
if {[lsearch $XSTLIBSKIP $bn] < 0 } {
|
||||
append mnc "SUBLIB $bn VhdlLibrary vhdl\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_xlnx_top {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
upvar tmp_npl_contents mnc
|
||||
append mnc "LIBFILE $f $bn vhdl\n"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
upvar tmp_npl_contents mnc
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
set temp "SOURCE $f\n"
|
||||
append temp $mnc
|
||||
set mnc $temp
|
||||
}
|
||||
} else {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
append mnc "LIBFILE $f $bn vhdl\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
upvar tmp_npl_contents mnc
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
append mnc "LIBFILE $f $bn verilog\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
upvar tmp_npl_contents mnc
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
append mnc "LIBFILE $f $bn verilog\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_xlnx_top {} {
|
||||
global TOP UCF TECHNOLOGY GRLIB NETLISTTECH OS
|
||||
upvar TOP_npl_contents tnc
|
||||
upvar TOP_synplify_npl_contents tsnc
|
||||
upvar tmp_npl_contents mnc
|
||||
append tnc "\n"
|
||||
append tnc $mnc
|
||||
append tnc "DEPASSOC $TOP $UCF\n"
|
||||
append tnc "\[Normal\]\n"
|
||||
append tnc "_SynthFsmEncode=xstvhd, $TECHNOLOGY, VHDL.t_synthesize, 1102507235, None\n"
|
||||
append tnc "p_xstBusDelimiter=xstvhd, $TECHNOLOGY, VHDL.t_synthesize, 1102507235, ()\n"
|
||||
append tnc "xilxMapAllowLogicOpt=xstvhd, $TECHNOLOGY, VHDL.t_placeAndRouteDes, 1102861051, True\n"
|
||||
append tnc "xilxMapCoverMode=xstvhd, $TECHNOLOGY, VHDL.t_placeAndRouteDes, 1102861051, Speed\n"
|
||||
append tnc "xilxMapTimingDrivenPacking=xstvhd, $TECHNOLOGY, VHDL.t_placeAndRouteDes, 1102861051, True\n"
|
||||
append tnc "xilxNgdbld_AUL=xstvhd, $TECHNOLOGY, VHDL.t_placeAndRouteDes, 1102861051, True\n"
|
||||
append tnc "xilxNgdbldMacro=xstvhd, $TECHNOLOGY, VHDL.t_ngdbuild, 1105377047, $GRLIB/netlists/xilinx/$NETLISTTECH\n"
|
||||
append tnc "xilxPAReffortLevel=xstvhd, $TECHNOLOGY, VHDL.t_placeAndRouteDes, 1102861051, Medium\n"
|
||||
|
||||
set wininfo [rmvlinebreak [string map {/ \\} $tnc] ]
|
||||
set winfile [open "$TOP\_win32.npl" w]
|
||||
puts $winfile $wininfo
|
||||
close $winfile
|
||||
if {![string equal -nocase [exec uname] "Linux"] && ![string equal -nocase [exec uname] "SunOs"]} {
|
||||
set tnc $wininfo
|
||||
}
|
||||
append tnc "\[STRATEGY-LIST\]\n"
|
||||
append tnc "Normal=True\n"
|
||||
append tnc "DEVSYNTHESISTOOL XST (VHDL/Verilog)"
|
||||
set nplfile [open "$TOP.npl" w]
|
||||
puts $nplfile $tnc
|
||||
close $nplfile
|
||||
|
||||
append tsnc "SOURCE synplify/$TOP.edf\n"
|
||||
append tsnc "DEPASSOC $TOP $UCF\n"
|
||||
append tsnc "\[Normal\]\n"
|
||||
append tsnc "xilxMapAllowLogicOpt=edif, $TECHNOLOGY, EDIF.t_placeAndRouteDes, 1102861051, True\n"
|
||||
append tsnc "xilxMapCoverMode=edif, $TECHNOLOGY, EDIF.t_placeAndRouteDes, 1102861051, Speed\n"
|
||||
append tsnc "xilxNgdbld_AUL=edif, $TECHNOLOGY, EDIF.t_placeAndRouteDes, 1102861051, True\n"
|
||||
append tsnc "xilxPAReffortLevel=edif, $TECHNOLOGY, EDIF.t_placeAndRouteDes, 1102861051, Medium\n"
|
||||
append tsnc "xilxNgdbldMacro=edif, $TECHNOLOGY, EDIF.t_placeAndRouteDes, 1105378344, $GRLIB/netlists/xilinx/$NETLISTTECH\n"
|
||||
|
||||
set wininfo [rmvlinebreak [string map {/ \\} $tsnc] ]
|
||||
set winfile [open "$TOP\_synplify_win32.npl" w]
|
||||
puts $winfile $wininfo
|
||||
close $winfile
|
||||
|
||||
if {![string equal -nocase [exec uname] "Linux"] && ![string equal -nocase [exec uname] "SunOs"]} {
|
||||
set tsnc $wininfo
|
||||
}
|
||||
|
||||
append tsnc "\[STRATEGY-LIST\]\n"
|
||||
append tsnc "Normal=True"
|
||||
set synpfile [open "$TOP\_synplify.npl" w]
|
||||
puts $synpfile $tsnc
|
||||
close $synpfile
|
||||
return
|
||||
}
|
||||
83
bin/scriptgen/filebuild/xlnx_top_files.tcl
Normal file
83
bin/scriptgen/filebuild/xlnx_top_files.tcl
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
set TOP_files_prj_contents ""
|
||||
proc append_file_top_files {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
global TOP
|
||||
upvar TOP_files_prj_contents tfpc
|
||||
append tfpc "\nvhdl $bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP TOP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_files_prj_contents tfpc
|
||||
append tfpc "\nvhdl $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP TOP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_files_prj_contents tfpc
|
||||
append tfpc "\nverilog $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global XSTLIBSKIP XSTDIRSKIP XSTSKIP TOP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_files_prj_contents tfpc
|
||||
append tfpc "\nverilog $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_xlnx_top_files {} {
|
||||
global TOP
|
||||
upvar TOP_files_prj_contents tfpc
|
||||
set prjfile [open "$TOP\_files.prj" w]
|
||||
puts $prjfile $tfpc
|
||||
close $prjfile
|
||||
return
|
||||
}
|
||||
175
bin/scriptgen/filebuild/xlnx_top_xise.tcl
Normal file
175
bin/scriptgen/filebuild/xlnx_top_xise.tcl
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
set TOP_xise_contents ""
|
||||
proc create_xlnx_top_xise {} {
|
||||
upvar TOP_xise_contents txc
|
||||
global GRLIB TOP UCF
|
||||
set readfile [open "$GRLIB/bin/head.xise" r]
|
||||
append txc [read $readfile]
|
||||
append txc " \<files\>\n"
|
||||
foreach u $UCF {
|
||||
append txc " \<file xil_pn:name=\"$u\" xil_pn:type=\"FILE_UCF\"\>\n"
|
||||
append txc " \<association xil_pn:name=\"Implementation\"/\>\n"
|
||||
append txc " \</file\>\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_top_xise {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
global TOP
|
||||
upvar TOP_xise_contents txc
|
||||
append txc " <file xil_pn:name=\"$f\" xil_pn:type=\"FILE_VHDL\">\n"
|
||||
append txc " <association xil_pn:name=\"BehavioralSimulation\"/>\n"
|
||||
append txc " <association xil_pn:name=\"Implementation\"/>\n"
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
append txc " </file>\n"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
global TOP XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_xise_contents txc
|
||||
append txc " <file xil_pn:name=\"$f\" xil_pn:type=\"FILE_VHDL\">\n"
|
||||
append txc " <association xil_pn:name=\"BehavioralSimulation\"/>\n"
|
||||
append txc " <association xil_pn:name=\"Implementation\"/>\n"
|
||||
if {![string equal $l "local"] || ![string equal $bn "work"] } {
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
}
|
||||
append txc " </file>\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
if {[string equal $l "local"] && [string equal $bn "work"] } {
|
||||
} else {
|
||||
global TOP XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_xise_contents txc
|
||||
append txc " <file xil_pn:name=\"$f\" xil_pn:type=\"FILE_VERILOG\">\n"
|
||||
append txc " <association xil_pn:name=\"BehavioralSimulation\"/>\n"
|
||||
append txc " <association xil_pn:name=\"Implementation\"/>\n"
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
append txc " </file>\n"
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global TOP XSTLIBSKIP XSTDIRSKIP XSTSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $XSTLIBSKIP $bn] < 0 && [lsearchmatch $XSTDIRSKIP $l] < 0 && [lsearchmatch $XSTSKIP $q] < 0 } {
|
||||
upvar TOP_xise_contents txc
|
||||
append txc " <file xil_pn:name=\"$f\" xil_pn:type=\"FILE_VERILOG\">\n"
|
||||
append txc " <association xil_pn:name=\"BehavioralSimulation\"/>\n"
|
||||
append txc " <association xil_pn:name=\"Implementation\"/>\n"
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
append txc " </file>\n"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
global TOP
|
||||
upvar TOP_xise_contents txc
|
||||
set l [dict get $finfo l]
|
||||
append txc " <file xil_pn:name=\"$f\" xil_pn:type=\"FILE_VHDL\">\n"
|
||||
append txc " <association xil_pn:name=\"BehavioralSimulation\"/>\n"
|
||||
if {![string equal $l "local"] || ![string equal $bn "work"] } {
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
}
|
||||
append txc " </file>\n"
|
||||
return
|
||||
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_xlnx_xise {} {
|
||||
global TOP PART ISE11TECH NETLISTTECH ISEMAPOPT XSTOPT EFFORT \
|
||||
GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs PACKAGE GRLIB_XIL_PN_Simulator \
|
||||
SPEED SIMTOP GRLIB basenames
|
||||
upvar TOP_xise_contents txc
|
||||
append txc " </files>\n"
|
||||
append txc " <properties>\n"
|
||||
append txc " <property xil_pn:name=\"Allow Unmatched LOC Constraints\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Auto Implementation Top\" xil_pn:value=\"false\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Bus Delimiter\" xil_pn:value=\"()\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Constraints Entry\" xil_pn:value=\"Constraints Editor\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Create Mask File\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Create ReadBack Data Files\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Device\" xil_pn:value=\"$PART\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Device Family\" xil_pn:value=\"$ISE11TECH\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Drive Done Pin High\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"FSM Encoding Algorithm\" xil_pn:value=\"None\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Implementation Top\" xil_pn:value=\"Architecture|$TOP|rtl\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Implementation Top Instance Path\" xil_pn:value=\"/$TOP\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Macro Search Path\" xil_pn:value=\"$GRLIB/netlists/xilinx/$NETLISTTECH\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Other Map Command Line Options\" xil_pn:value=\"$ISEMAPOPT\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Other XST Command Line Options\" xil_pn:value=\"$XSTOPT\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Place & Route Effort Level (Overall)\" xil_pn:value=\"$EFFORT\"/>\n"
|
||||
append txc " <property xil_pn:name=\"PROP_DesignName\" xil_pn:value=\"$TOP\"/>\n"
|
||||
append txc " <property xil_pn:name=\"PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Pack I/O Registers into IOBs\" xil_pn:value=\"Yes\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Pack I/O Registers/Latches into IOBs\" xil_pn:value=\"$GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Package\" xil_pn:value=\"$PACKAGE\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Preferred Language\" xil_pn:value=\"VHDL\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Run Design Rules Checker (DRC)\" xil_pn:value=\"false\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Simulator\" xil_pn:value=\"$GRLIB_XIL_PN_Simulator\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Speed Grade\" xil_pn:value=\"$SPEED\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Synthesis Tool\" xil_pn:value=\"XST (VHDL/Verilog)\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Top-Level Source Type\" xil_pn:value=\"HDL\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Verbose Property Persistence\" xil_pn:value=\"false\"/>\n"
|
||||
append txc " <property xil_pn:name=\"Manual Implementation Compile Order\" xil_pn:value=\"true\"/>\n"
|
||||
append txc " <property xil_pn:name=\"PROP_BehavioralSimTop\" xil_pn:value=\"$SIMTOP\"/>\n"
|
||||
append txc " </properties>\n"
|
||||
append txc " <bindings/>\n"
|
||||
append txc " <libraries>\n"
|
||||
foreach bn $basenames {
|
||||
append txc " <library xil_pn:name=\"$bn\"/>\n"
|
||||
}
|
||||
append txc " </libraries>\n"
|
||||
append txc " <partitions>\n"
|
||||
append txc " <partition xil_pn:name=\"/$TOP\"/>\n"
|
||||
append txc " </partitions>\n"
|
||||
append txc "</project>"
|
||||
set xisefile [open "$TOP.xise" w]
|
||||
puts $xisefile $txc
|
||||
close $xisefile
|
||||
return
|
||||
}
|
||||
206
bin/scriptgen/filebuild/xlnx_vivado.tcl
Normal file
206
bin/scriptgen/filebuild/xlnx_vivado.tcl
Normal file
|
|
@ -0,0 +1,206 @@
|
|||
set vivado_contents ""
|
||||
proc create_xlnx_vivado {} {
|
||||
global DESIGN DEVICE VIVADO_SIMSET SIMTOP GRLIB_VIVADO_SOURCE_MGMT_MODE
|
||||
upvar vivado_contents vc
|
||||
|
||||
file mkdir "vivado"
|
||||
|
||||
append vc "# Xilinx Vivado script for LEON/GRLIB"
|
||||
append vc "\n# Create a new project"
|
||||
append vc "\ncreate_project $DESIGN ./vivado/$DESIGN -part $DEVICE -force"
|
||||
if {![string equal $VIVADO_SIMSET "sim_1"]} {
|
||||
append vc "\ncreate_fileset -simset $VIVADO_SIMSET"
|
||||
}
|
||||
if {![string equal $GRLIB_VIVADO_SOURCE_MGMT_MODE ""]} {
|
||||
append vc "\nset_property source_mgmt_mode $GRLIB_VIVADO_SOURCE_MGMT_MODE \[current_project\]"
|
||||
}
|
||||
append vc "\nset_property top $SIMTOP \[get_filesets $VIVADO_SIMSET\]"
|
||||
append vc "\nset_property target_language verilog \[current_project\]"
|
||||
append vc "\n# Add files for simulation and synthesis"
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
proc append_file_xlnx_vivado {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
global VIVADOVHDL
|
||||
upvar vivado_contents vc
|
||||
append vc "\n$VIVADOVHDL $bn $f"
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOVHDL VIVADOLIBSKIP VIVADODIRSKIP VIVADOSKIP
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $VIVADOLIBSKIP $bn] < 0 && [lsearchmatch $VIVADODIRSKIP $l] < 0 && [lsearchmatch $VIVADOSKIP $q] < 0 } {
|
||||
upvar vivado_contents vc
|
||||
append vc "\n$VIVADOVHDL $bn $f"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOVLOG
|
||||
upvar vivado_contents vc
|
||||
append vc "\n$VIVADOVLOG $bn $f"
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
global VIVADOVLOG
|
||||
upvar vivado_contents vc
|
||||
append vc "\n$VIVADOVLOG $bn -sv $f"
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
set l [dict get $finfo l]
|
||||
global VIVADOLIBSKIP VIVADODIRSKIP VIVADOSKIP
|
||||
upvar vivado_contents vc
|
||||
set l [dict get $finfo l]
|
||||
set q [dict get $finfo q]
|
||||
if {[lsearchmatch $VIVADOLIBSKIP $bn] < 0 && [lsearchmatch $VIVADODIRSKIP $l] < 0 && [lsearchmatch $VIVADOSKIP $q] < 0 } {
|
||||
append vc "\nread_vhdl -library $bn $f"
|
||||
append vc "\nset_property used_in_synthesis false \[get_files $f\]"
|
||||
}
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
set l [dict get $finfo l]
|
||||
upvar vivado_contents vc
|
||||
append vc "\nread_verilog -library $bn $f"
|
||||
append vc "\nset_property used_in_synthesis false \[get_files $f\]"
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
proc eof_xlnx_vivado {} {
|
||||
global VIVADO_SIMSET GRLIB_XIL_Vivado_sim_verilog_define XDC TCL VIVADO_UCF \
|
||||
GRLIB_XIL_Vivado_Simulator TOP PROTOBOARD CONFIG_MIG_7SERIES BOARD VIVADO_MIG_AXI \
|
||||
AXI_64 AXI_128 DESIGN CONFIG_GRETH_ENABLE NETLISTTECH GRLIB \
|
||||
VIVADO_SYNTH_FLOW VIVADO_SYNTH_STRATEGY VIVADO_IMPL_STRATEGY
|
||||
upvar vivado_contents vc
|
||||
|
||||
append vc "\nadd_files -fileset $VIVADO_SIMSET prom.srec ram.srec"
|
||||
if {![string equal $GRLIB_XIL_Vivado_sim_verilog_define ""]} {
|
||||
append vc "\nset_property verilog_define {$GRLIB_XIL_Vivado_sim_verilog_define} \[get_filesets $VIVADO_SIMSET\]"
|
||||
}
|
||||
append vc "\n# Read board specific constraints"
|
||||
foreach i $XDC {
|
||||
append vc "\nread_xdc $i"
|
||||
append vc "\nset_property used_in_synthesis true \[get_files $i\]"
|
||||
append vc "\nset_property used_in_implementation true \[get_files $i\]"
|
||||
}
|
||||
foreach i $TCL {
|
||||
append vc "\nsource $i"
|
||||
}
|
||||
foreach i $VIVADO_UCF {
|
||||
append vc "\nimport_files $i"
|
||||
append vc "\nset_property used_in_synthesis true \[get_files $i\]"
|
||||
append vc "\nset_property used_in_implementation true \[get_files $i\]"
|
||||
}
|
||||
append vc "\n# Board, part and design properties"
|
||||
append vc "\nset_property target_simulator $GRLIB_XIL_Vivado_Simulator \[current_project\]"
|
||||
append vc "\nset_property top_lib work \[current_fileset\]"
|
||||
append vc "\nset_property top_arch rtl \[current_fileset\]"
|
||||
append vc "\nset_property top $TOP \[current_fileset\]"
|
||||
if {![string equal $PROTOBOARD ""]} {
|
||||
append vc "\nset_property board_part $PROTOBOARD \[current_project\]"
|
||||
}
|
||||
if {[string equal $CONFIG_MIG_7SERIES "y"]} {
|
||||
if {[string equal $BOARD "digilent-nexys4ddr-xc7a100t"]} {
|
||||
append vc "\nset_property STEPS.WRITE_BITSTREAM.TCL.PRE ../../../../bitstream.tcl \[get_runs impl_1\]"
|
||||
}
|
||||
if {[file exists "$GRLIB/boards/$BOARD/mig.xci"]} {
|
||||
if {![string equal $VIVADO_MIG_AXI ""]} {
|
||||
if {![string equal $AXI_64 ""]} {
|
||||
set files [glob -nocomplain -type f "$GRLIB/boards/$BOARD/axi_64/mig*"]
|
||||
} else {
|
||||
if {![string equal $AXI_128 ""]} {
|
||||
set files [glob -nocomplain -type f "$GRLIB/boards/$BOARD/axi_128/mig*"]
|
||||
} else {
|
||||
set files [glob -nocomplain -type f "$GRLIB/boards/$BOARD/axi/mig*"]
|
||||
}
|
||||
}
|
||||
} else {
|
||||
set files [glob -nocomplain -type f "$GRLIB/boards/$BOARD/mig.*"]
|
||||
}
|
||||
foreach f $files {
|
||||
file copy $f "vivado/"
|
||||
}
|
||||
append vc "\nset_property target_language verilog \[current_project\]"
|
||||
append vc "\nimport_ip -files vivado/mig.xci -name mig"
|
||||
append vc "\n#upgrade_ip \[get_ips mig\]"
|
||||
append vc "\ngenerate_target all \[get_files ./vivado/$DESIGN/$DESIGN.srcs/sources_1/ip/mig/mig.xci\] -force "
|
||||
} else {
|
||||
puts "\n\nWARNING: No MIG 7series IP was found\n\n"
|
||||
}
|
||||
}
|
||||
if {[string equal $CONFIG_GRETH_ENABLE "y"]} {
|
||||
if {[file exists "$GRLIB/boards/$BOARD/sgmii.xci"]} {
|
||||
set files [glob -nocomplain -type f "$GRLIB/boards/$BOARD/sgmii.*"]
|
||||
foreach f $files {
|
||||
file copy $f "vivado/"
|
||||
}
|
||||
append vc "\nset_property target_language verilog \[current_project\]"
|
||||
append vc "\nimport_ip -files vivado/sgmii.xci -name sgmii"
|
||||
append vc "\ngenerate_target all \[get_files ./vivado/$DESIGN/$DESIGN.srcs/sources_1/ip/sgmii/sgmii.xci\] -force "
|
||||
}
|
||||
}
|
||||
if {[file isdirectory "$GRLIB/netlists/xilinx/$NETLISTTECH" ]} {
|
||||
append vc "\nimport_files $GRLIB/netlists/xilinx/$NETLISTTECH"
|
||||
}
|
||||
set vivfile [open "vivado/$TOP\_vivado.tcl" w]
|
||||
puts $vivfile $vc
|
||||
close $vivfile
|
||||
|
||||
set vc "synth_design -directive runtimeoptimized -resource_sharing off -keep_equivalent_registers -no_lc -rtl -name rtl_1"
|
||||
append vc "\nset_property flow {$VIVADO_SYNTH_FLOW} \[get_runs synth_1\]"
|
||||
append vc "\nset_property strategy {$VIVADO_SYNTH_STRATEGY} \[get_runs synth_1\]"
|
||||
append vc "\nlaunch_runs synth_1"
|
||||
append vc "\nwait_on_run -timeout 360 synth_1"
|
||||
append vc "\nget_ips"
|
||||
append vc "\n# Launch place and route"
|
||||
append vc "\nset_property strategy {$VIVADO_IMPL_STRATEGY} \[get_runs impl_1\]"
|
||||
append vc "\nset_property steps.write_bitstream.args.mask_file true \[get_runs impl_1\]"
|
||||
append vc "\nset_msg_config -suppress -id {Drc 23-20}"
|
||||
append vc "\nlaunch_runs impl_1 -to_step write_bitstream"
|
||||
append vc "\nwait_on_run -timeout 360 impl_1"
|
||||
append vc "\n#report_timing_summary -delay_type min_max -path_type full_clock_expanded -report_unconstrained -check_timing_verbose -max_paths 10 -nworst 1 -significant_digits 3 -input_pins -name timing_1 -file ./vivado/$TOP\_post_timing.rpt"
|
||||
append vc "\n#report_drc -file $TOP\_drc_route.rpt"
|
||||
|
||||
set vivfile [open "vivado/$TOP\_vivado_run.tcl" w]
|
||||
puts $vivfile $vc
|
||||
close $vivfile
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
16
bin/scriptgen/main.tcl
Normal file
16
bin/scriptgen/main.tcl
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
if {[info exists ::env(GRLIB)]} {
|
||||
set GRLIB $::env(GRLIB)
|
||||
}
|
||||
|
||||
if {[catch {dict get {}}]} {
|
||||
puts stderr "Error! Script generation terminated.\nBuilt-in tcl command \"dict\" not supported by Tcl version $tcl_version.\nDictionaries are added in Tcl 8.5.\nReasons for having an older tcl version could be if the tclsh provided with ISE is used."
|
||||
close [open "scriptgendone" w]
|
||||
return
|
||||
}
|
||||
|
||||
source "scriptgenwork/tools.tcl"
|
||||
source "scriptgenwork/extrafiles.tcl"
|
||||
|
||||
source "$GRLIB/bin/scriptgen/database.tcl"
|
||||
|
||||
close [open "scriptgendone" w]
|
||||
141
bin/scriptgen/scriptgen_variables.txt
Normal file
141
bin/scriptgen/scriptgen_variables.txt
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
XTECHLIBS
|
||||
GRLIB
|
||||
LIBADD
|
||||
FILEADD
|
||||
EXTRALIBS
|
||||
DIRADD
|
||||
TECHLIBS
|
||||
XLIBSKIP
|
||||
GRLIB_LEON3_VERSION
|
||||
XDIRSKIP
|
||||
GRLIB_CONFIG
|
||||
XFILESKIP
|
||||
VHDLANOPT
|
||||
VLOGANOPT
|
||||
SVLOGANOPT
|
||||
VCOM
|
||||
VHDLOPT
|
||||
VLOG
|
||||
SVLOG
|
||||
SYNPVHDL
|
||||
DCVHDL
|
||||
RTLCVHDL
|
||||
XSTVHDL
|
||||
VIVADOVHDL
|
||||
ACOM
|
||||
NCVHDL
|
||||
XDCLIBSKIP
|
||||
XDCDIRSKIP
|
||||
DCSKIP
|
||||
XSYNPLIBSKIP
|
||||
XSYNPDIRSKIP
|
||||
SYNPSKIP
|
||||
XSTLIBSKIP
|
||||
XSTDIRSKIP
|
||||
XSTSKIP
|
||||
VIVADOLIBSKIP
|
||||
VIVADODIRSKIP
|
||||
VIVADOSKIP
|
||||
GHDLI
|
||||
GHDLIOPT
|
||||
NCVLOG
|
||||
SNPS_HOME
|
||||
TOP
|
||||
SYNPVLOG
|
||||
LIBEROLIBSKIP
|
||||
LIBERODIRSKIP
|
||||
LIBEROSKIP
|
||||
FMVHDL
|
||||
FMVHDLOPT
|
||||
FMVLOG
|
||||
RTLCVLOG
|
||||
XSTVLOG
|
||||
SF2SIMLIB_RIVIERA
|
||||
PLANAHEAD_SIMSET
|
||||
PRECDIRSKIP
|
||||
PRECLIBSKIP
|
||||
PRECSKIP
|
||||
ALOG
|
||||
QUARTUSLIBSKIP
|
||||
QDIRSKIP
|
||||
QUARTUSSKIP
|
||||
PART
|
||||
SPEED
|
||||
PACKAGE
|
||||
ISPPACKAGE
|
||||
LIBERO_PACKAGE
|
||||
DESIGNER_PACKAGE
|
||||
MGCPACKAGE
|
||||
ISPLIB
|
||||
TECHNOLOGY
|
||||
DESIGNER_TECHNOLOGY
|
||||
MGCTECHNOLOGY
|
||||
LIBERO_DIE
|
||||
DESIGNER_VOLTAGE
|
||||
DESIGNER_TEMPR
|
||||
DESIGNER_VOLTRANGE
|
||||
DESIGNER_PINS
|
||||
DESIGNER_PARTR
|
||||
MANUFACTURER
|
||||
MGCPART
|
||||
ISETECH
|
||||
QSF
|
||||
VHDLOPTSYNFILES
|
||||
VHDLSYNFILES
|
||||
UCF
|
||||
GRLIB_SIMULATOR
|
||||
SIMTOP
|
||||
VHDLSIMFILES
|
||||
PRECOPT
|
||||
SYNFREQ
|
||||
ISE11TECH
|
||||
NETLISTTECH
|
||||
XSTOPT
|
||||
EFFORT
|
||||
GRLIB_XIL_PN_Pack_Reg_Latches_into_IOBs
|
||||
QSF_APPEND
|
||||
GRLIB_XIL_PN_Simulator
|
||||
ISEMAPOPT
|
||||
SYNPVLOGDEFS
|
||||
VERILOGSYNFILES
|
||||
VERILOGOPTSYNFILES
|
||||
VERILOGSIMFILES
|
||||
SDCFILE
|
||||
SDC
|
||||
PDC
|
||||
LIBERO_EXTRA_SDC
|
||||
LIBEROPRECOMPLIBDIR
|
||||
DCVLOG
|
||||
VIVADOVLOG
|
||||
DESIGNER_LAYOUT_OPT
|
||||
DESIGNER_RADEXP
|
||||
SDC_EXTRA
|
||||
PDC_EXTRA
|
||||
DESIGNER_PART
|
||||
DESIGNER_PACKAGE
|
||||
DESIGN
|
||||
DEVICE
|
||||
GRLIB_XIL_PlanAhead_Simulator
|
||||
PROTOBOARD
|
||||
CONFIG_MIG_DDR2
|
||||
UCF_PLANAHEAD
|
||||
PLANAHEAD_BITGEN
|
||||
GRLIB_XIL_PlanAhead_sim_verilog_define
|
||||
PLANAHEAD_SYNTH_STRATEGY
|
||||
PLANAHEAD_IMPL_STRATEGY
|
||||
GRLIB_XIL_Vivado_sim_verilog_define
|
||||
XDC
|
||||
TCL
|
||||
VIVADO_UCF
|
||||
GRLIB_XIL_Vivado_Simulator
|
||||
CONFIG_MIG_7SERIES
|
||||
VIVADO_MIG_AXI
|
||||
AXI_64
|
||||
AXI_128
|
||||
CONFIG_GRETH_ENABLE
|
||||
VIVADO_SYNTH_FLOW
|
||||
VIVADO_SYNTH_STRATEGY
|
||||
VIVADO_IMPL_STRATEGY
|
||||
VIVADO_SIMSET
|
||||
GRLIB_VIVADO_SOURCE_MGMT_MODE
|
||||
BOARD
|
||||
12
bin/scriptgen/scriptgencfg-examples/extrafiles.tcl
Normal file
12
bin/scriptgen/scriptgencfg-examples/extrafiles.tcl
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
set filelist [list]
|
||||
lappend filelist "extrafile.vhd"
|
||||
set dir "local"
|
||||
set libdict [dict create]
|
||||
dict set libdict $dir $filelist
|
||||
set lib "$GRLIB/lib/work"
|
||||
set extrafiletree [dict create]
|
||||
dict set extrafiletree $lib $libdict
|
||||
|
||||
set extrafileinfo [dict create]
|
||||
dict set extrafileinfo "$GRLIB/lib/work" [dict create k_real "/home/gaisler/grlib/lib/work" bn "work"]
|
||||
dict set extrafileinfo "extrafile.vhd" [dict create bn "work" f_real "/home/gaisler/grlib/lib/work/local/extrafile.vhd" q "extrafile.vhd" l "local" i "vhdlsyn" k "../../lib/work"]
|
||||
21
bin/scriptgen/scriptgencfg-examples/newtool.tcl
Normal file
21
bin/scriptgen/scriptgencfg-examples/newtool.tcl
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
proc newtool_create_tool {filetree fileinfo} {
|
||||
global GRLIB
|
||||
source "scriptgenwork/filebuild/newtool_example_file.tcl"
|
||||
create_newtool_example_file
|
||||
foreach k [dict keys $filetree] {
|
||||
set ktree [dict get $filetree $k]
|
||||
set kinfo [dict get $fileinfo $k]
|
||||
append_lib_newtool_example_file $k $kinfo
|
||||
foreach l [dict keys $ktree] {
|
||||
set filelist [dict get $ktree $l]
|
||||
foreach f $filelist {
|
||||
set finfo [dict get $fileinfo $f]
|
||||
append_file_newtool_example_file $f $finfo
|
||||
}
|
||||
}
|
||||
}
|
||||
eof_newtool_example_file
|
||||
}
|
||||
|
||||
newtool_create_tool $filetree $fileinfo
|
||||
return
|
||||
71
bin/scriptgen/scriptgencfg-examples/newtool_example_file.tcl
Normal file
71
bin/scriptgen/scriptgencfg-examples/newtool_example_file.tcl
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
set newtool_example_contents ""
|
||||
proc create_newtool_example_file {} {
|
||||
upvar newtool_example_contents nec
|
||||
append nec ""
|
||||
return
|
||||
}
|
||||
proc append_lib_newtool_example_file {k kinfo} {
|
||||
upvar newtool_example_contents nec
|
||||
append nec ""
|
||||
return
|
||||
}
|
||||
proc append_file_newtool_example_file {f finfo} {
|
||||
set i [dict get $finfo i]
|
||||
set bn [dict get $finfo bn]
|
||||
switch $i {
|
||||
"vhdlp1735" {
|
||||
return
|
||||
}
|
||||
"vhdlmtie" {
|
||||
return
|
||||
}
|
||||
"vhdlsynpe" {
|
||||
return
|
||||
}
|
||||
"vhdldce" {
|
||||
return
|
||||
}
|
||||
"vhdlcdse" {
|
||||
return
|
||||
}
|
||||
"vhdlxile" {
|
||||
return
|
||||
}
|
||||
"vhdlfpro" {
|
||||
return
|
||||
}
|
||||
"vhdlprec" {
|
||||
return
|
||||
}
|
||||
"vhdlsyn" {
|
||||
upvar newtool_example_contents nec
|
||||
append nec ""
|
||||
return
|
||||
}
|
||||
"vlogsyn" {
|
||||
return
|
||||
}
|
||||
"svlogsyn" {
|
||||
return
|
||||
}
|
||||
"vhdlsim" {
|
||||
upvar newtool_example_contents nec
|
||||
append nec ""
|
||||
return
|
||||
}
|
||||
"vlogsim" {
|
||||
return
|
||||
}
|
||||
"svlogsim" {
|
||||
return
|
||||
}
|
||||
}
|
||||
return
|
||||
}
|
||||
proc eof_newtool_example_file {} {
|
||||
upvar newtool_example_contents nec
|
||||
set examplefile [open "newtool.example" w]
|
||||
puts $examplefile $nec
|
||||
close $examplefile
|
||||
return
|
||||
}
|
||||
1
bin/scriptgen/scriptgencfg-examples/tools.tcl
Normal file
1
bin/scriptgen/scriptgencfg-examples/tools.tcl
Normal file
|
|
@ -0,0 +1 @@
|
|||
set tools {aldec altera cdns ghdl lattice mentor microsemi snps xlnx newtool}
|
||||
1
bin/scriptgen/scriptgencfg/README.txt
Normal file
1
bin/scriptgen/scriptgencfg/README.txt
Normal file
|
|
@ -0,0 +1 @@
|
|||
See documentation in $GRLIB/bin/scriptgen/README.txt
|
||||
2
bin/scriptgen/scriptgencfg/extrafiles.tcl
Normal file
2
bin/scriptgen/scriptgencfg/extrafiles.tcl
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
set extrafiletree [dict create]
|
||||
set extrafileinfo [dict create]
|
||||
1
bin/scriptgen/scriptgencfg/tools.tcl
Normal file
1
bin/scriptgen/scriptgencfg/tools.tcl
Normal file
|
|
@ -0,0 +1 @@
|
|||
set tools {actel aldec altera cdns ghdl lattice mentor microsemi snps xlnx}
|
||||
64
bin/scriptgen/targets.tcl
Normal file
64
bin/scriptgen/targets.tcl
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
set toolsstring ""
|
||||
|
||||
if {[info exists ::env(TOP)]} {
|
||||
set TOP $::env(TOP)
|
||||
}
|
||||
source "scriptgenwork/tools.tcl"
|
||||
foreach tool $tools {
|
||||
switch $tool {
|
||||
"aldec" {
|
||||
append toolsstring "compile.asim "
|
||||
append toolsstring "make.riviera "
|
||||
append toolsstring "riviera_ws_create.do "
|
||||
continue
|
||||
}
|
||||
"altera" {
|
||||
append toolsstring "$TOP\_quartus.qsf "
|
||||
continue
|
||||
}
|
||||
"cdns" {
|
||||
append toolsstring "compile.ncsim "
|
||||
append toolsstring "compile.rc "
|
||||
continue
|
||||
}
|
||||
"ghdl" {
|
||||
append toolsstring "make.ghdl "
|
||||
continue
|
||||
}
|
||||
"lattice" {
|
||||
append toolsstring "$TOP\.ldf "
|
||||
continue
|
||||
}
|
||||
"mentor" {
|
||||
append toolsstring "compile.vsim "
|
||||
append toolsstring "$TOP\_precision.tcl "
|
||||
append toolsstring "modelsim.ini "
|
||||
append toolsstring "$TOP\_rtl_fpro.fl "
|
||||
continue
|
||||
|
||||
}
|
||||
"microsemi" {
|
||||
append toolsstring "$TOP\_libero.prj "
|
||||
continue
|
||||
}
|
||||
"snps" {
|
||||
append toolsstring "compile.dc "
|
||||
append toolsstring "compile.synp "
|
||||
continue
|
||||
}
|
||||
"xlnx" {
|
||||
append toolsstring "vivado/$TOP\_vivado.tcl "
|
||||
append toolsstring "planahead/$TOP\_planAhead.tcl "
|
||||
append toolsstring "compile.xst "
|
||||
append toolsstring "$TOP.npl "
|
||||
append toolsstring "$TOP\_ise.tcl "
|
||||
append toolsstring "$TOP.xise "
|
||||
continue
|
||||
}
|
||||
}
|
||||
}
|
||||
if {[string length $toolsstring] > 0 } {
|
||||
set toolsstring [string range $toolsstring 0 end-1]
|
||||
}
|
||||
|
||||
puts $toolsstring
|
||||
3
bin/synopsys_sim.setup
Executable file
3
bin/synopsys_sim.setup
Executable file
|
|
@ -0,0 +1,3 @@
|
|||
WORK > work
|
||||
timebase = ps
|
||||
|
||||
26
bin/synplify.prj
Normal file
26
bin/synplify.prj
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
#implementation: "synplify"
|
||||
impl -add synplify
|
||||
|
||||
#device options
|
||||
set_option -technology TECHNOLOGY
|
||||
set_option -part PART
|
||||
set_option -speed_grade SPEED
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -use_fsm_explorer 0
|
||||
set_option -symbolic_fsm_compiler 0
|
||||
set_option -resource_sharing 0
|
||||
|
||||
set_option -write_vhdl 1
|
||||
#set_option -disable_io_insertion 0
|
||||
|
||||
#map options
|
||||
set_option -frequency SYNFREQ
|
||||
|
||||
set_option -top_module TOP
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "synplify/TOP.edf"
|
||||
|
||||
#implementation attributes
|
||||
190
bin/tkconfig/.config
Normal file
190
bin/tkconfig/.config
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
|
||||
#
|
||||
# Synthesis
|
||||
#
|
||||
# CONFIG_SYN_GENERIC is not set
|
||||
# CONFIG_SYN_ATC35 is not set
|
||||
# CONFIG_SYN_ATC25 is not set
|
||||
# CONFIG_SYN_ATC18 is not set
|
||||
# CONFIG_SYN_FS90 is not set
|
||||
# CONFIG_SYN_UMC018 is not set
|
||||
# CONFIG_SYN_TSMC025 is not set
|
||||
# CONFIG_SYN_PROASIC is not set
|
||||
# CONFIG_SYN_AXCEL is not set
|
||||
# CONFIG_SYN_VIRTEX is not set
|
||||
CONFIG_SYN_VIRTEX2=y
|
||||
# CONFIG_SYN_INFER_RAM is not set
|
||||
# CONFIG_SYN_INFER_REGF is not set
|
||||
# CONFIG_SYN_INFER_ROM is not set
|
||||
# CONFIG_SYN_INFER_PCI_PADS is not set
|
||||
CONFIG_SYN_INFER_MULT=y
|
||||
CONFIG_SYN_RFTYPE=y
|
||||
CONFIG_SYN_TRACE_DPRAM=y
|
||||
|
||||
#
|
||||
# Clock generation
|
||||
#
|
||||
# CONFIG_CLK_VIRTEX is not set
|
||||
CONFIG_CLK_VIRTEX2=y
|
||||
# CONFIG_DCM_2_3 is not set
|
||||
# CONFIG_DCM_3_4 is not set
|
||||
# CONFIG_DCM_4_5 is not set
|
||||
CONFIG_DCM_1_1=y
|
||||
# CONFIG_DCM_5_4 is not set
|
||||
# CONFIG_DCM_4_3 is not set
|
||||
# CONFIG_DCM_3_2 is not set
|
||||
# CONFIG_DCM_5_3 is not set
|
||||
# CONFIG_DCM_2_1 is not set
|
||||
# CONFIG_DCM_3_1 is not set
|
||||
# CONFIG_DCM_4_1 is not set
|
||||
# CONFIG_PCI_DLL is not set
|
||||
# CONFIG_PCI_SYSCLK is not set
|
||||
|
||||
#
|
||||
# Processor
|
||||
#
|
||||
|
||||
#
|
||||
# Integer unit
|
||||
#
|
||||
CONFIG_IU_NWINDOWS=8
|
||||
CONFIG_IU_V8MULDIV=y
|
||||
# CONFIG_IU_MUL_LATENCY_1 is not set
|
||||
# CONFIG_IU_MUL_LATENCY_2 is not set
|
||||
CONFIG_IU_MUL_LATENCY_4=y
|
||||
# CONFIG_IU_MUL_LATENCY_5 is not set
|
||||
# CONFIG_IU_MUL_LATENCY_35 is not set
|
||||
# CONFIG_IU_MUL_MAC is not set
|
||||
CONFIG_IU_LDELAY=1
|
||||
CONFIG_IU_FASTJUMP=y
|
||||
CONFIG_IU_ICCHOLD=y
|
||||
CONFIG_IU_FASTDECODE=y
|
||||
CONFIG_IU_WATCHPOINTS=2
|
||||
|
||||
#
|
||||
# Floating-point unit
|
||||
#
|
||||
# CONFIG_FPU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Co-processor
|
||||
#
|
||||
# CONFIG_CP_ENABLE is not set
|
||||
|
||||
#
|
||||
# Cache system
|
||||
#
|
||||
|
||||
#
|
||||
# Instruction cache
|
||||
#
|
||||
CONFIG_ICACHE_ASSO1=y
|
||||
# CONFIG_ICACHE_ASSO2 is not set
|
||||
# CONFIG_ICACHE_ASSO3 is not set
|
||||
# CONFIG_ICACHE_ASSO4 is not set
|
||||
# CONFIG_ICACHE_SZ1 is not set
|
||||
# CONFIG_ICACHE_SZ2 is not set
|
||||
CONFIG_ICACHE_SZ4=y
|
||||
# CONFIG_ICACHE_SZ8 is not set
|
||||
# CONFIG_ICACHE_SZ16 is not set
|
||||
# CONFIG_ICACHE_SZ32 is not set
|
||||
# CONFIG_ICACHE_SZ64 is not set
|
||||
# CONFIG_ICACHE_LZ16 is not set
|
||||
CONFIG_ICACHE_LZ32=y
|
||||
|
||||
#
|
||||
# Data cache
|
||||
#
|
||||
CONFIG_DCACHE_ASSO1=y
|
||||
# CONFIG_DCACHE_ASSO2 is not set
|
||||
# CONFIG_DCACHE_ASSO3 is not set
|
||||
# CONFIG_DCACHE_ASSO4 is not set
|
||||
# CONFIG_DCACHE_SZ1 is not set
|
||||
# CONFIG_DCACHE_SZ2 is not set
|
||||
CONFIG_DCACHE_SZ4=y
|
||||
# CONFIG_DCACHE_SZ8 is not set
|
||||
# CONFIG_DCACHE_SZ16 is not set
|
||||
# CONFIG_DCACHE_SZ32 is not set
|
||||
# CONFIG_DCACHE_SZ64 is not set
|
||||
# CONFIG_DCACHE_LZ16 is not set
|
||||
CONFIG_DCACHE_LZ32=y
|
||||
CONFIG_DCACHE_SNOOP=y
|
||||
CONFIG_DCACHE_SNOOP_SLOW=y
|
||||
# CONFIG_DCACHE_SNOOP_FAST is not set
|
||||
# CONFIG_DCACHE_LRAM is not set
|
||||
|
||||
#
|
||||
# MMU
|
||||
#
|
||||
# CONFIG_MMU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Debug support unit
|
||||
#
|
||||
CONFIG_DSU_ENABLE=y
|
||||
CONFIG_DSU_TRACEBUF=y
|
||||
CONFIG_DSU_MIXED_TRACE=y
|
||||
# CONFIG_DSU_TRACESZ64 is not set
|
||||
# CONFIG_DSU_TRACESZ128 is not set
|
||||
CONFIG_DSU_TRACESZ256=y
|
||||
# CONFIG_DSU_TRACESZ512 is not set
|
||||
# CONFIG_DSU_TRACESZ1024 is not set
|
||||
|
||||
#
|
||||
# AMBA configuration
|
||||
#
|
||||
CONFIG_AHB_DEFMST=0
|
||||
# CONFIG_AHB_SPLIT is not set
|
||||
|
||||
#
|
||||
# Memory controller
|
||||
#
|
||||
# CONFIG_MCTRL_8BIT is not set
|
||||
# CONFIG_MCTRL_16BIT is not set
|
||||
# CONFIG_PERI_WPROT is not set
|
||||
# CONFIG_MCTRL_WFB is not set
|
||||
# CONFIG_MCTRL_5CS is not set
|
||||
CONFIG_MCTRL_SDRAM=y
|
||||
# CONFIG_MCTRL_SDRAM_INVCLK is not set
|
||||
CONFIG_MCTRL_SDRAM_SEPBUS=y
|
||||
|
||||
#
|
||||
# Peripherals
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
# CONFIG_PERI_IRQ2 is not set
|
||||
# CONFIG_PERI_WDOG is not set
|
||||
CONFIG_PERI_AHBSTAT=y
|
||||
# CONFIG_AHBRAM_ENABLE is not set
|
||||
|
||||
#
|
||||
# Ethernet interface
|
||||
#
|
||||
CONFIG_ETH_ENABLE=y
|
||||
CONFIG_ETH_TXFIFO=8
|
||||
CONFIG_ETH_RXFIFO=8
|
||||
CONFIG_ETH_BURST=4
|
||||
|
||||
#
|
||||
# PCI interface
|
||||
#
|
||||
# CONFIG_PCI_ENABLE is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
#
|
||||
CONFIG_BOOT_EXTPROM=y
|
||||
# CONFIG_BOOT_INTPROM is not set
|
||||
# CONFIG_BOOT_MIXPROM is not set
|
||||
|
||||
#
|
||||
# VHDL Debugging
|
||||
#
|
||||
# CONFIG_DEBUG_UART is not set
|
||||
# CONFIG_DEBUG_IURF is not set
|
||||
# CONFIG_DEBUG_NOHALT is not set
|
||||
# CONFIG_DEBUG_PC32 is not set
|
||||
157
bin/tkconfig/.config.old
Normal file
157
bin/tkconfig/.config.old
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
|
||||
#
|
||||
# Synthesis
|
||||
#
|
||||
CONFIG_SYN_GENERIC=y
|
||||
# CONFIG_SYN_ATC35 is not set
|
||||
# CONFIG_SYN_ATC25 is not set
|
||||
# CONFIG_SYN_ATC18 is not set
|
||||
# CONFIG_SYN_FS90 is not set
|
||||
# CONFIG_SYN_UMC018 is not set
|
||||
# CONFIG_SYN_TSMC025 is not set
|
||||
# CONFIG_SYN_PROASIC is not set
|
||||
# CONFIG_SYN_AXCEL is not set
|
||||
# CONFIG_SYN_VIRTEX is not set
|
||||
# CONFIG_SYN_VIRTEX2 is not set
|
||||
CONFIG_SYN_INFER_MULT=y
|
||||
CONFIG_SYN_RFTYPE=y
|
||||
|
||||
#
|
||||
# Clock generation
|
||||
#
|
||||
# CONFIG_PCI_SYSCLK is not set
|
||||
|
||||
#
|
||||
# Processor
|
||||
#
|
||||
|
||||
#
|
||||
# Integer unit
|
||||
#
|
||||
CONFIG_IU_NWINDOWS=8
|
||||
CONFIG_IU_V8MULDIV=y
|
||||
# CONFIG_IU_MUL_LATENCY_1 is not set
|
||||
# CONFIG_IU_MUL_LATENCY_2 is not set
|
||||
CONFIG_IU_MUL_LATENCY_4=y
|
||||
# CONFIG_IU_MUL_LATENCY_5 is not set
|
||||
# CONFIG_IU_MUL_LATENCY_35 is not set
|
||||
CONFIG_IU_MUL_MAC=y
|
||||
CONFIG_IU_LDELAY=1
|
||||
CONFIG_IU_FASTJUMP=y
|
||||
CONFIG_IU_ICCHOLD=y
|
||||
CONFIG_IU_FASTDECODE=y
|
||||
CONFIG_IU_WATCHPOINTS=0
|
||||
|
||||
#
|
||||
# Floating-point unit
|
||||
#
|
||||
# CONFIG_FPU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Co-processor
|
||||
#
|
||||
# CONFIG_CP_ENABLE is not set
|
||||
|
||||
#
|
||||
# Cache system
|
||||
#
|
||||
|
||||
#
|
||||
# Instruction cache
|
||||
#
|
||||
CONFIG_ICACHE_ASSO1=y
|
||||
# CONFIG_ICACHE_ASSO2 is not set
|
||||
# CONFIG_ICACHE_ASSO3 is not set
|
||||
# CONFIG_ICACHE_ASSO4 is not set
|
||||
# CONFIG_ICACHE_SZ1 is not set
|
||||
# CONFIG_ICACHE_SZ2 is not set
|
||||
CONFIG_ICACHE_SZ4=y
|
||||
# CONFIG_ICACHE_SZ8 is not set
|
||||
# CONFIG_ICACHE_SZ16 is not set
|
||||
# CONFIG_ICACHE_SZ32 is not set
|
||||
# CONFIG_ICACHE_SZ64 is not set
|
||||
# CONFIG_ICACHE_LZ16 is not set
|
||||
CONFIG_ICACHE_LZ32=y
|
||||
|
||||
#
|
||||
# Data cache
|
||||
#
|
||||
CONFIG_DCACHE_ASSO1=y
|
||||
# CONFIG_DCACHE_ASSO2 is not set
|
||||
# CONFIG_DCACHE_ASSO3 is not set
|
||||
# CONFIG_DCACHE_ASSO4 is not set
|
||||
# CONFIG_DCACHE_SZ1 is not set
|
||||
# CONFIG_DCACHE_SZ2 is not set
|
||||
CONFIG_DCACHE_SZ4=y
|
||||
# CONFIG_DCACHE_SZ8 is not set
|
||||
# CONFIG_DCACHE_SZ16 is not set
|
||||
# CONFIG_DCACHE_SZ32 is not set
|
||||
# CONFIG_DCACHE_SZ64 is not set
|
||||
# CONFIG_DCACHE_LZ16 is not set
|
||||
CONFIG_DCACHE_LZ32=y
|
||||
# CONFIG_DCACHE_LRAM is not set
|
||||
|
||||
#
|
||||
# MMU
|
||||
#
|
||||
# CONFIG_MMU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Debug support unit
|
||||
#
|
||||
CONFIG_DSU_ENABLE=y
|
||||
# CONFIG_DSU_TRACEBUF is not set
|
||||
|
||||
#
|
||||
# AMBA configuration
|
||||
#
|
||||
CONFIG_AHB_DEFMST=0
|
||||
# CONFIG_AHB_SPLIT is not set
|
||||
|
||||
#
|
||||
# Memory controller
|
||||
#
|
||||
# CONFIG_MCTRL_8BIT is not set
|
||||
# CONFIG_MCTRL_16BIT is not set
|
||||
# CONFIG_PERI_WPROT is not set
|
||||
# CONFIG_MCTRL_WFB is not set
|
||||
# CONFIG_MCTRL_5CS is not set
|
||||
# CONFIG_MCTRL_SDRAM is not set
|
||||
|
||||
#
|
||||
# Peripherals
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
# CONFIG_PERI_IRQ2 is not set
|
||||
# CONFIG_PERI_WDOG is not set
|
||||
# CONFIG_PERI_AHBSTAT is not set
|
||||
# CONFIG_AHBRAM_ENABLE is not set
|
||||
|
||||
#
|
||||
# Ethernet interface
|
||||
#
|
||||
# CONFIG_ETH_ENABLE is not set
|
||||
|
||||
#
|
||||
# PCI interface
|
||||
#
|
||||
# CONFIG_PCI_ENABLE is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
#
|
||||
CONFIG_BOOT_EXTPROM=y
|
||||
# CONFIG_BOOT_INTPROM is not set
|
||||
# CONFIG_BOOT_MIXPROM is not set
|
||||
|
||||
#
|
||||
# VHDL Debugging
|
||||
#
|
||||
# CONFIG_DEBUG_UART is not set
|
||||
# CONFIG_DEBUG_IURF is not set
|
||||
# CONFIG_DEBUG_NOHALT is not set
|
||||
# CONFIG_DEBUG_PC32 is not set
|
||||
157
bin/tkconfig/.null
Normal file
157
bin/tkconfig/.null
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Automatically generated C config: don't edit
|
||||
*/
|
||||
#define AUTOCONF_INCLUDED
|
||||
#define CONFIG_PERI_LCONF 1
|
||||
/*
|
||||
* Synthesis
|
||||
*/
|
||||
#undef CONFIG_SYN_GENERIC
|
||||
#undef CONFIG_SYN_ATC35
|
||||
#undef CONFIG_SYN_ATC25
|
||||
#undef CONFIG_SYN_ATC18
|
||||
#undef CONFIG_SYN_FS90
|
||||
#undef CONFIG_SYN_UMC018
|
||||
#undef CONFIG_SYN_TSMC025
|
||||
#undef CONFIG_SYN_PROASIC
|
||||
#undef CONFIG_SYN_AXCEL
|
||||
#define CONFIG_SYN_VIRTEX 1
|
||||
#undef CONFIG_SYN_VIRTEX2
|
||||
#undef CONFIG_SYN_INFER_RAM
|
||||
#undef CONFIG_SYN_INFER_REGF
|
||||
#undef CONFIG_SYN_INFER_ROM
|
||||
#define CONFIG_SYN_INFER_MULT 1
|
||||
#define CONFIG_SYN_RFTYPE 1
|
||||
#define CONFIG_SYN_TRACE_DPRAM 1
|
||||
/*
|
||||
* Clock generation
|
||||
*/
|
||||
#define CONFIG_CLK_VIRTEX 1
|
||||
#undef CONFIG_CLKDLL_1_2
|
||||
#define CONFIG_CLKDLL_1_1 1
|
||||
#undef CONFIG_CLKDLL_2_1
|
||||
#undef CONFIG_PCI_DLL
|
||||
/*
|
||||
* Processor
|
||||
*/
|
||||
/*
|
||||
* Integer unit
|
||||
*/
|
||||
#define CONFIG_IU_NWINDOWS (8)
|
||||
#undef CONFIG_IU_V8MULDIV
|
||||
#define CONFIG_IU_LDELAY (1)
|
||||
#define CONFIG_IU_FASTJUMP 1
|
||||
#define CONFIG_IU_ICCHOLD 1
|
||||
#define CONFIG_IU_FASTDECODE 1
|
||||
#define CONFIG_IU_WATCHPOINTS (2)
|
||||
#define CONFIG_IU_IMPL 0x0
|
||||
#define CONFIG_IU_VER 0x0
|
||||
/*
|
||||
* Floating-point unit
|
||||
*/
|
||||
#undef CONFIG_FPU_ENABLE
|
||||
/*
|
||||
* Co-processor
|
||||
*/
|
||||
#undef CONFIG_CP_ENABLE
|
||||
/*
|
||||
* Cache system
|
||||
*/
|
||||
/*
|
||||
* Instruction cache
|
||||
*/
|
||||
#undef CONFIG_ICACHE_ASSO1
|
||||
#define CONFIG_ICACHE_ASSO2 1
|
||||
#undef CONFIG_ICACHE_ASSO3
|
||||
#undef CONFIG_ICACHE_ASSO4
|
||||
#undef CONFIG_ICACHE_SZ1
|
||||
#define CONFIG_ICACHE_SZ2 1
|
||||
#undef CONFIG_ICACHE_SZ4
|
||||
#undef CONFIG_ICACHE_SZ8
|
||||
#undef CONFIG_ICACHE_SZ16
|
||||
#undef CONFIG_ICACHE_SZ32
|
||||
#undef CONFIG_ICACHE_SZ64
|
||||
#undef CONFIG_ICACHE_LZ16
|
||||
#define CONFIG_ICACHE_LZ32 1
|
||||
#undef CONFIG_ICACHE_ALGORND
|
||||
#define CONFIG_ICACHE_ALGOLRR 1
|
||||
#undef CONFIG_ICACHE_ALGOLRU
|
||||
#undef CONFIG_ICACHE_LOCK
|
||||
/*
|
||||
* Data cache
|
||||
*/
|
||||
#undef CONFIG_DCACHE_ASSO1
|
||||
#define CONFIG_DCACHE_ASSO2 1
|
||||
#undef CONFIG_DCACHE_ASSO3
|
||||
#undef CONFIG_DCACHE_ASSO4
|
||||
#undef CONFIG_DCACHE_SZ1
|
||||
#define CONFIG_DCACHE_SZ2 1
|
||||
#undef CONFIG_DCACHE_SZ4
|
||||
#undef CONFIG_DCACHE_SZ8
|
||||
#undef CONFIG_DCACHE_SZ16
|
||||
#undef CONFIG_DCACHE_SZ32
|
||||
#undef CONFIG_DCACHE_SZ64
|
||||
#undef CONFIG_DCACHE_LZ16
|
||||
#define CONFIG_DCACHE_LZ32 1
|
||||
#undef CONFIG_DCACHE_ALGORND
|
||||
#define CONFIG_DCACHE_ALGOLRR 1
|
||||
#undef CONFIG_DCACHE_ALGOLRU
|
||||
#undef CONFIG_DCACHE_LOCK
|
||||
#undef CONFIG_DCACHE_SNOOP
|
||||
#undef CONFIG_DCACHE_RFAST
|
||||
#undef CONFIG_DCACHE_WFAST
|
||||
#undef CONFIG_DCACHE_LRAM
|
||||
/*
|
||||
* Debug support unit
|
||||
*/
|
||||
#define CONFIG_DSU_ENABLE 1
|
||||
#define CONFIG_DSU_TRACEBUF 1
|
||||
#undef CONFIG_DSU_MIXED_TRACE
|
||||
#undef CONFIG_DSU_TRACESZ64
|
||||
#define CONFIG_DSU_TRACESZ128 1
|
||||
#undef CONFIG_DSU_TRACESZ256
|
||||
#undef CONFIG_DSU_TRACESZ512
|
||||
#undef CONFIG_DSU_TRACESZ1024
|
||||
/*
|
||||
* AMBA configuration
|
||||
*/
|
||||
#define CONFIG_AHB_DEFMST (0)
|
||||
#undef CONFIG_AHB_SPLIT
|
||||
/*
|
||||
* Memory controller
|
||||
*/
|
||||
#undef CONFIG_MCTRL_8BIT
|
||||
#undef CONFIG_MCTRL_16BIT
|
||||
#undef CONFIG_PERI_WPROT
|
||||
#undef CONFIG_MCTRL_WFB
|
||||
#undef CONFIG_MCTRL_5CS
|
||||
#undef CONFIG_MCTRL_SDRAM
|
||||
/*
|
||||
* Peripherals
|
||||
*/
|
||||
#define CONFIG_PERI_LCONF 1
|
||||
#undef CONFIG_PERI_IRQ2
|
||||
#undef CONFIG_PERI_WDOG
|
||||
#undef CONFIG_PERI_AHBSTAT
|
||||
#undef CONFIG_AHBRAM_ENABLE
|
||||
/*
|
||||
* Ethernet interface
|
||||
*/
|
||||
#undef CONFIG_ETH_ENABLE
|
||||
/*
|
||||
* PCI interface
|
||||
*/
|
||||
#undef CONFIG_PCI_ENABLE
|
||||
/*
|
||||
* Boot options
|
||||
*/
|
||||
#define CONFIG_BOOT_EXTPROM 1
|
||||
#undef CONFIG_BOOT_INTPROM
|
||||
#undef CONFIG_BOOT_MIXPROM
|
||||
/*
|
||||
* VHDL Debugging
|
||||
*/
|
||||
#undef CONFIG_DEBUG_UART
|
||||
#undef CONFIG_DEBUG_IURF
|
||||
#undef CONFIG_DEBUG_NOHALT
|
||||
#undef CONFIG_DEBUG_PC32
|
||||
35
bin/tkconfig/Makefile
Normal file
35
bin/tkconfig/Makefile
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
|
||||
CC=gcc
|
||||
CFLAGS=-g
|
||||
|
||||
all: lconfig.tk
|
||||
|
||||
xconfig: lconfig.tk
|
||||
wish -f lconfig.tk; echo xconfig exited with code $$?;
|
||||
|
||||
wconfig: lconfig.tk
|
||||
cygwish80 -f lconfig.tk
|
||||
|
||||
dep: mkdevice lconfig.tk
|
||||
./mkdevice < .config
|
||||
-cp device.vhd device.v ../leon/
|
||||
|
||||
tkparse: tkparse.o tkcond.o tkgen.o
|
||||
$(CC) tkparse.o tkcond.o tkgen.o -o tkparse
|
||||
|
||||
mkdevice: mkdevice.o
|
||||
$(CC) mkdevice.o -o mkdevice
|
||||
|
||||
lconfig.tk: leon.tk header.tk tail.tk
|
||||
cat header.tk leon.tk tail.tk > lconfig.tk
|
||||
chmod a+x lconfig.tk
|
||||
|
||||
leon.tk : config.in tkparse
|
||||
./tkparse < config.in > leon.tk
|
||||
|
||||
clean:
|
||||
-rm lconfig.tk leon.tk test.tk *.o tkparse mkdevice *.exe device.vhd device.v
|
||||
|
||||
dist-clean: clean
|
||||
-rm .config .config.old
|
||||
cp defconfig .config
|
||||
710
bin/tkconfig/config-language.txt
Normal file
710
bin/tkconfig/config-language.txt
Normal file
|
|
@ -0,0 +1,710 @@
|
|||
Config Language Specification
|
||||
18 October 1999
|
||||
Michael Elizabeth Chastain, <mailto:mec@shout.net>
|
||||
|
||||
|
||||
|
||||
=== Introduction
|
||||
|
||||
Config Language is not 'bash'.
|
||||
|
||||
This document describes Config Language, the Linux Kernel Configuration
|
||||
Language. config.in and Config.in files are written in this language.
|
||||
|
||||
Although it looks, and usually acts, like a subset of the 'sh' language,
|
||||
Config Language has a restricted syntax and different semantics.
|
||||
|
||||
Here is a basic guideline for Config Language programming: use only the
|
||||
programming idioms that you see in existing Config.in files. People often
|
||||
draw on their shell programming experience to invent idioms that look
|
||||
reasonable to shell programmers, but silently fail in Config Language.
|
||||
|
||||
Config Language is not 'bash'.
|
||||
|
||||
|
||||
|
||||
=== Interpreters
|
||||
|
||||
Four different configuration programs read Config Language:
|
||||
|
||||
scripts/Configure make config, make oldconfig
|
||||
scripts/Menuconfig make menuconfig
|
||||
scripts/tkparse make xconfig
|
||||
mconfig ftp.kernel.org/pub/linux/kernel/people/hch/mconfig/
|
||||
|
||||
'Configure' is a bash script which interprets Config.in files by sourcing
|
||||
them. Some of the Config Language commands are native bash commands;
|
||||
simple bash functions implement the rest of the commands.
|
||||
|
||||
'Menuconfig' is another bash script. It scans the input files with a
|
||||
small awk script, builds a shell function for each menu, sources the
|
||||
shell functions that it builds, and then executes the shell functions
|
||||
in a user-driven order. Menuconfig uses 'lxdialog', a back-end utility
|
||||
program, to perform actual screen output. 'lxdialog' is a C program
|
||||
which uses curses.
|
||||
|
||||
'scripts/tkparse' is a C program with an ad hoc parser which translates
|
||||
a Config Language script to a huge TCL/TK program. 'make xconfig'
|
||||
then hands this TCL/TK program to 'wish', which executes it.
|
||||
|
||||
'mconfig' is the next generation of Config Language interpreters. It is a
|
||||
C program with a bison parser which translates a Config Language script
|
||||
into an internal syntax tree and then hands the syntax tree to one of
|
||||
several user-interface front ends.
|
||||
|
||||
|
||||
|
||||
=== Statements
|
||||
|
||||
A Config Language script is a list of statements. There are 21 simple
|
||||
statements; an 'if' statement; menu blocks; and a 'source' statement.
|
||||
|
||||
A '\' at the end of a line marks a line continuation.
|
||||
|
||||
'#' usually introduces a comment, which continues to the end of the line.
|
||||
Lines of the form '# ... is not set', however, are not comments. They
|
||||
are semantically meaningful, and all four config interpreters implement
|
||||
this meaning.
|
||||
|
||||
Newlines are significant. You may not substitute semicolons for newlines.
|
||||
The 'if' statement does accept a semicolon in one position; you may use
|
||||
a newline in that position instead.
|
||||
|
||||
Here are the basic grammar elements.
|
||||
|
||||
A /prompt/ is a single-quoted string or a double-quoted string.
|
||||
If the word is double-quoted, it may not have any $ substitutions.
|
||||
|
||||
A /word/ is a single unquoted word, a single-quoted string, or a
|
||||
double-quoted string. If the word is unquoted or double quoted,
|
||||
then $-substitution will be performed on the word.
|
||||
|
||||
A /symbol/ is a single unquoted word. A symbol must have a name of
|
||||
the form CONFIG_*. scripts/mkdep.c relies on this convention in order
|
||||
to generate dependencies on individual CONFIG_* symbols instead of
|
||||
making one massive dependency on include/linux/autoconf.h.
|
||||
|
||||
A /dep/ is a dependency. Syntactically, it is a /word/. At run
|
||||
time, a /dep/ must evaluate to "y", "m", "n", or "".
|
||||
|
||||
An /expr/ is a bash-like expression using the operators
|
||||
'=', '!=', '-a', '-o', and '!'.
|
||||
|
||||
Here are all the statements:
|
||||
|
||||
Text statements:
|
||||
|
||||
mainmenu_name /prompt/
|
||||
comment /prompt/
|
||||
text /prompt/
|
||||
|
||||
Ask statements:
|
||||
|
||||
bool /prompt/ /symbol/
|
||||
hex /prompt/ /symbol/ /word/
|
||||
int /prompt/ /symbol/ /word/
|
||||
string /prompt/ /symbol/ /word/
|
||||
tristate /prompt/ /symbol/
|
||||
|
||||
Define statements:
|
||||
|
||||
define_bool /symbol/ /word/
|
||||
define_hex /symbol/ /word/
|
||||
define_int /symbol/ /word/
|
||||
define_string /symbol/ /word/
|
||||
define_tristate /symbol/ /word/
|
||||
|
||||
Dependent statements:
|
||||
|
||||
dep_bool /prompt/ /symbol/ /dep/ ...
|
||||
dep_mbool /prompt/ /symbol/ /dep/ ...
|
||||
dep_hex /prompt/ /symbol/ /word/ /dep/ ...
|
||||
dep_int /prompt/ /symbol/ /word/ /dep/ ...
|
||||
dep_string /prompt/ /symbol/ /word/ /dep/ ...
|
||||
dep_tristate /prompt/ /symbol/ /dep/ ...
|
||||
|
||||
Unset statement:
|
||||
|
||||
unset /symbol/ ...
|
||||
|
||||
Choice statements:
|
||||
|
||||
choice /prompt/ /word/ /word/
|
||||
nchoice /prompt/ /symbol/ /prompt/ /symbol/ ...
|
||||
|
||||
If statements:
|
||||
|
||||
if [ /expr/ ] ; then
|
||||
/statement/
|
||||
...
|
||||
fi
|
||||
|
||||
if [ /expr/ ] ; then
|
||||
/statement/
|
||||
...
|
||||
else
|
||||
/statement/
|
||||
...
|
||||
fi
|
||||
|
||||
Menu block:
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment /prompt/
|
||||
/statement/
|
||||
...
|
||||
endmenu
|
||||
|
||||
Source statement:
|
||||
|
||||
source /word/
|
||||
|
||||
|
||||
|
||||
=== mainmenu_name /prompt/
|
||||
|
||||
This verb is a lot less important than it looks. It specifies the top-level
|
||||
name of this Config Language file.
|
||||
|
||||
Configure: ignores this line
|
||||
Menuconfig: ignores this line
|
||||
Xconfig: uses /prompt/ for the label window.
|
||||
mconfig: ignores this line (mconfig does a better job without it).
|
||||
|
||||
Example:
|
||||
|
||||
# arch/sparc/config.in
|
||||
mainmenu_name "Linux/SPARC Kernel Configuration"
|
||||
|
||||
|
||||
|
||||
=== comment /prompt/
|
||||
|
||||
This verb displays its prompt to the user during the configuration process
|
||||
and also echoes it to the output files during output. Note that the
|
||||
prompt, like all prompts, is a quoted string with no dollar substitution.
|
||||
|
||||
The 'comment' verb is not a Config Language comment. It causes the
|
||||
user interface to display text, and it causes output to appear in the
|
||||
output files.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/net/Config.in
|
||||
comment 'CCP compressors for PPP are only built as modules.'
|
||||
|
||||
|
||||
|
||||
=== text /prompt/
|
||||
|
||||
This verb displays the prompt to the user with no adornment whatsoever.
|
||||
It does not echo the prompt to the output file. mconfig uses this verb
|
||||
internally for its help facility.
|
||||
|
||||
Configure: not implemented
|
||||
Menuconfig: not implemented
|
||||
Xconfig: not implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# mconfig internal help text
|
||||
text 'Here are all the mconfig command line options.'
|
||||
|
||||
|
||||
|
||||
=== bool /prompt/ /symbol/
|
||||
|
||||
This verb displays /prompt/ to the user, accepts a value from the user,
|
||||
and assigns that value to /symbol/. The legal input values are "n" and
|
||||
"y".
|
||||
|
||||
Note that the bool verb does not have a default value. People keep
|
||||
trying to write Config Language scripts with a default value for bool,
|
||||
but *all* of the existing language interpreters discard additional values.
|
||||
Feel free to submit a multi-interpreter patch to linux-kbuild if you
|
||||
want to implement this as an enhancement.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# arch/i386/config.in
|
||||
bool 'Symmetric multi-processing support' CONFIG_SMP
|
||||
|
||||
|
||||
|
||||
=== hex /prompt/ /symbol/ /word/
|
||||
|
||||
This verb displays /prompt/ to the user, accepts a value from the user,
|
||||
and assigns that value to /symbol/. Any hexadecimal number is a legal
|
||||
input value. /word/ is the default value.
|
||||
|
||||
The hex verb does not accept range parameters.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/sound/Config.in
|
||||
hex 'I/O base for SB Check from manual of the card' CONFIG_SB_BASE 220
|
||||
|
||||
|
||||
|
||||
=== int /prompt/ /symbol/ /word/
|
||||
|
||||
This verb displays /prompt/ to the user, accepts a value from the user,
|
||||
and assigns that value to /symbol/. /word/ is the default value.
|
||||
Any decimal number is a legal input value.
|
||||
|
||||
The int verb does not accept range parameters.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/char/Config.in
|
||||
int 'Maximum number of Unix98 PTYs in use (0-2048)' \
|
||||
CONFIG_UNIX98_PTY_COUNT 256
|
||||
|
||||
|
||||
|
||||
=== string /prompt/ /symbol/ /word/
|
||||
|
||||
This verb displays /prompt/ to the user, accepts a value from the user,
|
||||
and assigns that value to /symbol/. /word/ is the default value. Legal
|
||||
input values are any ASCII string, except for the characters '"' and '\\'.
|
||||
Configure will trap an input string of "?" to display help.
|
||||
|
||||
The default value is mandatory.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/sound/Config.in
|
||||
string ' Full pathname of DSPxxx.LD firmware file' \
|
||||
CONFIG_PSS_BOOT_FILE /etc/sound/dsp001.ld
|
||||
|
||||
|
||||
|
||||
=== tristate /prompt/ /symbol/
|
||||
|
||||
This verb displays /prompt/ to the user, accepts a value from the user,
|
||||
and assigns that value to /symbol/. Legal values are "n", "m", or "y".
|
||||
|
||||
The value "m" stands for "module"; it indicates that /symbol/ should
|
||||
be built as a kernel module. The value "m" is legal only if the symbol
|
||||
CONFIG_MODULES currently has the value "y".
|
||||
|
||||
The tristate verb does not have a default value.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# fs/Config.in
|
||||
tristate 'NFS filesystem support' CONFIG_NFS_FS
|
||||
|
||||
|
||||
|
||||
=== define_bool /symbol/ /word/
|
||||
|
||||
This verb the value of /word/ to /symbol/. Legal values are "n" or "y".
|
||||
|
||||
For compatibility reasons, the value of "m" is also legal, because it
|
||||
will be a while before define_tristate is implemented everywhere.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# arch/alpha/config.in
|
||||
if [ "$CONFIG_ALPHA_GENERIC" = "y" ]
|
||||
then
|
||||
define_bool CONFIG_PCI y
|
||||
define_bool CONFIG_ALPHA_NEED_ROUNDING_EMULATION y
|
||||
fi
|
||||
|
||||
|
||||
|
||||
=== define_hex /symbol/ /word/
|
||||
|
||||
This verb assigns the value of /word/ to /symbol/. Any hexadecimal
|
||||
number is a legal value.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# Not from the corpus
|
||||
bool 'Specify custom serial port' CONFIG_SERIAL_PORT_CUSTOM
|
||||
if [ "$CONFIG_SERIAL_PORT_CUSTOM" = "y" ]; then
|
||||
hex 'Serial port number' CONFIG_SERIAL_PORT
|
||||
else
|
||||
define_hex CONFIG_SERIAL_PORT 0x3F8
|
||||
fi
|
||||
|
||||
|
||||
|
||||
=== define_int /symbol/ /word/
|
||||
|
||||
This verb assigns /symbol/ the value /word/. Any decimal number is a
|
||||
legal value.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/char/ftape/Config.in
|
||||
define_int CONFIG_FT_ALPHA_CLOCK 0
|
||||
|
||||
|
||||
|
||||
=== define_string /symbol/ /word/
|
||||
|
||||
This verb assigns the value of /word/ to /symbol/. Legal input values
|
||||
are any ASCII string, except for the characters '"' and '\\'.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example
|
||||
|
||||
# Not from the corpus
|
||||
define_string CONFIG_VERSION "2.2.0"
|
||||
|
||||
|
||||
|
||||
=== define_tristate /symbol/ /word/
|
||||
|
||||
This verb assigns the value of /word/ to /symbol/. Legal input values
|
||||
are "n", "m", and "y".
|
||||
|
||||
As soon as this verb is implemented in all interpreters, please use it
|
||||
instead of define_bool to define tristate values. This aids in static
|
||||
type checking.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/video/Config.in
|
||||
if [ "$CONFIG_FB_AMIGA" = "y" ]; then
|
||||
define_tristate CONFIG_FBCON_AFB y
|
||||
define_tristate CONFIG_FBCON_ILBM y
|
||||
else
|
||||
if [ "$CONFIG_FB_AMIGA" = "m" ]; then
|
||||
define_tristate CONFIG_FBCON_AFB m
|
||||
define_tristate CONFIG_FBCON_ILBM m
|
||||
fi
|
||||
fi
|
||||
|
||||
|
||||
|
||||
=== dep_bool /prompt/ /symbol/ /dep/ ...
|
||||
|
||||
This verb evaluates all of the dependencies in the dependency list.
|
||||
Any dependency which has a value of "y" does not restrict the input
|
||||
range. Any dependency which has an empty value is ignored.
|
||||
Any dependency which has a value of "n", or which has some other value,
|
||||
(like "m") restricts the input range to "n". Quoting dependencies is not
|
||||
allowed. Using dependencies with an empty value possible is not
|
||||
recommended. See also dep_mbool below.
|
||||
|
||||
If the input range is restricted to the single choice "n", dep_bool
|
||||
silently assigns "n" to /symbol/. If the input range has more than
|
||||
one choice, dep_bool displays /prompt/ to the user, accepts a value
|
||||
from the user, and assigns that value to /symbol/.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
XConfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/net/Config.in
|
||||
dep_bool 'Aironet 4500/4800 PCI support 'CONFIG_AIRONET4500_PCI $CONFIG_PCI
|
||||
|
||||
Known bugs:
|
||||
- Xconfig does not write "# foo is not set" to .config (as well as
|
||||
"#undef foo" to autoconf.h) if command is disabled by its dependencies.
|
||||
|
||||
|
||||
=== dep_mbool /prompt/ /symbol/ /dep/ ...
|
||||
|
||||
This verb evaluates all of the dependencies in the dependency list.
|
||||
Any dependency which has a value of "y" or "m" does not restrict the
|
||||
input range. Any dependency which has an empty value is ignored.
|
||||
Any dependency which has a value of "n", or which has some other value,
|
||||
restricts the input range to "n". Quoting dependencies is not allowed.
|
||||
Using dependencies with an empty value possible is not recommended.
|
||||
|
||||
If the input range is restricted to the single choice "n", dep_bool
|
||||
silently assigns "n" to /symbol/. If the input range has more than
|
||||
one choice, dep_bool displays /prompt/ to the user, accepts a value
|
||||
from the user, and assigns that value to /symbol/.
|
||||
|
||||
Notice that the only difference between dep_bool and dep_mbool
|
||||
is in the way of treating the "m" value as a dependency.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
XConfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# Not from the corpus
|
||||
dep_mbool 'Packet socket: mmapped IO' CONFIG_PACKET_MMAP $CONFIG_PACKET
|
||||
|
||||
Known bugs:
|
||||
- Xconfig does not write "# foo is not set" to .config (as well as
|
||||
"#undef foo" to autoconf.h) if command is disabled by its dependencies.
|
||||
|
||||
|
||||
=== dep_hex /prompt/ /symbol/ /word/ /dep/ ...
|
||||
=== dep_int /prompt/ /symbol/ /word/ /dep/ ...
|
||||
=== dep_string /prompt/ /symbol/ /word/ /dep/ ...
|
||||
|
||||
I am still thinking about the semantics of these verbs.
|
||||
|
||||
Configure: not implemented
|
||||
Menuconfig: not implemented
|
||||
XConfig: not implemented
|
||||
mconfig: not implemented
|
||||
|
||||
|
||||
|
||||
=== dep_tristate /prompt/ /symbol/ /dep/ ...
|
||||
|
||||
This verb evaluates all of the dependencies in the dependency list.
|
||||
Any dependency which has a value of "y" does not restrict the input range.
|
||||
Any dependency which has a value of "m" restricts the input range to
|
||||
"m" or "n". Any dependency which has an empty value is ignored.
|
||||
Any dependency which has a value of "n", or which has some other value,
|
||||
restricts the input range to "n". Quoting dependencies is not allowed.
|
||||
Using dependencies with an empty value possible is not recommended.
|
||||
|
||||
If the input range is restricted to the single choice "n", dep_tristate
|
||||
silently assigns "n" to /symbol/. If the input range has more than
|
||||
one choice, dep_tristate displays /prompt/ to the user, accepts a value
|
||||
from the user, and assigns that value to /symbol/.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# drivers/char/Config.in
|
||||
dep_tristate 'Parallel printer support' CONFIG_PRINTER $CONFIG_PARPORT
|
||||
|
||||
Known bugs:
|
||||
- Xconfig does not write "# foo is not set" to .config (as well as
|
||||
"#undef foo" to autoconf.h) if command is disabled by its dependencies.
|
||||
|
||||
|
||||
=== unset /symbol/ ...
|
||||
|
||||
This verb assigns the value "" to /symbol/, but does not cause /symbol/
|
||||
to appear in the output. The existence of this verb is a hack; it covers
|
||||
up deeper problems with variable semantics in a random-execution language.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented (with bugs)
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# arch/mips/config.in
|
||||
unset CONFIG_PCI
|
||||
unset CONFIG_MIPS_JAZZ
|
||||
unset CONFIG_VIDEO_G364
|
||||
|
||||
|
||||
|
||||
=== choice /prompt/ /word/ /word/
|
||||
|
||||
This verb implements a choice list or "radio button list" selection.
|
||||
It displays /prompt/ to the user, as well as a group of sub-prompts
|
||||
which have corresponding symbols.
|
||||
|
||||
When the user selects a value, the choice verb sets the corresponding
|
||||
symbol to "y" and sets all the other symbols in the choice list to "n".
|
||||
|
||||
The second argument is a single-quoted or double-quoted word that
|
||||
describes a series of sub-prompts and symbol names. The interpreter
|
||||
breaks up the word at white space boundaries into a list of sub-words.
|
||||
The first sub-word is the first prompt; the second sub-word is the
|
||||
first symbol. The third sub-word is the second prompt; the fourth
|
||||
sub-word is the second symbol. And so on, for all the sub-words.
|
||||
|
||||
The third word is a literal word. Its value must be a unique abbreviation
|
||||
for exactly one of the prompts. The symbol corresponding to this prompt
|
||||
is the default enabled symbol.
|
||||
|
||||
Note that because of the syntax of the choice verb, the sub-prompts
|
||||
may not have spaces in them.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
Example:
|
||||
|
||||
# arch/i386/config.in
|
||||
choice ' PCI access mode' \
|
||||
"BIOS CONFIG_PCI_GOBIOS \
|
||||
Direct CONFIG_PCI_GODIRECT \
|
||||
Any CONFIG_PCI_GOANY" Any
|
||||
|
||||
|
||||
|
||||
=== nchoice /prompt/ /symbol/ /prompt/ /symbol/ ...
|
||||
|
||||
This verb has the same semantics as the choice verb, but with a sensible
|
||||
syntax.
|
||||
|
||||
The first /prompt/ is the master prompt for the entire choice list.
|
||||
|
||||
The first /symbol/ is the default symbol to enable (notice that this
|
||||
is a symbol, not a unique prompt abbreviation).
|
||||
|
||||
The subsequent /prompt/ and /symbol/ pairs are the prompts and symbols
|
||||
for the choice list.
|
||||
|
||||
Configure: not implemented
|
||||
Menuconfig: not implemented
|
||||
XConfig: not implemented
|
||||
mconfig: implemented
|
||||
|
||||
|
||||
|
||||
=== if [ /expr/ ] ; then
|
||||
|
||||
This is a conditional statement, with an optional 'else' clause. You may
|
||||
substitute a newline for the semicolon if you choose.
|
||||
|
||||
/expr/ may contain the following atoms and operators. Note that, unlike
|
||||
shell, you must use double quotes around every atom.
|
||||
|
||||
/atom/:
|
||||
"..." a literal
|
||||
"$..." a variable
|
||||
|
||||
/expr/:
|
||||
/atom/ = /atom/ true if atoms have identical value
|
||||
/atom/ != /atom/ true if atoms have different value
|
||||
|
||||
/expr/:
|
||||
/expr/ -o /expr/ true if either expression is true
|
||||
/expr/ -a /expr/ true if both expressions are true
|
||||
! /expr/ true if expression is not true
|
||||
|
||||
Note that a naked /atom/ is not a valid /expr/. If you try to use it
|
||||
as such:
|
||||
|
||||
# Do not do this.
|
||||
if [ "$CONFIG_EXPERIMENTAL" ]; then
|
||||
bool 'Bogus experimental feature' CONFIG_BOGUS
|
||||
fi
|
||||
|
||||
... then you will be surprised, because CONFIG_EXPERIMENTAL never has a
|
||||
value of the empty string! It is always "y" or "n", and both of these
|
||||
are treated as true (non-empty) by the bash-based interpreters Configure
|
||||
and Menuconfig.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
XConfig: implemented, with bugs
|
||||
mconfig: implemented
|
||||
|
||||
Xconfig has some known bugs, and probably some unknown bugs too:
|
||||
|
||||
- literals with an empty "" value are not properly handled.
|
||||
|
||||
|
||||
|
||||
=== mainmenu_option next_comment
|
||||
|
||||
This verb introduces a new menu. The next statement must have a comment
|
||||
verb. The /prompt/ of that comment verb becomes the title of the menu.
|
||||
(I have no idea why the original designer didn't create a 'menu ...' verb).
|
||||
|
||||
Statements outside the scope of any menu are in the implicit top menu.
|
||||
The title of the top menu comes from a variety of sources, depending on
|
||||
the interpreter.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
|
||||
|
||||
=== endmenu
|
||||
|
||||
This verb closes the scope of a menu.
|
||||
|
||||
Configure: implemented
|
||||
Menuconfig: implemented
|
||||
Xconfig: implemented
|
||||
mconfig: implemented
|
||||
|
||||
|
||||
|
||||
=== source /word/
|
||||
|
||||
This verb interprets the literal /word/ as a filename, and interpolates
|
||||
the contents of that file. The word must be a single unquoted literal
|
||||
word.
|
||||
|
||||
Some interpreters interpret this verb at run time; some interpreters
|
||||
interpret it at parse time.
|
||||
|
||||
Inclusion is textual inclusion, like the C preprocessor #include facility.
|
||||
The source verb does not imply a submenu or any kind of block nesting.
|
||||
|
||||
Configure: implemented (run time)
|
||||
Menuconfig: implemented (parse time)
|
||||
Xconfig: implemented (parse time)
|
||||
mconfig: implemented (parse time)
|
||||
173
bin/tkconfig/config.h
Executable file
173
bin/tkconfig/config.h
Executable file
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* Automatically generated C config: don't edit
|
||||
*/
|
||||
#define AUTOCONF_INCLUDED
|
||||
#define CONFIG_PERI_LCONF 1
|
||||
/*
|
||||
* Synthesis
|
||||
*/
|
||||
#undef CONFIG_SYN_GENERIC
|
||||
#undef CONFIG_SYN_ATC35
|
||||
#undef CONFIG_SYN_ATC25
|
||||
#undef CONFIG_SYN_ATC18
|
||||
#undef CONFIG_SYN_FS90
|
||||
#undef CONFIG_SYN_UMC018
|
||||
#undef CONFIG_SYN_TSMC025
|
||||
#undef CONFIG_SYN_PROASIC
|
||||
#undef CONFIG_SYN_AXCEL
|
||||
#undef CONFIG_SYN_VIRTEX
|
||||
#define CONFIG_SYN_VIRTEX2 1
|
||||
#undef CONFIG_SYN_INFER_RAM
|
||||
#undef CONFIG_SYN_INFER_REGF
|
||||
#undef CONFIG_SYN_INFER_ROM
|
||||
#undef CONFIG_SYN_INFER_PCI_PADS
|
||||
#define CONFIG_SYN_INFER_MULT 1
|
||||
#define CONFIG_SYN_RFTYPE 1
|
||||
#define CONFIG_SYN_TRACE_DPRAM 1
|
||||
/*
|
||||
* Clock generation
|
||||
*/
|
||||
#undef CONFIG_CLK_VIRTEX
|
||||
#define CONFIG_CLK_VIRTEX2 1
|
||||
#undef CONFIG_DCM_2_3
|
||||
#undef CONFIG_DCM_3_4
|
||||
#undef CONFIG_DCM_4_5
|
||||
#define CONFIG_DCM_1_1 1
|
||||
#undef CONFIG_DCM_5_4
|
||||
#undef CONFIG_DCM_4_3
|
||||
#undef CONFIG_DCM_3_2
|
||||
#undef CONFIG_DCM_5_3
|
||||
#undef CONFIG_DCM_2_1
|
||||
#undef CONFIG_DCM_3_1
|
||||
#undef CONFIG_DCM_4_1
|
||||
#undef CONFIG_PCI_DLL
|
||||
#undef CONFIG_PCI_SYSCLK
|
||||
/*
|
||||
* Processor
|
||||
*/
|
||||
/*
|
||||
* Integer unit
|
||||
*/
|
||||
#define CONFIG_IU_NWINDOWS (8)
|
||||
#define CONFIG_IU_V8MULDIV 1
|
||||
#undef CONFIG_IU_MUL_LATENCY_1
|
||||
#undef CONFIG_IU_MUL_LATENCY_2
|
||||
#define CONFIG_IU_MUL_LATENCY_4 1
|
||||
#undef CONFIG_IU_MUL_LATENCY_5
|
||||
#undef CONFIG_IU_MUL_LATENCY_35
|
||||
#undef CONFIG_IU_MUL_MAC
|
||||
#define CONFIG_IU_LDELAY (1)
|
||||
#define CONFIG_IU_FASTJUMP 1
|
||||
#define CONFIG_IU_ICCHOLD 1
|
||||
#define CONFIG_IU_FASTDECODE 1
|
||||
#define CONFIG_IU_WATCHPOINTS (2)
|
||||
/*
|
||||
* Floating-point unit
|
||||
*/
|
||||
#undef CONFIG_FPU_ENABLE
|
||||
/*
|
||||
* Co-processor
|
||||
*/
|
||||
#undef CONFIG_CP_ENABLE
|
||||
/*
|
||||
* Cache system
|
||||
*/
|
||||
/*
|
||||
* Instruction cache
|
||||
*/
|
||||
#define CONFIG_ICACHE_ASSO1 1
|
||||
#undef CONFIG_ICACHE_ASSO2
|
||||
#undef CONFIG_ICACHE_ASSO3
|
||||
#undef CONFIG_ICACHE_ASSO4
|
||||
#undef CONFIG_ICACHE_SZ1
|
||||
#undef CONFIG_ICACHE_SZ2
|
||||
#define CONFIG_ICACHE_SZ4 1
|
||||
#undef CONFIG_ICACHE_SZ8
|
||||
#undef CONFIG_ICACHE_SZ16
|
||||
#undef CONFIG_ICACHE_SZ32
|
||||
#undef CONFIG_ICACHE_SZ64
|
||||
#undef CONFIG_ICACHE_LZ16
|
||||
#define CONFIG_ICACHE_LZ32 1
|
||||
/*
|
||||
* Data cache
|
||||
*/
|
||||
#define CONFIG_DCACHE_ASSO1 1
|
||||
#undef CONFIG_DCACHE_ASSO2
|
||||
#undef CONFIG_DCACHE_ASSO3
|
||||
#undef CONFIG_DCACHE_ASSO4
|
||||
#undef CONFIG_DCACHE_SZ1
|
||||
#undef CONFIG_DCACHE_SZ2
|
||||
#define CONFIG_DCACHE_SZ4 1
|
||||
#undef CONFIG_DCACHE_SZ8
|
||||
#undef CONFIG_DCACHE_SZ16
|
||||
#undef CONFIG_DCACHE_SZ32
|
||||
#undef CONFIG_DCACHE_SZ64
|
||||
#undef CONFIG_DCACHE_LZ16
|
||||
#define CONFIG_DCACHE_LZ32 1
|
||||
#define CONFIG_DCACHE_SNOOP 1
|
||||
#define CONFIG_DCACHE_SNOOP_SLOW 1
|
||||
#undef CONFIG_DCACHE_SNOOP_FAST
|
||||
#undef CONFIG_DCACHE_LRAM
|
||||
/*
|
||||
* MMU
|
||||
*/
|
||||
#undef CONFIG_MMU_ENABLE
|
||||
/*
|
||||
* Debug support unit
|
||||
*/
|
||||
#define CONFIG_DSU_ENABLE 1
|
||||
#define CONFIG_DSU_TRACEBUF 1
|
||||
#define CONFIG_DSU_MIXED_TRACE 1
|
||||
#undef CONFIG_DSU_TRACESZ64
|
||||
#undef CONFIG_DSU_TRACESZ128
|
||||
#define CONFIG_DSU_TRACESZ256 1
|
||||
#undef CONFIG_DSU_TRACESZ512
|
||||
#undef CONFIG_DSU_TRACESZ1024
|
||||
/*
|
||||
* AMBA configuration
|
||||
*/
|
||||
#define CONFIG_AHB_DEFMST (0)
|
||||
#undef CONFIG_AHB_SPLIT
|
||||
/*
|
||||
* Memory controller
|
||||
*/
|
||||
#undef CONFIG_MCTRL_8BIT
|
||||
#undef CONFIG_MCTRL_16BIT
|
||||
#undef CONFIG_PERI_WPROT
|
||||
#undef CONFIG_MCTRL_WFB
|
||||
#undef CONFIG_MCTRL_5CS
|
||||
#define CONFIG_MCTRL_SDRAM 1
|
||||
#undef CONFIG_MCTRL_SDRAM_INVCLK
|
||||
#define CONFIG_MCTRL_SDRAM_SEPBUS 1
|
||||
/*
|
||||
* Peripherals
|
||||
*/
|
||||
#define CONFIG_PERI_LCONF 1
|
||||
#undef CONFIG_PERI_IRQ2
|
||||
#undef CONFIG_PERI_WDOG
|
||||
#define CONFIG_PERI_AHBSTAT 1
|
||||
#undef CONFIG_AHBRAM_ENABLE
|
||||
/*
|
||||
* Ethernet interface
|
||||
*/
|
||||
#define CONFIG_ETH_ENABLE 1
|
||||
#define CONFIG_ETH_TXFIFO (8)
|
||||
#define CONFIG_ETH_RXFIFO (8)
|
||||
#define CONFIG_ETH_BURST (4)
|
||||
/*
|
||||
* PCI interface
|
||||
*/
|
||||
#undef CONFIG_PCI_ENABLE
|
||||
/*
|
||||
* Boot options
|
||||
*/
|
||||
#define CONFIG_BOOT_EXTPROM 1
|
||||
#undef CONFIG_BOOT_INTPROM
|
||||
#undef CONFIG_BOOT_MIXPROM
|
||||
/*
|
||||
* VHDL Debugging
|
||||
*/
|
||||
#undef CONFIG_DEBUG_UART
|
||||
#undef CONFIG_DEBUG_IURF
|
||||
#undef CONFIG_DEBUG_NOHALT
|
||||
#undef CONFIG_DEBUG_PC32
|
||||
702
bin/tkconfig/config.help
Normal file
702
bin/tkconfig/config.help
Normal file
|
|
@ -0,0 +1,702 @@
|
|||
|
||||
Name of configuration
|
||||
CONFIG_CFG_NAME
|
||||
The VHDL name of the created configuration record. Must be a valid
|
||||
VHDL identifier.
|
||||
|
||||
Prompt for target technology
|
||||
CONFIG_SYN_GENERIC
|
||||
Selects the target technology. The following are available:
|
||||
|
||||
- Generic: Generic FPGA or ASIC targets if your synthesis tool
|
||||
is capable of infering RAMs and pads automatically.
|
||||
|
||||
- ATC35: Atmel-Nantes 0.35 um rad-hard CMOS
|
||||
|
||||
- ATC25: Atmel-Nantes 0.25 um rad-hard CMOS
|
||||
|
||||
- ATC18: Atmel-Nantes 0.18 um rad-hard CMOS with Virage ram cells
|
||||
|
||||
- FS90: UMC with Faraday FS90 libraries
|
||||
|
||||
- UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
|
||||
|
||||
- TSMC-0.25: TSMC 0.25 um CMOS
|
||||
|
||||
- Xilinx-Virtex: Xilinx Virtex libraries
|
||||
|
||||
- Xilinx-Virtex2: Xilinx Virtex2 libraries
|
||||
|
||||
- Actel ProAsic and Axellerator FPGAs
|
||||
|
||||
Infer ram
|
||||
CONFIG_SYN_INFER_RAM
|
||||
Say Y here if you want the synthesis tool to infer your
|
||||
RAMs for cache memories and trace buffer. Say N to directly
|
||||
instantiate technology-specific RAM cells from the selected
|
||||
target technology package (tech_xxx.vhd).
|
||||
|
||||
Infer register file
|
||||
CONFIG_SYN_INFER_REGF
|
||||
Say Y here if you want the synthesis tool to infer the RAMS in
|
||||
the register file. Say N to directly instantiate technology-
|
||||
specific RAM cells from the selected target technology package
|
||||
(tech_xxx.vhd).
|
||||
|
||||
Infer rom
|
||||
CONFIG_SYN_INFER_ROM
|
||||
Say Y here if you want the synthesis tool to infer the
|
||||
(optional) internal boot ROM. Say N to directly instantiate
|
||||
technology-specific ROM cells from the selected target
|
||||
technology package (tech_xxx.vhd). Most users should say Y
|
||||
here since only the Virtex package provides support for hard
|
||||
ROM cells, and then only through Coregen.
|
||||
|
||||
Infer pads
|
||||
CONFIG_SYN_INFER_PADS
|
||||
Say Y here if you want the synthesis tool to infer pads.
|
||||
Say N to directly instantiate technology-specific pads from
|
||||
the selected target technology package (tech_xxx.vhd).
|
||||
|
||||
Infer multiplier
|
||||
CONFIG_SYN_INFER_MULT
|
||||
Say Y here if you want the synthesis tool to infer a multiplier
|
||||
for the UMUL/SMUL instructions. Say N to use a structural
|
||||
multiplier provided in multlib.vhd. FPGA targets should say Y
|
||||
here, ASIC targets should say N unless your synthesis tool can
|
||||
infer some really fast multiplier core.
|
||||
|
||||
Use dual-port RAMS for DSU trace buffer
|
||||
CONFIG_SYN_TRACE_DPRAM
|
||||
Say Y here if you want to use dual-port RAMs instead of single-port
|
||||
RAMs for the DSU trace buffer. This will reduce the total number of
|
||||
RAM blocks. Note that the target tech package must have support for
|
||||
DPRAM's, which is currently only implemented for Virtex, ATC25, and
|
||||
TSMC025.
|
||||
|
||||
Improve register file write timing
|
||||
CONFIG_SYN_RFTYPE
|
||||
If you say Y here, the register file write timing will be improved
|
||||
by clocking the write port on the rising edge, providing a whole
|
||||
cycle for write strobe generation. If you say N, both read and write
|
||||
ports will be clocked on the falling edge of the clock, simplifying
|
||||
timing analysis.
|
||||
|
||||
This option is not implemented on all targets. Say Y when possible.
|
||||
|
||||
Use Virtex CLKDLL for clock synchronisation
|
||||
CONFIG_CLK_VIRTEX
|
||||
Valid for all Spartan and Virtex targets. If enabled, the input
|
||||
clock will be re-synchronized using a Virtex CLKDLL macro. This
|
||||
will improve clock-to-output delays and allow scaling the clock
|
||||
with a factor 0.5, 1.0, or 2.0. This option also re-synchronizes
|
||||
the SDRAM clock, allowing the use of the SDRAM controller without
|
||||
the inverted-clock option. For this to work, connect SDCLK to PLLREF.
|
||||
|
||||
WARNING: This option cannot be simulated unless you also compile
|
||||
the VHDL component libraries for the Virtex macro blocks (comes
|
||||
with the Xilinx ISE tool). Also, the input clock must be at
|
||||
least 24 MHz for the CKLDLL to work.
|
||||
|
||||
System clock multiplier
|
||||
CONFIG_CLKDLL_1_2
|
||||
Scale the input clock with a factor of 0.5, 1.0, or 2.0. Useful
|
||||
when the target board has an oscillator with a too high (or low)
|
||||
frequency for your design. The divided clock will be used as the
|
||||
main clock for the whole processor (except PCI and ethernet clocks).
|
||||
|
||||
Use Virtex-II DCM for clock synchronisation
|
||||
CONFIG_CLK_VIRTEX2
|
||||
Valid for Spartan2/Spartan3/Virtex2 targets. If enabled, the input
|
||||
clock will be re-synchronized using a Virtex DCM macro. This
|
||||
will improve clock-to-output delays and allow scaling the clock
|
||||
frequency. This option also re-synchronizes the SDRAM clock,
|
||||
allowing the use of the SDRAM controller without the inverted-clock
|
||||
option. For this to work, connect SDCLK to PLLREF.
|
||||
|
||||
WARNING: This option cannot be simulated unless you also compile
|
||||
the VHDL component libraries for the Virtex macro blocks (comes
|
||||
with the Xilinx ISE tool).
|
||||
|
||||
System clock multiplier
|
||||
CONFIG_DCM_2_3
|
||||
Scale the input clock with a factor of 2/3, 3/4, 1, 4/3, 3/2,
|
||||
2, 3, and 4. Useful when the target board has an oscillator with a
|
||||
too high (or low) frequency for your design. The divided clock will
|
||||
be used as the main clock for the whole processor (except PCI and
|
||||
ethernet clocks). NOTE: the resulting frequency must be at least
|
||||
24 MHz or the DCM might not work (see Virtex-II datasheet).
|
||||
|
||||
Enable CLKDLL for PCI clock
|
||||
CONFIG_PCI_DLL
|
||||
Say Y here to re-synchronize the PCI clock using a
|
||||
Virtex BUFGDLL macro. Will improve PCI clock-to-output
|
||||
delays on the expense of input-setup requirements.
|
||||
|
||||
Use PCI clock system clock
|
||||
CONFIG_PCI_SYSCLK
|
||||
Say Y here to the PCI clock to generate the system clock.
|
||||
The PCI clock can be scaled using the DCM or CLKDLL to
|
||||
generate a suitable processor clock.
|
||||
|
||||
Number of SPARC register windows
|
||||
CONFIG_IU_NWINDOWS
|
||||
The SPARC architecture (and LEON) allows 2 - 32 register windows.
|
||||
However, any number except 8 will require that you modify and
|
||||
recompile your run-time system or kernel. Unless you know what
|
||||
you are doing, use 8.
|
||||
|
||||
SPARC V8 multiply and divide instruction
|
||||
CONFIG_IU_V8MULDIV
|
||||
If you say Y here, the SPARC V8 multiply and divide instructions
|
||||
will be implemented. The instructions are: UMUL, UMULCC, SMUL,
|
||||
SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
|
||||
integer multiplications and divisions, significant performance
|
||||
increase can be achieved. Emulated floating-point operations will
|
||||
also benefit from this option.
|
||||
|
||||
By default, the sparc-rtems-gcc compiler does not emit these
|
||||
instructions and your code must be compiled with -mv8 to see any
|
||||
performance increase. On the other hand, code compiled with -mv8
|
||||
will generate an illegal instruction trap when executed on processors
|
||||
with this option disabled.
|
||||
|
||||
The divider consumes approximately 2 kgates, the size of the
|
||||
multiplier depends on the latency.
|
||||
|
||||
Multiplier latency
|
||||
CONFIG_IU_MUL_LATENCY_1
|
||||
The multiplier used for UMUL/SMUL instructions can be implemented
|
||||
with 1, 2, 4, 5 or 35 cycles latency. Lower latency gives higher
|
||||
multiplication performance, but increases area and might reduce
|
||||
the maximum clock frequency. The best area/timing/performance
|
||||
compromise is usually 4 or 5. A latency of 5 cycles will use the
|
||||
same multiplier (16x16) as for 4 cycles, but with a pipeline register
|
||||
to improve timing.
|
||||
|
||||
Multiplier latency
|
||||
CONFIG_IU_MUL_MAC
|
||||
If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
|
||||
instructions will be enabled. The instructions implement a
|
||||
single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
|
||||
The details of these instructions can be found in the LEON manual,
|
||||
section 2.4. Note that the multiplier must be configured with 4
|
||||
cycles latency for this option to be enabled.
|
||||
|
||||
Load latency
|
||||
CONFIG_IU_LDELAY
|
||||
Defines the pipeline load delay (= pipeline cycles before the data
|
||||
from a load instruction is available for the next instruction).
|
||||
One cycle gives best performance, but might create a critical path
|
||||
on targets with slow (data) cache memories. A 2-cycle delay can
|
||||
improve timing but will reduce performance with about 5 - 8%.
|
||||
All FPGA targets and most ASIC targets do fine with 1.
|
||||
|
||||
Icc interlock
|
||||
CONFIG_IU_ICCHOLD
|
||||
If you say Y here, a pipeline stall cycle will be introduced when
|
||||
an instruction that modifies the condition codes is directly followed
|
||||
by a branch instruction that uses these codes (BICC, TICC). The option
|
||||
reduces the performance with about 5% but significantly improves timing
|
||||
on FPGA targets. Recommendation: say Y on FPGA targets, N on ASIC targets.
|
||||
|
||||
Fast jump address generation
|
||||
CONFIG_IU_FASTJUMP
|
||||
If you say Y here, jump address generation will accelerated by
|
||||
using a separate address adder. Will improve timing on most targets
|
||||
to the cost of approximately 300 gates.
|
||||
|
||||
Fast instruction decoding
|
||||
CONFIG_IU_FASTDECODE
|
||||
If you say Y here, instruction decode timing will be improved by adding
|
||||
some extra parallel logic. Useful when you have a critical path
|
||||
ending at the register file read address ports.
|
||||
|
||||
Register file power saving
|
||||
CONFIG_IU_RFPOW
|
||||
If you say Y here, the read ports of the register file will be disabled
|
||||
when not used in an attempt to save power. Only implemented on TSMC-0.25,
|
||||
UMC-0.18 and UMC-FS90 targets. Might lead to a critical path to the
|
||||
register file read enable signal. If so, say N and the read ports will
|
||||
be permanently enabled. Also say N if saving a few gates feels better
|
||||
than saving a few milli-Watts.
|
||||
|
||||
Hardware watchpoints
|
||||
CONFIG_IU_WATCHPOINTS
|
||||
The processor can have up to 4 hardware watchpoints, allowing to
|
||||
create both data and instruction breakpoints at any memory location,
|
||||
also in PROM. Each watchpoint will use approximately 500 gates.
|
||||
Use 0 to disable the watchpoint function.
|
||||
|
||||
Processor implementation ID
|
||||
CONFIG_IU_IMPL
|
||||
Each SPARC processor has a 4-bit implementation ID hardcoded in the
|
||||
processor status register (%psr). You should not use numbers 0 - 9
|
||||
which are used by existing implementations. The value 10 will be
|
||||
assigned to Gaisler Research use this value unless you have a
|
||||
compelling reason not to. In any case, do NOT use 1 since this
|
||||
number is used by ERC32 and will cause applications compiled with
|
||||
LECCS to fail.
|
||||
|
||||
Processor version ID
|
||||
CONFIG_IU_VER
|
||||
Each SPARC processor has a 4-bit version ID hardcoded in the
|
||||
processor status register (%psr). Use 2 for LEON2.
|
||||
|
||||
Floating-point enable
|
||||
CONFIG_FPU_ENABLE
|
||||
Say Y here to enable the floating-point unit. Note that only the
|
||||
(incomplete) LTH FPU is provided with the LEON VHDL model. The
|
||||
Gaisler GRFPU and the Meiko FPU are commercial cores and must be
|
||||
obtained separately.
|
||||
|
||||
FPU selection
|
||||
CONFIG_FPU_GRFPU
|
||||
Select between Gaisler Research's GRFPU, the Sun Meiko FPU core or
|
||||
the open-source LTH core from Lund's University. The Meiko and GRFPU
|
||||
are fully IEEE-754 compatible and supports all SPARC FPU instructions.
|
||||
The LTH FPU also supports IEEE-754, but does not implement the FMUL,
|
||||
FDIV and FSQRT instructions and cannot (yet) be used for general
|
||||
floating-point code.
|
||||
|
||||
FPU version ID
|
||||
CONFIG_FPU_VER
|
||||
Each SPARC FPU has a 3-bit version ID hardcoded in the FPU status
|
||||
register (%fsr). Has no impact on operation or any (known) software.
|
||||
Use as you like, staying with 0 is safe.
|
||||
|
||||
Co-processor enable
|
||||
CONFIG_CP_ENABLE
|
||||
Say Y here to enable the interface to a (custom) co-processor unit.
|
||||
Unless you actually want to add your own co-processor, say N.
|
||||
|
||||
Co-processor configuration
|
||||
CONFIG_CP_CFG
|
||||
The VHDL name of the co-processor configuration to be used. Should
|
||||
exist in target.vhd.
|
||||
|
||||
Instruction cache associativity
|
||||
CONFIG_ICACHE_ASSO1
|
||||
The instruction cache can be implemented as a multi-set cache with
|
||||
1 - 4 sets. Higher associativity usually increases the cache hit
|
||||
rate and thereby the performance. The downside is higher power
|
||||
consumption and increased gate-count for tag comparators.
|
||||
|
||||
Note that a 1-set cache is effectively a direct-mapped cache.
|
||||
|
||||
Instruction cache set size
|
||||
CONFIG_ICACHE_SZ1
|
||||
The size of each set in the instuction cache (kbytes). Valid values
|
||||
are 1 - 64 in binary steps. Note that the full range is only supported
|
||||
by the generic and virtex2 targets. Most target packages are limited
|
||||
to 2 - 16 kbyte. Large set size gives higher performance but might
|
||||
affect the maximum frequency (on ASIC targets). The total instruction
|
||||
cache size is the number of set multiplied with the set size.
|
||||
|
||||
Instruction cache line size
|
||||
CONFIG_ICACHE_LZ16
|
||||
The instruction cache line size. Can be set to either 16 or 32
|
||||
bytes per line. Instruction caches typically benefit from larger
|
||||
line sizes, but on small caches, it migh be better with 16 bytes/line
|
||||
to limit eviction miss rate.
|
||||
|
||||
Instruction cache replacement algorithm
|
||||
CONFIG_ICACHE_ALGORND
|
||||
Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
|
||||
algorithm selects the set to evict randomly. The least-recently-used
|
||||
(LRR) algorithm evicts the set least recently replaced. The least-
|
||||
recently-used (LRU) algorithm evicts the set least recently accessed.
|
||||
The random algorithm uses a simple 1- or 2-bit counter to select
|
||||
the eviction set and has low area overhead. The LRR scheme uses one
|
||||
extra bit in the tag ram and has therefore also low area overhead.
|
||||
However, the LRR scheme can only be used with 2-set caches. The LRU
|
||||
scheme has typically the best performance but also highest area overhead.
|
||||
A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
|
||||
per line, and a 4-set LRU uses 5 flip-flops per line to store the access
|
||||
history.
|
||||
|
||||
Instruction cache locking
|
||||
CONFIG_ICACHE_LOCK
|
||||
Say Y here to enable cache locking in the instruction cache.
|
||||
Locking can be done on cache-line level, but will increase the
|
||||
width of the tag ram with one bit. If you don't know what
|
||||
locking is good for, it is safe to say N.
|
||||
|
||||
Data cache associativity
|
||||
CONFIG_DCACHE_ASSO1
|
||||
The data cache can be implemented as a multi-set cache with
|
||||
1 - 4 sets. Higher associativity usually increases the cache hit
|
||||
rate and thereby the performance. The downside is higher power
|
||||
consumption and increased gate-count for tag comparators.
|
||||
|
||||
Note that a 1-set cache is effectively a direct-mapped cache.
|
||||
|
||||
Data cache set size
|
||||
CONFIG_DCACHE_SZ1
|
||||
The size of each set in the data cache (kbytes). Valid values are
|
||||
1 - 64 in binary steps. Note that the full range is only supported
|
||||
by the generic and virtex2 targets. Most target packages are limited
|
||||
to 2 - 16 kbyte. A large cache gives higher performance but the
|
||||
data cache is timing critical an a too large setting might affect
|
||||
the maximum frequency (on ASIC targets). The total data cache size
|
||||
is the number of set multiplied with the set size.
|
||||
|
||||
Data cache line size
|
||||
CONFIG_DCACHE_LZ16
|
||||
The data cache line size. Can be set to either 16 or 32 bytes per
|
||||
line. A smaller line size gives better associativity and higher
|
||||
cache hit rate, but requires a larger tag memory.
|
||||
|
||||
Data cache replacement algorithm
|
||||
CONFIG_DCACHE_ALGORND
|
||||
See the explanation for instruction cache replacement algorithm.
|
||||
|
||||
Data cache locking
|
||||
CONFIG_DCACHE_LOCK
|
||||
Say Y here to enable cache locking in the data cache.
|
||||
Locking can be done on cache-line level, but will increase the
|
||||
width of the tag ram with one bit. If you don't know what
|
||||
locking is good for, it is safe to say N.
|
||||
|
||||
Data cache snooping
|
||||
CONFIG_DCACHE_SNOOP
|
||||
Say Y here to enable data cache snooping on the AHB bus. Is only
|
||||
useful if you have additional AHB masters such as the DSU or a
|
||||
target PCI interface. Note that the target technology must support
|
||||
dual-port RAMs for this option to be enabled. Dual-port RAMS are
|
||||
currently supported on Virtex/2, ATC25, ATC18 and TSMC025 targets.
|
||||
|
||||
Data cache snooping implementation
|
||||
CONFIG_DCACHE_SNOOP_SLOW
|
||||
Selects the snooping implementation. Use 'slow' if you don't have
|
||||
AHB slaves in cacheable areas which are capable of supporting
|
||||
zero-waitstates non-sequential write accesses. Otherwise use 'fast'
|
||||
and suffer a few kgates extra area.
|
||||
|
||||
Fast read-data generation
|
||||
CONFIG_DCACHE_RFAST
|
||||
Say Y here to improve the data read timing in multi-set caches.
|
||||
FPGA implementations usually do fine with N, while ASIC
|
||||
implementations tuned for maximum frequency should say Y. Increases
|
||||
the area with about 200 gates per set.
|
||||
|
||||
Fast write-data generation
|
||||
CONFIG_DCACHE_WFAST
|
||||
Say Y here to improve the timing of the data inputs to the data
|
||||
cache data memory in multi-set caches. FPGA implementations
|
||||
usually do fine with N, while ASIC implementations tuned for
|
||||
maximum frequency should say Y. Increases the area with about
|
||||
200 gates per set.
|
||||
|
||||
Local data ram
|
||||
CONFIG_DCACHE_LRAM
|
||||
Say Y here to add a local ram to the data cache controller.
|
||||
Accesses to the ram (load/store) will be performed at 0 waitstates
|
||||
and store data will never be written back to the AHB bus.
|
||||
|
||||
Size of local data ram
|
||||
CONFIG_DCACHE_LRAM_SZ1
|
||||
Defines the size of the local data ram in Kbytes. Note that most
|
||||
technology libraries do not support larger rams than 16 Kbyte.
|
||||
|
||||
Start address of local data ram
|
||||
CONFIG_DCACHE_LRSTART
|
||||
Defines the 8 MSB bits of start address of the local data ram.
|
||||
By default set to 8f (start address = 0x8f000000), but any value
|
||||
(except 0) is possible. Note that the local data ram 'shadows'
|
||||
a 16 Mbyte block of the address space.
|
||||
|
||||
MMU enable
|
||||
CONFIG_MMU_ENABLE
|
||||
Say Y here to enable the Memory Management Unit.
|
||||
|
||||
MMU split icache/dcache table lookaside buffer
|
||||
CONFIG_MMU_COMBINED
|
||||
Select "combined" for a combined icache/dcache table lookaside buffer,
|
||||
"split" for a split icache/dcache table lookaside buffer
|
||||
|
||||
MMU tlb replacement scheme
|
||||
CONFIG_MMU_REPARRAY
|
||||
Select "LRU" to use the "least recently used" algorithm for TLB
|
||||
replacement, or "Increment" for a simple incremental replacement
|
||||
scheme.
|
||||
|
||||
Combined i/dcache tlb
|
||||
CONFIG_MMU_I2
|
||||
Select the number of entries for the instruction TLB, or the
|
||||
combined icache/dcache TLB if such is used.
|
||||
|
||||
Split tlb, dcache
|
||||
CONFIG_MMU_D2
|
||||
Select the number of entries for the dcache TLB.
|
||||
|
||||
8-bit memory support
|
||||
CONFIG_MCTRL_8BIT
|
||||
If you say Y here, the PROM/SRAM memory controller will support
|
||||
8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
|
||||
Say N to save a few hundred gates.
|
||||
|
||||
16-bit memory support
|
||||
CONFIG_MCTRL_16BIT
|
||||
If you say Y here, the PROM/SRAM memory controller will support
|
||||
16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
|
||||
Say N to save a few hundred gates.
|
||||
|
||||
Write strobe feedback
|
||||
CONFIG_MCTRL_WFB
|
||||
If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
|
||||
be used to enable the data bus drivers during write cycles. This
|
||||
will guarantee that the data is still valid on the rising edge of
|
||||
the write strobe. If you say N, the write strobes and the data bus
|
||||
drivers will be clocked on the rising edge, potentially creating
|
||||
a hold time problem in external memory or I/O. However, in all
|
||||
practical cases, there is enough capacitance in the data bus lines
|
||||
to keep the value stable for a few (many?) nano-seconds after the
|
||||
buffers have been disabled, making it safe to say N and remove a
|
||||
combinational path in the netlist that might be difficult to
|
||||
analyze.
|
||||
|
||||
Write strobe feedback
|
||||
CONFIG_MCTRL_5CS
|
||||
If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
|
||||
be enabled. If you don't intend to use it, say N and save some gates.
|
||||
|
||||
SDRAM controller enable
|
||||
CONFIG_MCTRL_SDRAM
|
||||
Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
|
||||
intend to use SDRAM, say N and save about 1 kgates.
|
||||
|
||||
SDRAM controller inverted clock
|
||||
CONFIG_MCTRL_SDRAM_INVCLK
|
||||
If you say Y here, the SDRAM clock will be inverted in respect to the
|
||||
system clock and the SDRAM signals. This will limit the SDRAM frequency
|
||||
to 50/66 MHz, but has the benefit that you will not need a PLL to
|
||||
generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,
|
||||
say N and tell your foundry to balance the SDRAM clock output.
|
||||
|
||||
SDRAM separate address buses
|
||||
CONFIG_MCTRL_SDRAM_SEPBUS
|
||||
Say Y here if your SDRAM is connected through separate address
|
||||
and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
|
||||
board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
|
||||
|
||||
Default AHB master
|
||||
CONFIG_AHB_DEFMST
|
||||
Sets the default AHB master (see AMBA 2.0 specification for definition).
|
||||
Should not be set to a value larger than the number of AHB masters - 1.
|
||||
For highest processor performance, leave it at 0.
|
||||
|
||||
Support AHB split-transactions
|
||||
CONFIG_AHB_SPLIT
|
||||
Say Y here to enable AHB split-transaction support in the AHB arbiter.
|
||||
Unless you actually have an AHB slave that can generate AHB split
|
||||
responses, say N and save some gates. None of the AHB slaves provided
|
||||
with LEON generates split, so N is a safe choice.
|
||||
|
||||
AHB status register enable
|
||||
CONFIG_PERI_AHBSTAT
|
||||
If you want the AHB status register functionality say Y here.
|
||||
The register will catch the address and parameters of AHB transfers
|
||||
that are terminated with an error response. Saying N will save
|
||||
about 500 gates.
|
||||
|
||||
RAM write-protectionenable
|
||||
CONFIG_PERI_WPROT
|
||||
If you want to enable RAM write protection (LEON manual 7.13) say Y here.
|
||||
Otherwise say N and save 1 kgates.
|
||||
|
||||
LEON configuration register
|
||||
CONFIG_PERI_LCONF
|
||||
Enables the LEON configuration register that shows how the model was
|
||||
configured. The register is necessary for the test benches to run, and
|
||||
also needed by applications compiled with LECCS. Always say Y.
|
||||
|
||||
Secondary interrupt controller enable
|
||||
CONFIG_PERI_IRQ2
|
||||
Say Y here to enable the secondary interrupt controller (LEON
|
||||
manual 6.3). Routing of the interrupt sources is done in mcore.vhd.
|
||||
It is safe to say N.
|
||||
|
||||
Secondary interrupt controller configuration
|
||||
CONFIG_PERI_IRQ2_CFG
|
||||
The VHDL name of the secondary interrupt controller configuration
|
||||
to be used. Should exist in target.vhd.
|
||||
|
||||
Watchdog enable
|
||||
CONFIG_PERI_WDOG
|
||||
Say Y here to enable the watchdog functionallity in the timer module.
|
||||
Unless you need a watchdog, say N and save 200 gates.
|
||||
|
||||
On-chip ram
|
||||
CONFIG_AHBRAM_ENABLE
|
||||
Say Y here to add a block on on-chip ram to the AHB bus. The ram
|
||||
will be attached at address 0x60000000.
|
||||
|
||||
On-chip ram size
|
||||
CONFIG_AHBRAM_SZ1
|
||||
Set the size of the on-chip AHB ram. The ram is infered/instantiated
|
||||
as four byte-wide ram slices to allow byte and half-word write
|
||||
accesses. It is therefore essential that the target package can
|
||||
infer byte-wide rams. This is currently supported on the generic,
|
||||
virtex, virtex2, proasic and axellerator targets.
|
||||
|
||||
DSU enable
|
||||
CONFIG_DSU_ENABLE
|
||||
The debug support unit (DSU) allows non-intrusive debugging and tracing
|
||||
of both executed instructions and AHB transfers. If you want to enable
|
||||
the DSU, say Y here and select the configuration below.
|
||||
|
||||
Trace buffer enable
|
||||
CONFIG_DSU_TRACEBUF
|
||||
Say Y to enable the trace buffer. The buffer is not necessary for
|
||||
debugging, only for tracing instructions and data transfers.
|
||||
|
||||
Enable mixed tracing
|
||||
CONFIG_DSU_MIXED_TRACE
|
||||
If you say Y here, simultaneous instruction and AHB tracing will be
|
||||
possible. A N will still allow tracing of both, but not simultaneously.
|
||||
|
||||
Size of trace buffer
|
||||
CONFIG_DSU_TRACESZ64
|
||||
Select the number of entries on the trace buffer. For each entry,
|
||||
16 bytes (128 bits) will be needed. A 128-entry buffer will need
|
||||
2 kbyte.
|
||||
|
||||
PCI interface enable
|
||||
CONFIG_PCI_ENABLE
|
||||
To enable a PCI interface, say Y here.
|
||||
|
||||
PCI interface type
|
||||
CONFIG_PCI_TARGET
|
||||
Three PCI cores are provided with this version of Leon: a simple
|
||||
target-only interface without fifos, a fast target interface with
|
||||
configurable fifos, and a full master-target core with fifos.
|
||||
The simple target-only interface is small and robust, and is suitable
|
||||
to be used for DSU communications via PCI. The other two cores core
|
||||
are suitable when high transfer rates or a master interface are needed.
|
||||
|
||||
PCI trace buffer
|
||||
CONFIG_PCI_TRACE
|
||||
The PCI trace buffer implements a simple on-chip logic analyzer
|
||||
to trace the PCI signals. The PCI AD bus and most control signals
|
||||
are stored in a circular buffer, and can be read out by the DSU
|
||||
or any other AHB master. See the manual for detailed operation.
|
||||
Only available for target technologies with dual-port rams.
|
||||
|
||||
PCI trace buffer depth
|
||||
CONFIG_PCI_TRACE256
|
||||
Select the number of entries in the PCI trace buffer. Each entry
|
||||
will use 6 bytes of on-chip (block) ram.
|
||||
|
||||
PCI FIFO depth
|
||||
CONFIG_PCI_FIFO8
|
||||
The number words in the PCI FIFO buffers in the master-target
|
||||
core. The master interface uses four 33-bit wide FIFOs, while the
|
||||
target interface uses two.
|
||||
|
||||
Ethernet MAC enable
|
||||
CONFIG_ETH_ENABLE
|
||||
Say Y here to enable a Ethernet MAC from OpenCores. The control
|
||||
registers of the MAC will be mapped to 0xb0000000.
|
||||
|
||||
Ethernet MAC transmitt FIFO depth
|
||||
CONFIG_ETH_TXFIFO
|
||||
The number of 32-bit words in the transmitt FIFO. 8 words is a
|
||||
good compromise.
|
||||
|
||||
Ethernet MAC receive FIFO depth
|
||||
CONFIG_ETH_RXFIFO
|
||||
The number of 32-bit words in the receiver FIFO. 8 words is a
|
||||
good compromise.
|
||||
|
||||
Ethernet MAC burts length
|
||||
CONFIG_ETH_BURST
|
||||
The length of the burst on the AHB when moving data to and from
|
||||
the FIFOs. A good compromise is half of the FIFO depth.
|
||||
|
||||
Fault-tolerance enable
|
||||
CONFIG_FT_ENABLE
|
||||
Say Y here to enable the fault-tolerance features in LEON-FT. If you
|
||||
only have access to the the public LGPL model, say N or the model
|
||||
will not compile. If you do have the LEON-FT model, say Y here
|
||||
even if you say N to all other options.
|
||||
|
||||
Boot selection
|
||||
CONFIG_BOOT_EXTPROM
|
||||
The processor can be configured to boot from external memory, internal
|
||||
ROM, or both. The internal ROM contains by default the PMON monitor
|
||||
(LEON manual 11.8). If the 'both' option is selected, boot source will
|
||||
be controlled through PIO[4].
|
||||
|
||||
Default RAM read waitstates
|
||||
CONFIG_BOOT_RWS
|
||||
If booting from internal ROM is selected, the memory controller will
|
||||
automatically initialise the SRAM read waitstates setting with this
|
||||
value (valid range is 0 - 3).
|
||||
|
||||
Default RAM write waitstates
|
||||
CONFIG_BOOT_WWS
|
||||
If booting from internal ROM is selected, the memory controller will
|
||||
automatically initialise the SRAM write waitstates setting with this
|
||||
value (valid range is 0 - 3).
|
||||
|
||||
System clock
|
||||
CONFIG_BOOT_SYSCLK
|
||||
If booting from internal ROM is selected, this value should reflect
|
||||
the system clock frequency. This will allow proper default
|
||||
initialisation of the timer unit and UART baud-rate generation.
|
||||
|
||||
UART baud rate
|
||||
CONFIG_BOOT_BAUDRATE
|
||||
If booting from internal ROM is selected, use this value to
|
||||
automatically set the UART baud-rate.
|
||||
|
||||
Select external baud-rate
|
||||
CONFIG_BOOT_EXTBAUD
|
||||
If you say Y here and booting from internal ROM is selected, the UART
|
||||
baud-rate scaler register will be initialised from PIO[7:0].
|
||||
|
||||
Internal ROM addres bits
|
||||
CONFIG_BOOT_PROMABITS
|
||||
Defines the with of the internal ROM address bus. 11 bits is enough
|
||||
for 2 kbytes.
|
||||
|
||||
UART debugging
|
||||
CONFIG_DEBUG_UART
|
||||
During simulation, the output from the UARTs is printed on the
|
||||
simulator console. Since the ratio between the system clock and
|
||||
UART baud-rate is quite high, simulating UART output will be very
|
||||
slow. If you say Y here, the UARTs will print a character as soon
|
||||
as it is stored in the transmitter data register. The transmitter
|
||||
ready flag will be permanently set, speeding up simulation. However,
|
||||
the output on the UART tx line will be garbled. Has not impact on
|
||||
synthesis, but will cause the LEON test bench to fail.
|
||||
|
||||
IU register tracing
|
||||
CONFIG_DEBUG_IURF
|
||||
If you say Y here, all writes to the integer unit register file will be
|
||||
printed on the simulator console.
|
||||
|
||||
FPU register tracing
|
||||
CONFIG_DEBUG_FPURF
|
||||
If you say Y here, all writes to the floating-point unit register file
|
||||
will be printed on the simulator console.
|
||||
|
||||
Continue on reset trap
|
||||
CONFIG_DEBUG_NOHALT
|
||||
The SPARC standard mandates that when error mode is entered,
|
||||
the processor should be halted. If you say Y here, a reset trap
|
||||
(tt = 0x0) will be take on error mode and the processor will
|
||||
not be halted. Use only for testing, since it will not be
|
||||
possible to stop the processor with this option enabled!
|
||||
|
||||
32-bit program counters
|
||||
CONFIG_DEBUG_PC32
|
||||
Since the LSB 2 bits of the program counters always are zero, they are
|
||||
normally not implemented. If you say Y here, the program counters will
|
||||
be implemented with full 32 bits, making debugging of the VHDL model
|
||||
much easier. Turn of this option for synthesis or you will be wasting
|
||||
area.
|
||||
|
||||
|
||||
|
||||
381
bin/tkconfig/config.in
Normal file
381
bin/tkconfig/config.in
Normal file
|
|
@ -0,0 +1,381 @@
|
|||
#
|
||||
# LEON configuration written in linux configuration language
|
||||
#
|
||||
# Written by Jiri Gaisler, Aeroflex Gaisler
|
||||
#
|
||||
# Comments and bug reports to support@gaisler.com
|
||||
#
|
||||
#
|
||||
|
||||
define_bool CONFIG_PERI_LCONF y
|
||||
|
||||
mainmenu_name "LEON Processor Configuration"
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Synthesis '
|
||||
choice 'Target technology ' \
|
||||
"Generic CONFIG_SYN_GENERIC \
|
||||
Atmel-ATC35 CONFIG_SYN_ATC35 \
|
||||
Atmel-ATC25 CONFIG_SYN_ATC25 \
|
||||
Atmel-ATC18 CONFIG_SYN_ATC18 \
|
||||
UMC-FS90 CONFIG_SYN_FS90 \
|
||||
UMC-0.18 CONFIG_SYN_UMC018 \
|
||||
TSMC-0.25 CONFIG_SYN_TSMC025 \
|
||||
Actel-Proasic CONFIG_SYN_PROASIC \
|
||||
Actel-Axcel CONFIG_SYN_AXCEL \
|
||||
Xilinx-Virtex CONFIG_SYN_VIRTEX \
|
||||
Xilinx-Virtex2 CONFIG_SYN_VIRTEX2" Generic
|
||||
if [ "$CONFIG_SYN_GENERIC" != "y" ]; then
|
||||
bool 'Infer cache and trace buffer RAM' CONFIG_SYN_INFER_RAM
|
||||
bool 'Infer register file' CONFIG_SYN_INFER_REGF
|
||||
if [ "$CONFIG_SYN_VIRTEX" = "y" -o "$CONFIG_SYN_VIRTEX2" = "y"]; then
|
||||
bool 'Infer ROM' CONFIG_SYN_INFER_ROM
|
||||
fi
|
||||
if [ "$CONFIG_SYN_VIRTEX" != "y" -a "$CONFIG_SYN_AXCEL" != "y" \
|
||||
-a "$CONFIG_SYN_VIRTEX2" != "y" -a "$CONFIG_SYN_PROASIC" != "y" ]; then
|
||||
bool 'Infer pads' CONFIG_SYN_INFER_PADS
|
||||
fi
|
||||
if [ "$CONFIG_SYN_AXCEL" != "y" -a "$CONFIG_SYN_PROASIC" != "y" ]; then
|
||||
bool 'Infer PCI pads' CONFIG_SYN_INFER_PCI_PADS
|
||||
fi
|
||||
fi
|
||||
bool 'Infer multiplier' CONFIG_SYN_INFER_MULT
|
||||
if [ "$CONFIG_SYN_GENERIC" = "y" -o "$CONFIG_SYN_VIRTEX" = "y" \
|
||||
-o "$CONFIG_SYN_AXCEL" = "y" -o "$CONFIG_SYN_ATC25" = "y" \
|
||||
-o "$CONFIG_SYN_INFER_REGF" = "y" -o "$CONFIG_SYN_VIRTEX2" = "y"]; then
|
||||
bool 'Improve register file write timing' CONFIG_SYN_RFTYPE
|
||||
fi
|
||||
if [ "$CONFIG_SYN_ATC25" = "y" -o "$CONFIG_SYN_VIRTEX" = "y" -o "$CONFIG_SYN_VIRTEX2" = "y"\
|
||||
-o "$CONFIG_SYN_ATC18" = "y" -o "$CONFIG_SYN_TSMC025" = "y" ]; then
|
||||
if [ "$CONFIG_SYN_INFER_RAM" != "y" ]; then
|
||||
bool 'Use dual-port RAM for DSU trace buffer ' \
|
||||
CONFIG_SYN_TRACE_DPRAM $CONFIG_SYN_ATC25 $CONFIG_SYN_ATC18 \
|
||||
$CONFIG_SYN_VIRTEX $CONFIG_SYN_TSMC025 $CONFIG_SYN_VIRTEX2
|
||||
fi
|
||||
fi
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Clock generation'
|
||||
if [ "$CONFIG_SYN_VIRTEX" = "y" -o "$CONFIG_SYN_VIRTEX2" = "y" ]; then
|
||||
bool 'Use Virtex CLKDLL for clock generation' CONFIG_CLK_VIRTEX
|
||||
fi
|
||||
if [ "$CONFIG_SYN_VIRTEX2" = "y" -a "$CONFIG_CLK_VIRTEX" != "y"]; then
|
||||
bool 'Use Virtex-II DCM for clock generation' CONFIG_CLK_VIRTEX2
|
||||
fi
|
||||
if [ "$CONFIG_CLK_VIRTEX" = "y"]; then
|
||||
choice ' System clock multiplier (CLKDLL)' \
|
||||
"1/2 CONFIG_CLKDLL_1_2 \
|
||||
1 CONFIG_CLKDLL_1_1 \
|
||||
2 CONFIG_CLKDLL_2_1" 1
|
||||
fi
|
||||
if [ "$CONFIG_CLK_VIRTEX2" = "y"]; then
|
||||
choice ' System clock multiplier (DCM)' \
|
||||
"2/3 CONFIG_DCM_2_3 \
|
||||
3/4 CONFIG_DCM_3_4 \
|
||||
4/5 CONFIG_DCM_4_5 \
|
||||
1 CONFIG_DCM_1_1 \
|
||||
5/4 CONFIG_DCM_5_4 \
|
||||
4/3 CONFIG_DCM_4_3 \
|
||||
3/2 CONFIG_DCM_3_2 \
|
||||
5/3 CONFIG_DCM_5_3 \
|
||||
2 CONFIG_DCM_2_1 \
|
||||
3 CONFIG_DCM_3_1 \
|
||||
4 CONFIG_DCM_4_1" 1
|
||||
fi
|
||||
if [ "$CONFIG_SYN_AXCEL" = "y" ]; then
|
||||
bool 'Use global clock pad (Actel AX)' CONFIG_AXCEL_HCLKBUF
|
||||
fi
|
||||
if [ "$CONFIG_SYN_VIRTEX2" = "y" -o "$CONFIG_CLK_VIRTEX" = "y"]; then
|
||||
bool 'Enable CLKDLL for PCI clock' CONFIG_PCI_DLL
|
||||
fi
|
||||
if [ "$CONFIG_PCI_DLL" != "y" ]; then
|
||||
bool 'Use PCI clock as system clock' CONFIG_PCI_SYSCLK
|
||||
fi
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Processor '
|
||||
mainmenu_option next_comment
|
||||
comment 'Integer unit '
|
||||
int 'SPARC register windows' CONFIG_IU_NWINDOWS 8
|
||||
bool 'SPARC V8 MUL/DIV instructions' CONFIG_IU_V8MULDIV
|
||||
if [ "$CONFIG_IU_V8MULDIV" = "y" ]; then
|
||||
choice 'Hardware multiplier latency' \
|
||||
"1-cycle CONFIG_IU_MUL_LATENCY_1 \
|
||||
2-cycles CONFIG_IU_MUL_LATENCY_2 \
|
||||
4-cycles CONFIG_IU_MUL_LATENCY_4 \
|
||||
5-cycles CONFIG_IU_MUL_LATENCY_5 \
|
||||
35-cycles CONFIG_IU_MUL_LATENCY_35" 5-cycles
|
||||
fi
|
||||
dep_bool 'SPARC V8e SMAC/UMAC instructions ' CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_LATENCY_4 $CONFIG_IU_V8MULDIV
|
||||
int 'Load delay' CONFIG_IU_LDELAY 1
|
||||
bool 'Fast jump-address generation ' CONFIG_IU_FASTJUMP
|
||||
bool 'ICC interlock ' CONFIG_IU_ICCHOLD
|
||||
bool 'Fast instruction decoding ' CONFIG_IU_FASTDECODE
|
||||
if [ "$CONFIG_SYN_TSMC025" = "y" -o "$CONFIG_SYN_UMC018" = "y" \
|
||||
-o "$CONFIG_SYN_FS90" = "y" -o "$CONFIG_SYN_PROASIC" = "y" \
|
||||
-o "$CONFIG_SYN_ATC18" = "y" \
|
||||
-o "$CONFIG_SYN_AXCEL" = "y" -o "$CONFIG_SYN_ATC25" = "y" ]; then
|
||||
bool 'Register file power-saving ' CONFIG_IU_RFPOW
|
||||
fi
|
||||
int 'Hardware watchpoints' CONFIG_IU_WATCHPOINTS 0
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'Floating-point unit'
|
||||
bool 'Enable FPU ' CONFIG_FPU_ENABLE
|
||||
if [ "$CONFIG_FPU_ENABLE" = "y" ]; then
|
||||
choice 'FPU core' \
|
||||
"GRFPU CONFIG_FPU_GRFPU \
|
||||
Meiko CONFIG_FPU_MEIKO \
|
||||
LTH CONFIG_FPU_LTH" GRFPU
|
||||
int 'FSR version ID' CONFIG_FPU_VER 0
|
||||
fi
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'Co-processor'
|
||||
bool 'Enable co-processor ' CONFIG_CP_ENABLE
|
||||
if [ "$CONFIG_CP_ENABLE" = "y" ]; then
|
||||
string 'Co-processor configuration' CONFIG_CP_CFG "cp_none"
|
||||
fi
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'Cache system '
|
||||
comment 'Instruction cache '
|
||||
choice 'Associativity (sets) ' \
|
||||
"1 CONFIG_ICACHE_ASSO1 \
|
||||
2 CONFIG_ICACHE_ASSO2 \
|
||||
3 CONFIG_ICACHE_ASSO3 \
|
||||
4 CONFIG_ICACHE_ASSO4" 1
|
||||
choice 'Set size (kbytes/set)' \
|
||||
"1 CONFIG_ICACHE_SZ1 \
|
||||
2 CONFIG_ICACHE_SZ2 \
|
||||
4 CONFIG_ICACHE_SZ4 \
|
||||
8 CONFIG_ICACHE_SZ8 \
|
||||
16 CONFIG_ICACHE_SZ16 \
|
||||
32 CONFIG_ICACHE_SZ32 \
|
||||
64 CONFIG_ICACHE_SZ64" 2
|
||||
choice 'Line size (bytes/line)' \
|
||||
"16 CONFIG_ICACHE_LZ16 \
|
||||
32 CONFIG_ICACHE_LZ32" 16
|
||||
if [ "$CONFIG_ICACHE_ASSO1" != "y" ]; then
|
||||
choice 'Replacement alorithm' \
|
||||
"Random CONFIG_ICACHE_ALGORND \
|
||||
LRR CONFIG_ICACHE_ALGOLRR \
|
||||
LRU CONFIG_ICACHE_ALGOLRU" Random
|
||||
bool 'Cache locking ' CONFIG_ICACHE_LOCK
|
||||
fi
|
||||
comment 'Data cache'
|
||||
choice 'Associativity (sets)' \
|
||||
"1 CONFIG_DCACHE_ASSO1 \
|
||||
2 CONFIG_DCACHE_ASSO2 \
|
||||
3 CONFIG_DCACHE_ASSO3 \
|
||||
4 CONFIG_DCACHE_ASSO4" 1
|
||||
choice 'Set size (kbytes/set)' \
|
||||
"1 CONFIG_DCACHE_SZ1 \
|
||||
2 CONFIG_DCACHE_SZ2 \
|
||||
4 CONFIG_DCACHE_SZ4 \
|
||||
8 CONFIG_DCACHE_SZ8 \
|
||||
16 CONFIG_DCACHE_SZ16 \
|
||||
32 CONFIG_DCACHE_SZ32 \
|
||||
64 CONFIG_DCACHE_SZ64" 2
|
||||
choice 'Line size (bytes/line)' \
|
||||
"16 CONFIG_DCACHE_LZ16 \
|
||||
32 CONFIG_DCACHE_LZ32" 16
|
||||
if [ "$CONFIG_DCACHE_ASSO1" != "y" ]; then
|
||||
choice 'Replacement alorithm' \
|
||||
"Random CONFIG_DCACHE_ALGORND \
|
||||
LRR CONFIG_DCACHE_ALGOLRR \
|
||||
LRU CONFIG_DCACHE_ALGOLRU" Random
|
||||
bool 'Cache locking ' CONFIG_DCACHE_LOCK
|
||||
fi
|
||||
if [ "$CONFIG_SYN_ATC25" = "y" -o "$CONFIG_SYN_VIRTEX" = "y" -o "$CONFIG_SYN_VIRTEX2" = "y" \
|
||||
-o "$CONFIG_SYN_ATC18" = "y" -o "$CONFIG_SYN_TSMC025" = "y" ]; then
|
||||
if [ "$CONFIG_SYN_INFER_RAM" != "y" -a "$CONFIG_MMU_ENABLE" != "y" ]; then
|
||||
bool 'AHB snooping ' CONFIG_DCACHE_SNOOP
|
||||
fi
|
||||
fi
|
||||
if [ "$CONFIG_DCACHE_SNOOP" = "y" ]; then
|
||||
choice 'Snoop implementation' \
|
||||
"Slow CONFIG_DCACHE_SNOOP_SLOW \
|
||||
Fast CONFIG_DCACHE_SNOOP_FAST" Slow
|
||||
fi
|
||||
if [ "$CONFIG_DCACHE_ASSO1" != "y" ]; then
|
||||
bool 'Fast read-data generation ' CONFIG_DCACHE_RFAST
|
||||
fi
|
||||
if [ "$CONFIG_DCACHE_ASSO1" != "y" ]; then
|
||||
bool 'Fast write-data generation ' CONFIG_DCACHE_WFAST
|
||||
fi
|
||||
if [ "$CONFIG_MMU_ENABLE" != "y" ]; then
|
||||
bool 'Enable local data RAM ' CONFIG_DCACHE_LRAM
|
||||
fi
|
||||
if [ "$CONFIG_DCACHE_LRAM" = "y" ]; then
|
||||
choice 'Local data RAM size (kbytes)' \
|
||||
"1 CONFIG_DCACHE_LRAM_SZ1 \
|
||||
2 CONFIG_DCACHE_LRAM_SZ2 \
|
||||
4 CONFIG_DCACHE_LRAM_SZ4 \
|
||||
8 CONFIG_DCACHE_LRAM_SZ8 \
|
||||
16 CONFIG_DCACHE_LRAM_SZ16 \
|
||||
32 CONFIG_DCACHE_LRAM_SZ32 \
|
||||
64 CONFIG_DCACHE_LRAM_SZ64" 2
|
||||
hex ' Local RAM start address (8 MSB) ' CONFIG_DCACHE_LRSTART 0x8f
|
||||
fi
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'MMU'
|
||||
bool 'Enable MMU ' CONFIG_MMU_ENABLE
|
||||
if [ "$CONFIG_MMU_ENABLE" = "y" ]; then
|
||||
choice 'MMU type ' \
|
||||
"combined CONFIG_MMU_COMBINED \
|
||||
split CONFIG_MMU_SPLIT" combined
|
||||
choice 'TLB replacement sheme ' \
|
||||
"LRU CONFIG_MMU_REPARRAY \
|
||||
Increment CONFIG_MMU_REPINCREMENT" increment
|
||||
choice 'Instruction (or combined) TLB entries' \
|
||||
"2 CONFIG_MMU_I2 \
|
||||
4 CONFIG_MMU_I4 \
|
||||
8 CONFIG_MMU_I8 \
|
||||
16 CONFIG_MMU_I16 \
|
||||
32 CONFIG_MMU_I32" 8
|
||||
if [ "$CONFIG_MMU_SPLIT" = "y" ]; then
|
||||
choice 'Data TLB entries' \
|
||||
"2 CONFIG_MMU_D2 \
|
||||
4 CONFIG_MMU_D4 \
|
||||
8 CONFIG_MMU_D8 \
|
||||
16 CONFIG_MMU_D16 \
|
||||
32 CONFIG_MMU_D32" 8
|
||||
fi
|
||||
bool 'Enable Diagnostic Access ' CONFIG_MMU_DIAG
|
||||
fi
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Debug support unit '
|
||||
bool 'Debug support unit ' CONFIG_DSU_ENABLE
|
||||
if [ "$CONFIG_DSU_ENABLE" = "y" ]; then
|
||||
bool 'Trace buffer' CONFIG_DSU_TRACEBUF
|
||||
if [ "$CONFIG_DSU_TRACEBUF" = "y" ]; then
|
||||
bool 'Mixed instruction/AHB tracing' CONFIG_DSU_MIXED_TRACE
|
||||
choice 'Trace buffer lines' \
|
||||
"64 CONFIG_DSU_TRACESZ64 \
|
||||
128 CONFIG_DSU_TRACESZ128 \
|
||||
256 CONFIG_DSU_TRACESZ256 \
|
||||
512 CONFIG_DSU_TRACESZ512 \
|
||||
1024 CONFIG_DSU_TRACESZ1024" 128
|
||||
fi
|
||||
fi
|
||||
endmenu
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'AMBA configuration'
|
||||
int 'Default AHB master' CONFIG_AHB_DEFMST 0
|
||||
bool 'AHB split-transaction support ' CONFIG_AHB_SPLIT
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Memory controller'
|
||||
bool '8-bit PROM/SRAM bus support ' CONFIG_MCTRL_8BIT
|
||||
bool '16-bit PROM/SRAM bus support ' CONFIG_MCTRL_16BIT
|
||||
bool 'RAM write protection ' CONFIG_PERI_WPROT
|
||||
bool 'Write strobe timing feedback ' CONFIG_MCTRL_WFB
|
||||
bool '5th SRAM chip-select ' CONFIG_MCTRL_5CS
|
||||
bool 'SDRAM controller ' CONFIG_MCTRL_SDRAM
|
||||
if [ "$CONFIG_MCTRL_SDRAM" = "y" ]; then
|
||||
bool 'Inverted SDRAM clock' CONFIG_MCTRL_SDRAM_INVCLK
|
||||
bool 'Separate address and data buses' CONFIG_MCTRL_SDRAM_SEPBUS
|
||||
fi
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Peripherals '
|
||||
bool 'LEON configuration register ' CONFIG_PERI_LCONF
|
||||
bool 'Secondary interrupt controller ' CONFIG_PERI_IRQ2
|
||||
if [ "$CONFIG_PERI_IRQ2" = "y" ]; then
|
||||
string 'Sec. interrupt controller configuration ' CONFIG_PERI_IRQ2_CFG "irq2none"
|
||||
fi
|
||||
bool 'Watchdog ' CONFIG_PERI_WDOG
|
||||
bool 'AHB status register ' CONFIG_PERI_AHBSTAT
|
||||
bool 'On-chip AHB RAM ' CONFIG_AHBRAM_ENABLE
|
||||
if [ "$CONFIG_AHBRAM_ENABLE" = "y" ]; then
|
||||
choice 'AHB RAM size (Kbyte)' \
|
||||
"1 CONFIG_AHBRAM_SZ1 \
|
||||
2 CONFIG_AHBRAM_SZ2 \
|
||||
4 CONFIG_AHBRAM_SZ4 \
|
||||
8 CONFIG_AHBRAM_SZ8 \
|
||||
16 CONFIG_AHBRAM_SZ16 \
|
||||
32 CONFIG_AHBRAM_SZ32 \
|
||||
64 CONFIG_AHBRAM_SZ64" 4
|
||||
fi
|
||||
mainmenu_option next_comment
|
||||
comment 'Ethernet interface '
|
||||
bool 'Enable Ethernet interface ' CONFIG_ETH_ENABLE
|
||||
if [ "$CONFIG_ETH_ENABLE" = "y" ]; then
|
||||
int 'TX FIFO depth' CONFIG_ETH_TXFIFO 8
|
||||
int 'RX FIFO depth' CONFIG_ETH_RXFIFO 8
|
||||
int 'AHB burst length' CONFIG_ETH_BURST 4
|
||||
fi
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'PCI interface '
|
||||
bool 'Enable PCI interface ' CONFIG_PCI_ENABLE
|
||||
if [ "$CONFIG_PCI_ENABLE" = "y" ]; then
|
||||
choice 'PCI core' \
|
||||
"Simple-target CONFIG_PCI_SIMPLE_TARGET" Simple-target
|
||||
hex 'PCI vendor ID' CONFIG_PCI_VENDORID 16E3
|
||||
hex 'PCI device ID' CONFIG_PCI_DEVICEID 0210
|
||||
hex 'PCI revision ID' CONFIG_PCI_REVID 1
|
||||
if [ "$CONFIG_PCI_FAST_TARGET" = "y" -o "$CONFIG_PCI_MASTER_TARGET" = "y" ]; then
|
||||
choice 'PCI FIFO depth' \
|
||||
"8 CONFIG_PCI_FIFO8 \
|
||||
16 CONFIG_PCI_FIFO16 \
|
||||
32 CONFIG_PCI_FIFO32 \
|
||||
64 CONFIG_PCI_FIFO64 \
|
||||
128 CONFIG_PCI_FIFO128" 8
|
||||
fi
|
||||
if [ "$CONFIG_PCI_TRACE" = "y" ]; then
|
||||
choice 'PCI trace buffer depth' \
|
||||
"256 CONFIG_PCI_TRACE256 \
|
||||
512 CONFIG_PCI_TRACE512 \
|
||||
1024 CONFIG_PCI_TRACE1024 \
|
||||
2048 CONFIG_PCI_TRACE2048 \
|
||||
4096 CONFIG_PCI_TRACE4096" 256
|
||||
fi
|
||||
bool 'PCI reset affects complete processor' CONFIG_PCI_RESETALL
|
||||
bool 'PCI arbiter ' CONFIG_PCI_ARBEN
|
||||
fi
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
mainmenu_option next_comment
|
||||
comment 'Boot options'
|
||||
choice 'Boot selection ' \
|
||||
"Memory CONFIG_BOOT_EXTPROM \
|
||||
Internal-PROM CONFIG_BOOT_INTPROM \
|
||||
Both CONFIG_BOOT_MIXPROM" Memory
|
||||
if [ "$CONFIG_BOOT_EXTPROM" != "y" ]; then
|
||||
int 'RAM read waitstates' CONFIG_BOOT_RWS 0
|
||||
int 'RAM write waitstates' CONFIG_BOOT_WWS 0
|
||||
int 'System clock frequency' CONFIG_BOOT_SYSCLK 25000000
|
||||
int 'UART baud rate' CONFIG_BOOT_BAUDRATE 38400
|
||||
bool 'Use external baud rate setting (PIO[7:0]) ' CONFIG_BOOT_EXTBAUD
|
||||
int 'Internal boot PROM address bits' CONFIG_BOOT_PROMABITS 11
|
||||
fi
|
||||
endmenu
|
||||
mainmenu_option next_comment
|
||||
comment 'VHDL Debugging '
|
||||
bool 'Accelerated UART tracing ' CONFIG_DEBUG_UART
|
||||
bool 'Integer unit register writes ' CONFIG_DEBUG_IURF
|
||||
dep_bool 'Floating-point unit register writes ' CONFIG_DEBUG_FPURF $CONFIG_FPU_ENABLE
|
||||
bool 'Continue on reset trap ' CONFIG_DEBUG_NOHALT
|
||||
bool '32-bit program counters ' CONFIG_DEBUG_PC32
|
||||
if [ "$CONFIG_FT_ENABLE" = "y" ]; then
|
||||
if [ "$CONFIG_FT_RF_ENABLE" = "y" ]; then
|
||||
bool 'Inject register-file errors ' CONFIG_DEBUG_RFERR
|
||||
fi
|
||||
if [ "$CONFIG_FT_CACHEMEM_ENABLE" = "y" ]; then
|
||||
bool 'Inject cache memory errors ' CONFIG_DEBUG_CACHEMEMERR
|
||||
fi
|
||||
fi
|
||||
endmenu
|
||||
150
bin/tkconfig/defconfig
Normal file
150
bin/tkconfig/defconfig
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
|
||||
#
|
||||
# Synthesis
|
||||
#
|
||||
CONFIG_SYN_GENERIC=y
|
||||
# CONFIG_SYN_ATC35 is not set
|
||||
# CONFIG_SYN_ATC25 is not set
|
||||
# CONFIG_SYN_ATC18 is not set
|
||||
# CONFIG_SYN_FS90 is not set
|
||||
# CONFIG_SYN_UMC018 is not set
|
||||
# CONFIG_SYN_TSMC025 is not set
|
||||
# CONFIG_SYN_PROASIC is not set
|
||||
# CONFIG_SYN_AXCEL is not set
|
||||
# CONFIG_SYN_VIRTEX is not set
|
||||
# CONFIG_SYN_VIRTEX2 is not set
|
||||
CONFIG_SYN_INFER_MULT=y
|
||||
CONFIG_SYN_RFTYPE=y
|
||||
|
||||
#
|
||||
# Clock generation
|
||||
#
|
||||
# CONFIG_PCI_SYSCLK is not set
|
||||
|
||||
#
|
||||
# Processor
|
||||
#
|
||||
|
||||
#
|
||||
# Integer unit
|
||||
#
|
||||
CONFIG_IU_NWINDOWS=8
|
||||
# CONFIG_IU_V8MULDIV is not set
|
||||
CONFIG_IU_LDELAY=1
|
||||
CONFIG_IU_FASTJUMP=y
|
||||
CONFIG_IU_ICCHOLD=y
|
||||
CONFIG_IU_FASTDECODE=y
|
||||
CONFIG_IU_WATCHPOINTS=0
|
||||
|
||||
#
|
||||
# Floating-point unit
|
||||
#
|
||||
# CONFIG_FPU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Co-processor
|
||||
#
|
||||
# CONFIG_CP_ENABLE is not set
|
||||
|
||||
#
|
||||
# Cache system
|
||||
#
|
||||
|
||||
#
|
||||
# Instruction cache
|
||||
#
|
||||
CONFIG_ICACHE_ASSO1=y
|
||||
# CONFIG_ICACHE_ASSO2 is not set
|
||||
# CONFIG_ICACHE_ASSO3 is not set
|
||||
# CONFIG_ICACHE_ASSO4 is not set
|
||||
# CONFIG_ICACHE_SZ1 is not set
|
||||
# CONFIG_ICACHE_SZ2 is not set
|
||||
CONFIG_ICACHE_SZ4=y
|
||||
# CONFIG_ICACHE_SZ8 is not set
|
||||
# CONFIG_ICACHE_SZ16 is not set
|
||||
# CONFIG_ICACHE_SZ32 is not set
|
||||
# CONFIG_ICACHE_SZ64 is not set
|
||||
# CONFIG_ICACHE_LZ16 is not set
|
||||
CONFIG_ICACHE_LZ32=y
|
||||
|
||||
#
|
||||
# Data cache
|
||||
#
|
||||
CONFIG_DCACHE_ASSO1=y
|
||||
# CONFIG_DCACHE_ASSO2 is not set
|
||||
# CONFIG_DCACHE_ASSO3 is not set
|
||||
# CONFIG_DCACHE_ASSO4 is not set
|
||||
# CONFIG_DCACHE_SZ1 is not set
|
||||
# CONFIG_DCACHE_SZ2 is not set
|
||||
CONFIG_DCACHE_SZ4=y
|
||||
# CONFIG_DCACHE_SZ8 is not set
|
||||
# CONFIG_DCACHE_SZ16 is not set
|
||||
# CONFIG_DCACHE_SZ32 is not set
|
||||
# CONFIG_DCACHE_SZ64 is not set
|
||||
# CONFIG_DCACHE_LZ16 is not set
|
||||
CONFIG_DCACHE_LZ32=y
|
||||
# CONFIG_DCACHE_LRAM is not set
|
||||
|
||||
#
|
||||
# MMU
|
||||
#
|
||||
# CONFIG_MMU_ENABLE is not set
|
||||
|
||||
#
|
||||
# Debug support unit
|
||||
#
|
||||
# CONFIG_DSU_ENABLE is not set
|
||||
|
||||
#
|
||||
# AMBA configuration
|
||||
#
|
||||
CONFIG_AHB_DEFMST=0
|
||||
# CONFIG_AHB_SPLIT is not set
|
||||
|
||||
#
|
||||
# Memory controller
|
||||
#
|
||||
# CONFIG_MCTRL_8BIT is not set
|
||||
# CONFIG_MCTRL_16BIT is not set
|
||||
# CONFIG_PERI_WPROT is not set
|
||||
# CONFIG_MCTRL_WFB is not set
|
||||
# CONFIG_MCTRL_5CS is not set
|
||||
# CONFIG_MCTRL_SDRAM is not set
|
||||
|
||||
#
|
||||
# Peripherals
|
||||
#
|
||||
CONFIG_PERI_LCONF=y
|
||||
# CONFIG_PERI_IRQ2 is not set
|
||||
# CONFIG_PERI_WDOG is not set
|
||||
# CONFIG_PERI_AHBSTAT is not set
|
||||
# CONFIG_AHBRAM_ENABLE is not set
|
||||
|
||||
#
|
||||
# Ethernet interface
|
||||
#
|
||||
# CONFIG_ETH_ENABLE is not set
|
||||
|
||||
#
|
||||
# PCI interface
|
||||
#
|
||||
# CONFIG_PCI_ENABLE is not set
|
||||
|
||||
#
|
||||
# Boot options
|
||||
#
|
||||
CONFIG_BOOT_EXTPROM=y
|
||||
# CONFIG_BOOT_INTPROM is not set
|
||||
# CONFIG_BOOT_MIXPROM is not set
|
||||
|
||||
#
|
||||
# VHDL Debugging
|
||||
#
|
||||
# CONFIG_DEBUG_UART is not set
|
||||
# CONFIG_DEBUG_IURF is not set
|
||||
# CONFIG_DEBUG_NOHALT is not set
|
||||
# CONFIG_DEBUG_PC32 is not set
|
||||
645
bin/tkconfig/header.tk
Normal file
645
bin/tkconfig/header.tk
Normal file
|
|
@ -0,0 +1,645 @@
|
|||
# FILE: header.tk
|
||||
# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
|
||||
#
|
||||
# CHANGES
|
||||
# =======
|
||||
#
|
||||
# 8 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
# - Remove unused do_cmd function (part of the 2.0 sound support).
|
||||
# - Arrange buttons in three columns for better screen fitting.
|
||||
# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like:
|
||||
# dep_tristate 'foo' CONFIG_FOO m
|
||||
#
|
||||
# 23 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
# - Shut vfix the hell up.
|
||||
#
|
||||
# 24 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
# - Improve the exit message (Jeff Ronne).
|
||||
|
||||
#
|
||||
# This is a handy replacement for ".widget cget" that requires neither tk4
|
||||
# nor additional source code uglification.
|
||||
#
|
||||
proc cget { w option } {
|
||||
return "[lindex [$w configure $option] 4]"
|
||||
}
|
||||
|
||||
#
|
||||
# Function to compensate for broken config.in scripts like the sound driver,
|
||||
# which make dependencies on variables that are never even conditionally
|
||||
# defined.
|
||||
#
|
||||
proc vfix { var } {
|
||||
global $var
|
||||
if [ catch {eval concat $$var} ] {
|
||||
set $var 4
|
||||
}
|
||||
}
|
||||
|
||||
#
|
||||
# Constant values used by certain dep_tristate commands.
|
||||
#
|
||||
set CONSTANT_Y 1
|
||||
set CONSTANT_M 2
|
||||
set CONSTANT_N 0
|
||||
set CONSTANT_E 4
|
||||
|
||||
#
|
||||
# Create a "reference" object to steal colors from.
|
||||
#
|
||||
button .ref
|
||||
|
||||
#
|
||||
# On monochrome displays, -disabledforeground is blank by default; that's
|
||||
# bad. Fill it with -foreground instead.
|
||||
#
|
||||
if { [cget .ref -disabledforeground] == "" } {
|
||||
.ref configure -disabledforeground [cget .ref -foreground]
|
||||
}
|
||||
|
||||
|
||||
#
|
||||
# Define some macros we will need to parse the config.in file.
|
||||
#
|
||||
|
||||
proc mainmenu_name { text } {
|
||||
wm title . "$text"
|
||||
}
|
||||
|
||||
proc menu_option { w menu_num text } {
|
||||
global menus_per_column
|
||||
global processed_top_level
|
||||
set processed_top_level [expr $processed_top_level + 1]
|
||||
if { $processed_top_level <= $menus_per_column } then {
|
||||
set myframe left
|
||||
} elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then {
|
||||
set myframe middle
|
||||
} else {
|
||||
set myframe right
|
||||
}
|
||||
button .f0.x$menu_num -anchor w -text "$text" \
|
||||
-command "$w .$w \"$text\""
|
||||
pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe
|
||||
}
|
||||
|
||||
proc load_configfile { w title func } {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
global loadfile
|
||||
frame $w.x
|
||||
label $w.bm -bitmap questhead
|
||||
pack $w.bm -pady 10 -side top -padx 10
|
||||
label $w.x.l -text "Enter filename:" -relief raised
|
||||
entry $w.x.x -width 35 -relief sunken -borderwidth 2 \
|
||||
-textvariable loadfile
|
||||
pack $w.x.l $w.x.x -anchor w -side left
|
||||
pack $w.x -side top -pady 10
|
||||
wm title $w "$title"
|
||||
|
||||
set oldFocus [focus]
|
||||
frame $w.f
|
||||
button $w.f.back -text "OK" -width 20 \
|
||||
-command "destroy $w; focus $oldFocus;$func .fileio"
|
||||
button $w.f.canc -text "Cancel" \
|
||||
-width 20 -command "destroy $w; focus $oldFocus"
|
||||
pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
|
||||
pack $w.f -pady 10 -side bottom -padx 10 -anchor w
|
||||
focus $w
|
||||
global winx; global winy
|
||||
set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
|
||||
wm geometry $w +$winx+$winy
|
||||
}
|
||||
|
||||
bind all <Alt-q> {maybe_exit .maybe}
|
||||
|
||||
proc maybe_exit { w } {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
label $w.bm -bitmap questhead
|
||||
pack $w.bm -pady 10 -side top -padx 10
|
||||
message $w.m -width 400 -aspect 300 \
|
||||
-text "Changes will be lost. Are you sure?" -relief flat
|
||||
pack $w.m -pady 10 -side top -padx 10
|
||||
wm title $w "Are you sure?"
|
||||
|
||||
set oldFocus [focus]
|
||||
frame $w.f
|
||||
button $w.f.back -text "OK" -width 20 \
|
||||
-command "exit 1"
|
||||
button $w.f.canc -text "Cancel" \
|
||||
-width 20 -command "destroy $w; focus $oldFocus"
|
||||
pack $w.f.back $w.f.canc -side left -pady 10 -padx 45
|
||||
pack $w.f -pady 10 -side bottom -padx 10 -anchor w
|
||||
bind $w <Return> "exit 1"
|
||||
bind $w <Escape> "destroy $w; focus $oldFocus"
|
||||
focus $w
|
||||
global winx; global winy
|
||||
set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
|
||||
wm geometry $w +$winx+$winy
|
||||
}
|
||||
|
||||
proc read_config_file { w } {
|
||||
global loadfile
|
||||
if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then {
|
||||
read_config $loadfile
|
||||
} else {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
message $w.m -width 400 -aspect 300 -text \
|
||||
"Unable to read file $loadfile" \
|
||||
-relief raised
|
||||
label $w.bm -bitmap error
|
||||
pack $w.bm $w.m -pady 10 -side top -padx 10
|
||||
wm title $w "Xconfig Internal Error"
|
||||
|
||||
set oldFocus [focus]
|
||||
frame $w.f
|
||||
button $w.f.back -text "Bummer" \
|
||||
-width 10 -command "destroy $w; focus $oldFocus"
|
||||
pack $w.f.back -side bottom -pady 10 -anchor s
|
||||
pack $w.f -pady 10 -side top -padx 10 -anchor s
|
||||
focus $w
|
||||
global winx; global winy
|
||||
set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
|
||||
wm geometry $w +$winx+$winy
|
||||
}
|
||||
}
|
||||
|
||||
proc write_config_file { w } {
|
||||
global loadfile
|
||||
if { [string length $loadfile] != 0
|
||||
&& ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then {
|
||||
writeconfig $loadfile .null
|
||||
} else {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
message $w.m -width 400 -aspect 300 -text \
|
||||
"Unable to write file $loadfile" \
|
||||
-relief raised
|
||||
label $w.bm -bitmap error
|
||||
pack $w.bm $w.m -pady 10 -side top -padx 10
|
||||
wm title $w "Xconfig Internal Error"
|
||||
|
||||
set oldFocus [focus]
|
||||
frame $w.f
|
||||
button $w.f.back -text "OK" \
|
||||
-width 10 -command "destroy $w; focus $oldFocus"
|
||||
pack $w.f.back -side bottom -pady 10 -anchor s
|
||||
pack $w.f -pady 10 -side top -padx 10 -anchor s
|
||||
focus $w
|
||||
global winx; global winy
|
||||
set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
|
||||
wm geometry $w +$winx+$winy
|
||||
}
|
||||
}
|
||||
|
||||
proc read_config { filename } {
|
||||
set file1 [open $filename r]
|
||||
clear_choices
|
||||
while { [gets $file1 line] >= 0} {
|
||||
if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] {
|
||||
if { $value == "y" } then { set cmd "global $var; set $var 1" }
|
||||
if { $value == "n" } then { set cmd "global $var; set $var 0" }
|
||||
if { $value == "m" } then { set cmd "global $var; set $var 2" }
|
||||
eval $cmd
|
||||
}
|
||||
if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] {
|
||||
set cmd "global $var; set $var 0"
|
||||
eval $cmd
|
||||
}
|
||||
if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] {
|
||||
set cmd "global $var; set $var $value"
|
||||
eval $cmd
|
||||
}
|
||||
if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] {
|
||||
set cmd "global $var; set $var \"$value\""
|
||||
eval $cmd
|
||||
}
|
||||
}
|
||||
close $file1
|
||||
update_choices
|
||||
update_mainmenu
|
||||
}
|
||||
proc write_comment { file1 file2 text } {
|
||||
puts $file1 ""
|
||||
puts $file1 "#"
|
||||
puts $file1 "# $text"
|
||||
puts $file1 "#"
|
||||
puts $file2 "/*"
|
||||
puts $file2 " * $text"
|
||||
puts $file2 " */"
|
||||
}
|
||||
|
||||
proc effective_dep { deplist } {
|
||||
global CONFIG_MODULES
|
||||
set depend 1
|
||||
foreach i $deplist {
|
||||
if {$i == 0} then {set depend 0}
|
||||
if {$i == 2 && $depend == 1} then {set depend 2}
|
||||
}
|
||||
if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0}
|
||||
return $depend
|
||||
}
|
||||
|
||||
proc sync_tristate { var dep } {
|
||||
global CONFIG_MODULES
|
||||
if {$dep == 0 && ($var == 1 || $var == 2)} then {
|
||||
set var 0
|
||||
} elseif {$dep == 2 && $var == 1} then {
|
||||
set var 2
|
||||
} elseif {$var == 2 && $CONFIG_MODULES == 0} then {
|
||||
if {$dep == 1} then {set var 1} else {set var 0}
|
||||
}
|
||||
return $var
|
||||
}
|
||||
|
||||
proc sync_bool { var dep modset } {
|
||||
set var [sync_tristate $var $dep]
|
||||
if {$dep == 2 && $var == 2} then {
|
||||
set var $modset
|
||||
}
|
||||
return $var
|
||||
}
|
||||
|
||||
proc write_tristate { file1 file2 varname variable deplist modset } {
|
||||
set variable [sync_tristate $variable [effective_dep $deplist]]
|
||||
if { $variable == 2 } \
|
||||
then { set variable $modset }
|
||||
if { $variable == 1 } \
|
||||
then { puts $file1 "$varname=y"; \
|
||||
puts $file2 "#define $varname 1" } \
|
||||
elseif { $variable == 2 } \
|
||||
then { puts $file1 "$varname=m"; \
|
||||
puts $file2 "#undef $varname"; \
|
||||
puts $file2 "#define ${varname}_MODULE 1" } \
|
||||
elseif { $variable == 0 } \
|
||||
then { puts $file1 "# $varname is not set"; \
|
||||
puts $file2 "#undef $varname"} \
|
||||
else { \
|
||||
puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \
|
||||
}
|
||||
}
|
||||
|
||||
proc write_int { file1 file2 varname variable dep } {
|
||||
if { $dep == 0 } \
|
||||
then { puts $file1 "# $varname is not set"; \
|
||||
puts $file2 "#undef $varname"} \
|
||||
else {
|
||||
puts $file1 "$varname=$variable"; \
|
||||
puts $file2 "#define $varname ($variable)"; \
|
||||
}
|
||||
}
|
||||
|
||||
proc write_hex { file1 file2 varname variable dep } {
|
||||
if { $dep == 0 } \
|
||||
then { puts $file1 "# $varname is not set"; \
|
||||
puts $file2 "#undef $varname"} \
|
||||
else {
|
||||
puts $file1 "$varname=$variable"; \
|
||||
puts -nonewline $file2 "#define $varname "; \
|
||||
puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \
|
||||
}
|
||||
}
|
||||
|
||||
proc write_string { file1 file2 varname variable dep } {
|
||||
if { $dep == 0 } \
|
||||
then { puts $file1 "# $varname is not set"; \
|
||||
puts $file2 "#undef $varname"} \
|
||||
else {
|
||||
puts $file1 "$varname=\"$variable\""; \
|
||||
puts $file2 "#define $varname \"$variable\""; \
|
||||
}
|
||||
}
|
||||
|
||||
proc option_name {w mnum line text helpidx} {
|
||||
button $w.x$line.l -text "$text" -relief groove -anchor w
|
||||
$w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
|
||||
-activeback [cget $w.x$line.l -bg]
|
||||
button $w.x$line.help -text "Help" -relief raised \
|
||||
-command "dohelp .dohelp $helpidx .menu$mnum"
|
||||
pack $w.x$line.help -side right -fill y
|
||||
pack $w.x$line.l -side right -fill both -expand on
|
||||
}
|
||||
|
||||
proc toggle_switch2 {w mnum line text variable} {
|
||||
frame $w.x$line -relief sunken
|
||||
radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
|
||||
-relief groove -width 2 -command "update_active"
|
||||
# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \
|
||||
# -relief groove -width 2 -command "update_active"
|
||||
radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
|
||||
-relief groove -width 2 -command "update_active"
|
||||
|
||||
option_name $w $mnum $line $text $variable
|
||||
|
||||
pack $w.x$line.n $w.x$line.y -side right -fill y
|
||||
}
|
||||
|
||||
proc toggle_switch3 {w mnum line text variable} {
|
||||
frame $w.x$line -relief sunken
|
||||
radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \
|
||||
-relief groove -width 2 -command "update_active"
|
||||
radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \
|
||||
-relief groove -width 2 -command "update_active"
|
||||
radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \
|
||||
-relief groove -width 2 -command "update_active"
|
||||
|
||||
option_name $w $mnum $line $text $variable
|
||||
|
||||
global CONFIG_MODULES
|
||||
if {($CONFIG_MODULES == 0)} then {
|
||||
$w.x$line.m configure -state disabled
|
||||
}
|
||||
pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y
|
||||
}
|
||||
|
||||
proc bool {w mnum line text variable} {
|
||||
toggle_switch2 $w $mnum $line $text $variable
|
||||
# $w.x$line.m configure -state disabled
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc tristate {w mnum line text variable } {
|
||||
toggle_switch3 $w $mnum $line $text $variable
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc dep_tristate {w mnum line text variable } {
|
||||
tristate $w $mnum $line $text $variable
|
||||
}
|
||||
|
||||
proc dep_bool {w mnum line text variable } {
|
||||
bool $w $mnum $line $text $variable
|
||||
}
|
||||
|
||||
proc int { w mnum line text variable } {
|
||||
frame $w.x$line
|
||||
entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \
|
||||
-textvariable $variable
|
||||
option_name $w $mnum $line $text $variable
|
||||
pack $w.x$line.x -anchor w -side right -fill y
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc hex { w mnum line text variable } {
|
||||
int $w $mnum $line $text $variable
|
||||
}
|
||||
|
||||
proc istring { w mnum line text variable } {
|
||||
frame $w.x$line
|
||||
entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \
|
||||
-textvariable $variable
|
||||
option_name $w $mnum $line $text $variable
|
||||
pack $w.x$line.x -anchor w -side right -fill y
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc minimenu { w mnum line text variable helpidx } {
|
||||
frame $w.x$line
|
||||
menubutton $w.x$line.x -textvariable $variable -menu \
|
||||
$w.x$line.x.menu -relief raised \
|
||||
-anchor w
|
||||
option_name $w $mnum $line $text $helpidx
|
||||
pack $w.x$line.x -anchor w -side right -fill y
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc menusplit {w m n} {
|
||||
if { $n > 2 } then {
|
||||
update idletasks
|
||||
set menuoptsize [expr [$m yposition 2] - [$m yposition 1]]
|
||||
set maxsize [winfo screenheight $w]
|
||||
set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1]
|
||||
for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} {
|
||||
$m entryconfigure $i -columnbreak 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc menutitle {text menu w} {
|
||||
wm title $w "$text"
|
||||
}
|
||||
|
||||
proc submenu { w mnum line text subnum } {
|
||||
frame $w.x$line
|
||||
button $w.x$line.l -text "" -width 9 -relief groove
|
||||
$w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
|
||||
-activeback [cget $w.x$line.l -bg] -state disabled
|
||||
button $w.x$line.m -text "$text" -relief raised -anchor w \
|
||||
-command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\""
|
||||
pack $w.x$line.l -side left -fill both
|
||||
pack $w.x$line.m -anchor w -side right -fill both -expand on
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc comment {w mnum line text } {
|
||||
frame $w.x$line
|
||||
button $w.x$line.l -text "" -width 15 -relief groove
|
||||
$w.x$line.l configure -activefore [cget $w.x$line.l -fg] \
|
||||
-activeback [cget $w.x$line.l -bg] -state disabled
|
||||
button $w.x$line.m -text "$text" -relief groove -anchor w
|
||||
$w.x$line.m configure -activefore [cget $w.x$line.m -fg] \
|
||||
-activeback [cget $w.x$line.m -bg]
|
||||
pack $w.x$line.l -side left -fill both
|
||||
pack $w.x$line.m -anchor w -side right -fill both -expand on
|
||||
pack $w.x$line -anchor w -fill both -expand on
|
||||
}
|
||||
|
||||
proc readhelp {tag fn} {
|
||||
set message ""
|
||||
set b 0
|
||||
if { [file readable $fn] == 1} then {
|
||||
set fhandle [open $fn r]
|
||||
while {[gets $fhandle inline] >= 0} {
|
||||
if { $b == 0 } {
|
||||
if { [regexp $tag $inline ] } {
|
||||
set b 1
|
||||
set message "$inline:\n"
|
||||
}
|
||||
} else {
|
||||
if { [regexp {^[^ \t]} $inline]} {
|
||||
break
|
||||
}
|
||||
set message "$message\n$inline"
|
||||
}
|
||||
}
|
||||
close $fhandle
|
||||
}
|
||||
return $message
|
||||
}
|
||||
|
||||
proc dohelp {w var parent} {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
|
||||
set filefound 0
|
||||
set found 0
|
||||
set lineno 0
|
||||
|
||||
if { [file readable config.help] == 1} then {
|
||||
set filefound 1
|
||||
# First escape sed regexp special characters in var:
|
||||
set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g]
|
||||
# Now pick out right help text:
|
||||
set message [readhelp $var config.help]
|
||||
set found [expr [string length "$message"] > 0]
|
||||
}
|
||||
|
||||
frame $w.f1
|
||||
pack $w.f1 -fill both -expand on
|
||||
|
||||
# Do the OK button
|
||||
#
|
||||
set oldFocus [focus]
|
||||
frame $w.f2
|
||||
button $w.f2.ok -text "OK" \
|
||||
-width 10 -command "destroy $w; catch {focus $oldFocus}"
|
||||
pack $w.f2.ok -side bottom -pady 6 -anchor n
|
||||
pack $w.f2 -side bottom -padx 10 -anchor s
|
||||
|
||||
scrollbar $w.f1.vscroll -command "$w.f1.canvas yview"
|
||||
pack $w.f1.vscroll -side right -fill y
|
||||
|
||||
canvas $w.f1.canvas -relief flat -borderwidth 0 \
|
||||
-yscrollcommand "$w.f1.vscroll set"
|
||||
frame $w.f1.f
|
||||
pack $w.f1.canvas -side right -fill y -expand on
|
||||
|
||||
if { $found == 0 } then {
|
||||
if { $filefound == 0 } then {
|
||||
message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \
|
||||
"No help available - unable to open file config.help."
|
||||
} else {
|
||||
message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \
|
||||
"No help available for $var"
|
||||
}
|
||||
label $w.f1.bm -bitmap error
|
||||
wm title $w "RTFM"
|
||||
} else {
|
||||
text $w.f1.f.m -width 73 -relief flat -wrap word
|
||||
$w.f1.f.m insert 0.0 $message
|
||||
$w.f1.f.m conf -state disabled -height [$w.f1.f.m index end]
|
||||
|
||||
label $w.f1.bm -bitmap info
|
||||
wm title $w "Configuration help"
|
||||
}
|
||||
pack $w.f1.f.m -side left
|
||||
pack $w.f1.bm $w.f1.f -side left -padx 10
|
||||
|
||||
focus $w
|
||||
set winx [expr [winfo x $parent]+20]
|
||||
set winy [expr [winfo y $parent]+20]
|
||||
wm geometry $w +$winx+$winy
|
||||
set sizok [expr [winfo reqheight $w.f2.ok] + 12]
|
||||
set maxy [expr [winfo screenheight .] * 3 / 4]
|
||||
set canvtotal [winfo reqheight $w.f1.f.m]
|
||||
if [expr $sizok + $canvtotal < $maxy] {
|
||||
set sizy $canvtotal
|
||||
} else {
|
||||
set sizy [expr $maxy - $sizok]
|
||||
}
|
||||
$w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \
|
||||
-scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \
|
||||
[winfo reqheight $w.f1.f.m]"
|
||||
$w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f
|
||||
update idletasks
|
||||
|
||||
set maxy [winfo screenheight .]
|
||||
if [expr $sizok + $canvtotal < $maxy] {
|
||||
set sizy [expr $sizok + $canvtotal]
|
||||
} else {
|
||||
set sizy $maxy
|
||||
}
|
||||
wm maxsize $w [winfo width $w] $sizy
|
||||
}
|
||||
|
||||
bind all <Alt-s> { catch {exec cp -f .config .config.old}; \
|
||||
writeconfig .config config.h; wrapup .wrap }
|
||||
|
||||
proc wrapup {w } {
|
||||
catch {destroy $w}
|
||||
toplevel $w -class Dialog
|
||||
|
||||
global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS
|
||||
message $w.m -width 460 -aspect 300 -relief raised -text \
|
||||
"End of design configuration. "
|
||||
label $w.bm -bitmap info
|
||||
pack $w.bm $w.m -pady 10 -side top -padx 10
|
||||
wm title $w "LEON build instructions"
|
||||
|
||||
set oldFocus [focus]
|
||||
frame $w.f
|
||||
button $w.f.back -text "OK" \
|
||||
-width 10 -command "exit 2"
|
||||
pack $w.f.back -side bottom -pady 10 -anchor s
|
||||
pack $w.f -pady 10 -side top -padx 10 -anchor s
|
||||
focus $w
|
||||
bind $w <Return> "exit 2"
|
||||
global winx; global winy
|
||||
set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30]
|
||||
wm geometry $w +$winx+$winy
|
||||
|
||||
}
|
||||
|
||||
proc unregister_active {num} {
|
||||
global active_menus
|
||||
set index [lsearch -exact $active_menus $num]
|
||||
if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]}
|
||||
}
|
||||
|
||||
proc update_active {} {
|
||||
global active_menus total_menus
|
||||
set max 0
|
||||
if {[llength $active_menus] > 0} then {
|
||||
set max [lindex $active_menus end]
|
||||
update_define [toplevel_menu [lindex $active_menus 0]] $max 0
|
||||
}
|
||||
foreach i $active_menus {
|
||||
if {[winfo exists .menu$i] == 0} then {
|
||||
unregister_active $i
|
||||
} else {
|
||||
update_menu$i
|
||||
}
|
||||
}
|
||||
update_define [expr $max + 1] $total_menus 1
|
||||
update_mainmenu
|
||||
}
|
||||
|
||||
proc configure_entry {w option items} {
|
||||
foreach i $items {
|
||||
$w.$i configure -state $option
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_int {name val default} {
|
||||
if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then {
|
||||
global $name; set $name $default
|
||||
}
|
||||
}
|
||||
|
||||
proc validate_hex {name val default} {
|
||||
if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then {
|
||||
global $name; set $name $default
|
||||
}
|
||||
}
|
||||
|
||||
proc update_define {first last allow_update} {
|
||||
for {set i $first} {$i <= $last} {incr i} {
|
||||
update_define_menu$i
|
||||
if {$allow_update == 1} then update
|
||||
}
|
||||
}
|
||||
|
||||
#
|
||||
# Next set up the particulars for the top level menu, and define a few
|
||||
# buttons which we will stick down at the bottom.
|
||||
#
|
||||
|
||||
frame .f0
|
||||
frame .f0.left
|
||||
frame .f0.middle
|
||||
frame .f0.right
|
||||
|
||||
set active_menus [list]
|
||||
set processed_top_level 0
|
||||
set ARCH sparc
|
||||
931
bin/tkconfig/mkdevice.c
Normal file
931
bin/tkconfig/mkdevice.c
Normal file
|
|
@ -0,0 +1,931 @@
|
|||
/* mkdevice.c, a utility to generate LEON device.vhd from a config file.
|
||||
Written by Jiri Gaisler
|
||||
Copyright Cobham Gaisler, all rights reserved.
|
||||
*/
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
#define VAL(x) strtoul(x,(char **)NULL,0)
|
||||
|
||||
FILE *fp;
|
||||
|
||||
char false[] = "false";
|
||||
char true[] = "true";
|
||||
|
||||
/* Synthesis options */
|
||||
|
||||
char CONFIG_CFG_NAME[16] = "config";
|
||||
char CFG_SYN_TARGET_TECH[128] = "gen";
|
||||
char *CONFIG_SYN_INFER_PADS = false;
|
||||
char *CONFIG_SYN_INFER_PCI_PADS = false;
|
||||
char *CONFIG_SYN_INFER_RAM = false;
|
||||
char *CONFIG_SYN_INFER_ROM = false;
|
||||
char *CONFIG_SYN_INFER_REGF = false;
|
||||
char *CONFIG_SYN_INFER_MULT = false;
|
||||
int CONFIG_SYN_RFTYPE = 1;
|
||||
char CONFIG_TARGET_CLK[128] = "gen";
|
||||
int CONFIG_PLL_CLK_MUL = 1;
|
||||
int CONFIG_PLL_CLK_DIV = 1;
|
||||
char *CONFIG_PCI_CLKDLL = false;
|
||||
char *CONFIG_PCI_SYSCLK = false;
|
||||
|
||||
/* IU options */
|
||||
|
||||
int CONFIG_IU_NWINDOWS = 8;
|
||||
char CFG_IU_MUL_TYPE[16] = "none";
|
||||
char CFG_IU_DIVIDER[16] = "none";
|
||||
char *CONFIG_IU_MUL_MAC = false;
|
||||
char *CONFIG_IU_MULPIPE = false;
|
||||
char *CONFIG_IU_FASTJUMP = false;
|
||||
char *CONFIG_IU_ICCHOLD = false;
|
||||
char *CONFIG_IU_FASTDECODE = false;
|
||||
char *CONFIG_IU_RFPOW = false;
|
||||
int CONFIG_IU_LDELAY = 1;
|
||||
int CONFIG_IU_WATCHPOINTS = 0;
|
||||
|
||||
/* FPU config */
|
||||
|
||||
int CONFIG_FPU_ENABLE = 0;
|
||||
char *CFG_FPU_CORE = "meiko";
|
||||
char *CFG_FPU_IF = "none";
|
||||
int CONFIG_FPU_REGS = 32;
|
||||
int CONFIG_FPU_VER = 0;
|
||||
|
||||
/* CP config */
|
||||
|
||||
char CONFIG_CP_CFG[128] = "cp_none";
|
||||
|
||||
/* cache configuration */
|
||||
|
||||
int CFG_ICACHE_SZ = 2;
|
||||
int CFG_ICACHE_LSZ = 16;
|
||||
int CFG_ICACHE_ASSO = 1;
|
||||
char *CFG_ICACHE_ALGO = "rnd";
|
||||
int CFG_ICACHE_LOCK = 0;
|
||||
int CFG_DCACHE_SZ = 1;
|
||||
int CFG_DCACHE_LSZ = 16;
|
||||
char *CFG_DCACHE_SNOOP = "none";
|
||||
int CFG_DCACHE_ASSO = 1;
|
||||
char *CFG_DCACHE_ALGO = "rnd";
|
||||
int CFG_DCACHE_LOCK = 0;
|
||||
char *CFG_DCACHE_RFAST = false;
|
||||
char *CFG_DCACHE_WFAST = false;
|
||||
char *CFG_DCACHE_LRAM = false;
|
||||
int CFG_DCACHE_LRSZ = 1;
|
||||
int CFG_DCACHE_LRSTART = 0x8f;
|
||||
|
||||
/* MMU config */
|
||||
|
||||
int CFG_MMU_ENABLE = 0;
|
||||
char *CFG_MMU_TYPE = "combinedtlb";
|
||||
char *CFG_MMU_REP = "replruarray";
|
||||
int CFG_MMU_I = 8;
|
||||
int CFG_MMU_D = 8;
|
||||
char *CFG_MMU_DIAG = false;
|
||||
|
||||
/* Memory controller config */
|
||||
|
||||
char *CONFIG_MCTRL_8BIT = false;
|
||||
char *CONFIG_MCTRL_16BIT = false;
|
||||
char *CONFIG_MCTRL_5CS = false;
|
||||
char *CONFIG_MCTRL_WFB = false;
|
||||
char *CONFIG_MCTRL_SDRAM = false;
|
||||
char *CONFIG_MCTRL_SDRAM_INVCLK = false;
|
||||
char *CONFIG_MCTRL_SDRAM_SEPBUS = false;
|
||||
|
||||
/* Peripherals */
|
||||
char *CONFIG_PERI_LCONF = false;
|
||||
char *CONFIG_PERI_AHBSTAT = false;
|
||||
char *CONFIG_PERI_WPROT = false;
|
||||
char *CONFIG_PERI_WDOG = false;
|
||||
char *CONFIG_PERI_IRQ2 = false;
|
||||
|
||||
/* AHB */
|
||||
|
||||
int CONFIG_AHB_DEFMST = 0;
|
||||
char *CONFIG_AHB_SPLIT = false;
|
||||
char *CONFIG_AHBRAM_ENABLE = false;
|
||||
int CFG_AHBRAM_SZ = 4;
|
||||
|
||||
/* Debug */
|
||||
char *CONFIG_DEBUG_UART = false;
|
||||
char *CONFIG_DEBUG_IURF = false;
|
||||
char *CONFIG_DEBUG_FPURF = false;
|
||||
char *CONFIG_DEBUG_NOHALT = false;
|
||||
int CFG_DEBUG_PCLOW = 2;
|
||||
char *CONFIG_DEBUG_RFERR = false;
|
||||
char *CONFIG_DEBUG_CACHEMEMERR = false;
|
||||
|
||||
/* DSU */
|
||||
char *CONFIG_DSU_ENABLE = false;
|
||||
char *CONFIG_DSU_TRACEBUF = false;
|
||||
char *CONFIG_DSU_MIXED_TRACE = false;
|
||||
char *CONFIG_SYN_TRACE_DPRAM = false;
|
||||
int CFG_DSU_TRACE_SZ = 64;
|
||||
|
||||
/* Boot */
|
||||
char *CFG_BOOT_SOURCE = "memory";
|
||||
int CONFIG_BOOT_RWS = 0;
|
||||
int CONFIG_BOOT_WWS = 0;
|
||||
int CONFIG_BOOT_SYSCLK = 25000000;
|
||||
int CONFIG_BOOT_BAUDRATE = 19200;
|
||||
char *CONFIG_BOOT_EXTBAUD = false;
|
||||
int CONFIG_BOOT_PROMABITS = 11;
|
||||
|
||||
/* Ethernet */
|
||||
char *CONFIG_ETH_ENABLE = false;
|
||||
int CONFIG_ETH_TXFIFO = 8;
|
||||
int CONFIG_ETH_RXFIFO = 8;
|
||||
int CONFIG_ETH_BURST = 4;
|
||||
|
||||
/* PCI */
|
||||
char *CFG_PCI_CORE = "none";
|
||||
char *CONFIG_PCI_ENABLE = false;
|
||||
int CONFIG_PCI_VENDORID = 0;
|
||||
int CONFIG_PCI_DEVICEID = 0;
|
||||
int CONFIG_PCI_SUBSYSID = 0;
|
||||
int CONFIG_PCI_REVID = 0;
|
||||
int CONFIG_PCI_CLASSCODE = 0;
|
||||
int CFG_PCI_FIFO = 8;
|
||||
int CFG_PCI_TDEPTH = 256;
|
||||
char *CONFIG_PCI_TRACE = false;
|
||||
char *CONFIG_PCI_PMEPADS = false;
|
||||
char *CONFIG_PCI_P66PAD = false;
|
||||
char *CONFIG_PCI_RESETALL = false;
|
||||
char *CONFIG_PCI_ARBEN = false;
|
||||
int pciahbmst = 0;
|
||||
|
||||
/* FT */
|
||||
|
||||
int CONFIG_FT_ENABLE = 0;
|
||||
char *CONFIG_FT_RF_ENABLE = false;
|
||||
char *CONFIG_FT_RF_PARITY = false;
|
||||
char *CONFIG_FT_RF_EDAC = false;
|
||||
int CONFIG_FT_RF_PARBITS = 0;
|
||||
char *CONFIG_FT_RF_WRFAST = false;
|
||||
char *CONFIG_FT_TMR_REG = false;
|
||||
char *CONFIG_FT_TMR_CLK = false;
|
||||
char *CONFIG_FT_MC = false;
|
||||
char *CONFIG_FT_MEMEDAC = false;
|
||||
char *CONFIG_FT_CACHEMEM_ENABLE = false;
|
||||
int CONFIG_FT_CACHEMEM_PARBITS = 0;
|
||||
char *CONFIG_FT_CACHEMEM_APAR = false;
|
||||
|
||||
|
||||
int dsuen, pcien, ahbram, ethen;
|
||||
char tmps[32];
|
||||
int ahbmst = 1;
|
||||
|
||||
int log2(int x)
|
||||
{
|
||||
int i;
|
||||
|
||||
x--;
|
||||
for (i=0; x!=0; i++) x >>= 1;
|
||||
return(i);
|
||||
}
|
||||
|
||||
main()
|
||||
{
|
||||
|
||||
char lbuf[1024], *value;
|
||||
|
||||
fp = fopen("device.vhd", "w+");
|
||||
if (!fp) {
|
||||
printf("could not open file device.vhd\n");
|
||||
exit(1);
|
||||
}
|
||||
while (!feof(stdin))
|
||||
{
|
||||
lbuf[0] = 0;
|
||||
fgets (lbuf, 1023, stdin);
|
||||
if (strncmp(lbuf, "CONFIG", 6) == 0) {
|
||||
value = strchr(lbuf,'=');
|
||||
value[0] = 0;
|
||||
value++;
|
||||
while ((strlen (value) > 0) &&
|
||||
((value[strlen (value) - 1] == '\n')
|
||||
|| (value[strlen (value) - 1] == '\r')
|
||||
|| (value[strlen (value) - 1] == '"')
|
||||
)) value[strlen (value) - 1] = 0;
|
||||
if ((strlen (value) > 0) && (value[0] == '"')) {
|
||||
value++;
|
||||
}
|
||||
|
||||
/* synthesis options */
|
||||
else if (strcmp("CONFIG_SYN_GENERIC", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "gen");
|
||||
else if (strcmp("CONFIG_SYN_ATC35", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "atc35");
|
||||
else if (strcmp("CONFIG_SYN_ATC25", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "atc25");
|
||||
else if (strcmp("CONFIG_SYN_ATC18", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "atc18");
|
||||
else if (strcmp("CONFIG_SYN_FS90", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "fs90");
|
||||
else if (strcmp("CONFIG_SYN_UMC018", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "umc18");
|
||||
else if (strcmp("CONFIG_SYN_TSMC025", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "tsmc25");
|
||||
else if (strcmp("CONFIG_SYN_PROASIC", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "proasic");
|
||||
else if (strcmp("CONFIG_SYN_AXCEL", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "axcel");
|
||||
else if (strcmp("CONFIG_SYN_VIRTEX", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "virtex");
|
||||
else if (strcmp("CONFIG_SYN_VIRTEX2", lbuf) == 0)
|
||||
strcpy(CFG_SYN_TARGET_TECH, "virtex2");
|
||||
else if (strcmp("CONFIG_SYN_INFER_PADS", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_PADS = true;
|
||||
else if (strcmp("CONFIG_SYN_INFER_PCI_PADS", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_PCI_PADS = true;
|
||||
else if (strcmp("CONFIG_SYN_INFER_RAM", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_RAM = true;
|
||||
else if (strcmp("CONFIG_SYN_INFER_ROM", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_ROM = true;
|
||||
else if (strcmp("CONFIG_SYN_INFER_REGF", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_REGF = true;
|
||||
else if (strcmp("CONFIG_SYN_INFER_MULT", lbuf) == 0)
|
||||
CONFIG_SYN_INFER_MULT = true;
|
||||
else if (strcmp("CONFIG_SYN_RFTYPE", lbuf) == 0)
|
||||
CONFIG_SYN_RFTYPE = 2;
|
||||
else if (strcmp("CONFIG_SYN_TRACE_DPRAM", lbuf) == 0)
|
||||
CONFIG_SYN_TRACE_DPRAM = true;
|
||||
else if (strcmp("CONFIG_CLK_VIRTEX", lbuf) == 0)
|
||||
strcpy(CONFIG_TARGET_CLK, "virtex");
|
||||
else if (strcmp("CONFIG_AXCEL_HCLKBUF", lbuf) == 0)
|
||||
strcpy(CONFIG_TARGET_CLK, "axcel");
|
||||
else if (strcmp("CONFIG_CLKDLL_1_2", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 1; CONFIG_PLL_CLK_DIV = 2;
|
||||
} else if (strcmp("CONFIG_CLKDLL_1_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 1; CONFIG_PLL_CLK_DIV = 1;
|
||||
} else if (strcmp("CONFIG_CLKDLL_2_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 2; CONFIG_PLL_CLK_DIV = 1;
|
||||
} else if (strcmp("CONFIG_CLK_VIRTEX2", lbuf) == 0)
|
||||
strcpy(CONFIG_TARGET_CLK, "virtex2");
|
||||
else if (strcmp("CONFIG_DCM_2_3", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 2; CONFIG_PLL_CLK_DIV = 3;
|
||||
} else if (strcmp("CONFIG_DCM_3_4", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 3; CONFIG_PLL_CLK_DIV = 4;
|
||||
} else if (strcmp("CONFIG_DCM_4_5", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 4; CONFIG_PLL_CLK_DIV = 5;
|
||||
} else if (strcmp("CONFIG_DCM_1_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 2; CONFIG_PLL_CLK_DIV = 2;
|
||||
} else if (strcmp("CONFIG_DCM_5_4", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 5; CONFIG_PLL_CLK_DIV = 4;
|
||||
} else if (strcmp("CONFIG_DCM_4_3", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 4; CONFIG_PLL_CLK_DIV = 3;
|
||||
} else if (strcmp("CONFIG_DCM_3_2", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 3; CONFIG_PLL_CLK_DIV = 2;
|
||||
} else if (strcmp("CONFIG_DCM_5_3", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 5; CONFIG_PLL_CLK_DIV = 3;
|
||||
} else if (strcmp("CONFIG_DCM_2_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 2; CONFIG_PLL_CLK_DIV = 1;
|
||||
} else if (strcmp("CONFIG_DCM_3_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 3; CONFIG_PLL_CLK_DIV = 1;
|
||||
} else if (strcmp("CONFIG_DCM_4_1", lbuf) == 0) {
|
||||
CONFIG_PLL_CLK_MUL = 4; CONFIG_PLL_CLK_DIV = 1;
|
||||
} else if (strcmp("CONFIG_PCI_DLL", lbuf) == 0)
|
||||
CONFIG_PCI_CLKDLL = true;
|
||||
else if (strcmp("CONFIG_PCI_SYSCLK", lbuf) == 0)
|
||||
CONFIG_PCI_SYSCLK = true;
|
||||
/* IU options */
|
||||
else if (strcmp("CONFIG_IU_NWINDOWS", lbuf) == 0) {
|
||||
CONFIG_IU_NWINDOWS = VAL(value);
|
||||
if ((CONFIG_IU_NWINDOWS > 32) || (CONFIG_IU_NWINDOWS < 1))
|
||||
CONFIG_IU_NWINDOWS = 8;
|
||||
} else if (strcmp("CONFIG_IU_V8MULDIV", lbuf) == 0)
|
||||
strcpy(CFG_IU_DIVIDER, "radix2");
|
||||
else if (strcmp("CONFIG_IU_MUL_LATENCY_1", lbuf) == 0)
|
||||
strcpy(CFG_IU_MUL_TYPE, "m32x32");
|
||||
else if (strcmp("CONFIG_IU_MUL_LATENCY_2", lbuf) == 0)
|
||||
strcpy(CFG_IU_MUL_TYPE, "m32x16");
|
||||
else if (strcmp("CONFIG_IU_MUL_LATENCY_4", lbuf) == 0)
|
||||
strcpy(CFG_IU_MUL_TYPE, "m16x16");
|
||||
else if (strcmp("CONFIG_IU_MUL_LATENCY_5", lbuf) == 0) {
|
||||
strcpy(CFG_IU_MUL_TYPE, "m16x16");
|
||||
CONFIG_IU_MULPIPE = true;
|
||||
}
|
||||
else if (strcmp("CONFIG_IU_MUL_LATENCY_35", lbuf) == 0)
|
||||
strcpy(CFG_IU_MUL_TYPE, "iterative");
|
||||
else if (strcmp("CONFIG_IU_MUL_MAC", lbuf) == 0) {
|
||||
strcpy(CFG_IU_MUL_TYPE, "m16x16");
|
||||
CONFIG_IU_MUL_MAC = true;
|
||||
}
|
||||
else if (strcmp("CONFIG_IU_FASTJUMP", lbuf) == 0)
|
||||
CONFIG_IU_FASTJUMP = true;
|
||||
else if (strcmp("CONFIG_IU_FASTDECODE", lbuf) == 0)
|
||||
CONFIG_IU_FASTDECODE = true;
|
||||
else if (strcmp("CONFIG_IU_RFPOW", lbuf) == 0)
|
||||
CONFIG_IU_RFPOW = true;
|
||||
else if (strcmp("CONFIG_IU_ICCHOLD", lbuf) == 0)
|
||||
CONFIG_IU_ICCHOLD = true;
|
||||
else if (strcmp("CONFIG_IU_LDELAY", lbuf) == 0) {
|
||||
CONFIG_IU_LDELAY = VAL(value);
|
||||
if ((CONFIG_IU_LDELAY > 2) || (CONFIG_IU_LDELAY < 1))
|
||||
CONFIG_IU_LDELAY = 2;
|
||||
} else if (strcmp("CONFIG_IU_WATCHPOINTS", lbuf) == 0) {
|
||||
CONFIG_IU_WATCHPOINTS = VAL(value);
|
||||
if ((CONFIG_IU_WATCHPOINTS > 4) || (CONFIG_IU_WATCHPOINTS < 0))
|
||||
CONFIG_IU_WATCHPOINTS = 0;
|
||||
/* FPU config */
|
||||
} else if (strcmp("CONFIG_FPU_ENABLE", lbuf) == 0)
|
||||
CONFIG_FPU_ENABLE = 1;
|
||||
else if (strcmp("CONFIG_FPU_GRFPU", lbuf) == 0) {
|
||||
CFG_FPU_CORE = "grfpu"; CFG_FPU_IF = "parallel";
|
||||
CONFIG_FPU_REGS = 0;
|
||||
} else if (strcmp("CONFIG_FPU_MEIKO", lbuf) == 0) {
|
||||
CFG_FPU_CORE = "meiko"; CFG_FPU_IF = "serial";
|
||||
} else if (strcmp("CONFIG_FPU_LTH", lbuf) == 0) {
|
||||
CFG_FPU_CORE = "lth"; CFG_FPU_IF = "serial";
|
||||
} else if (strcmp("CONFIG_FPU_VER", lbuf) == 0)
|
||||
CONFIG_FPU_VER = VAL(value) & 0x07;
|
||||
/* CP config */
|
||||
else if (strcmp("CONFIG_CP_ENABLE", lbuf) == 0) {}
|
||||
else if (strcmp("CONFIG_CP_CFG", lbuf) == 0)
|
||||
strcpy(CONFIG_CP_CFG, value);
|
||||
/* cache config */
|
||||
else if (strcmp("CONFIG_ICACHE_ASSO1", lbuf) == 0)
|
||||
CFG_ICACHE_ASSO = 1;
|
||||
else if (strcmp("CONFIG_ICACHE_ASSO2", lbuf) == 0)
|
||||
CFG_ICACHE_ASSO = 2;
|
||||
else if (strcmp("CONFIG_ICACHE_ASSO3", lbuf) == 0)
|
||||
CFG_ICACHE_ASSO = 3;
|
||||
else if (strcmp("CONFIG_ICACHE_ASSO4", lbuf) == 0)
|
||||
CFG_ICACHE_ASSO = 4;
|
||||
else if (strcmp("CONFIG_ICACHE_ALGORND", lbuf) == 0)
|
||||
CFG_ICACHE_ALGO = "rnd";
|
||||
else if (strcmp("CONFIG_ICACHE_ALGOLRR", lbuf) == 0)
|
||||
CFG_ICACHE_ALGO = "lrr";
|
||||
else if (strcmp("CONFIG_ICACHE_ALGOLRU", lbuf) == 0)
|
||||
CFG_ICACHE_ALGO = "lru";
|
||||
else if (strcmp("CONFIG_ICACHE_LOCK", lbuf) == 0)
|
||||
CFG_ICACHE_LOCK = 1;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ1", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 1;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ2", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 2;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ4", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 4;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ8", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 8;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ16", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 16;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ32", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 32;
|
||||
else if (strcmp("CONFIG_ICACHE_SZ64", lbuf) == 0)
|
||||
CFG_ICACHE_SZ = 64;
|
||||
else if (strcmp("CONFIG_ICACHE_LZ16", lbuf) == 0)
|
||||
CFG_ICACHE_LSZ = 16;
|
||||
else if (strcmp("CONFIG_ICACHE_LZ32", lbuf) == 0)
|
||||
CFG_ICACHE_LSZ = 32;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ1", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 1;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ2", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 2;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ4", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 4;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ8", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 8;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ16", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 16;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ32", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 32;
|
||||
else if (strcmp("CONFIG_DCACHE_SZ64", lbuf) == 0)
|
||||
CFG_DCACHE_SZ = 64;
|
||||
else if (strcmp("CONFIG_DCACHE_LZ16", lbuf) == 0)
|
||||
CFG_DCACHE_LSZ = 16;
|
||||
else if (strcmp("CONFIG_DCACHE_LZ32", lbuf) == 0)
|
||||
CFG_DCACHE_LSZ = 32;
|
||||
else if (strcmp("CONFIG_DCACHE_SNOOP_SLOW", lbuf) == 0)
|
||||
CFG_DCACHE_SNOOP = "slow";
|
||||
else if (strcmp("CONFIG_DCACHE_SNOOP_FAST", lbuf) == 0)
|
||||
CFG_DCACHE_SNOOP = "fast";
|
||||
else if (strcmp("CONFIG_DCACHE_SNOOP", lbuf) == 0) {}
|
||||
else if (strcmp("CONFIG_DCACHE_ASSO1", lbuf) == 0)
|
||||
CFG_DCACHE_ASSO = 1;
|
||||
else if (strcmp("CONFIG_DCACHE_ASSO2", lbuf) == 0)
|
||||
CFG_DCACHE_ASSO = 2;
|
||||
else if (strcmp("CONFIG_DCACHE_ASSO3", lbuf) == 0)
|
||||
CFG_DCACHE_ASSO = 3;
|
||||
else if (strcmp("CONFIG_DCACHE_ASSO4", lbuf) == 0)
|
||||
CFG_DCACHE_ASSO = 4;
|
||||
else if (strcmp("CONFIG_DCACHE_ALGORND", lbuf) == 0)
|
||||
CFG_DCACHE_ALGO = "rnd";
|
||||
else if (strcmp("CONFIG_DCACHE_ALGOLRR", lbuf) == 0)
|
||||
CFG_DCACHE_ALGO = "lrr";
|
||||
else if (strcmp("CONFIG_DCACHE_ALGOLRU", lbuf) == 0)
|
||||
CFG_DCACHE_ALGO = "lru";
|
||||
else if (strcmp("CONFIG_DCACHE_LOCK", lbuf) == 0)
|
||||
CFG_DCACHE_LOCK = 1;
|
||||
else if (strcmp("CONFIG_DCACHE_RFAST", lbuf) == 0)
|
||||
CFG_DCACHE_RFAST = true;
|
||||
else if (strcmp("CONFIG_DCACHE_WFAST", lbuf) == 0)
|
||||
CFG_DCACHE_WFAST = true;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM", lbuf) == 0)
|
||||
CFG_DCACHE_LRAM = true;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ1", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 1;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ2", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 2;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ4", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 4;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ8", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 8;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ16", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 16;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ32", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 32;
|
||||
else if (strcmp("CONFIG_DCACHE_LRAM_SZ64", lbuf) == 0)
|
||||
CFG_DCACHE_LRSZ = 64;
|
||||
else if (strcmp("CONFIG_DCACHE_LRSTART", lbuf) == 0) {
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CFG_DCACHE_LRSTART = VAL(tmps) & 0x0ff;
|
||||
} else if (strcmp("CONFIG_MMU_ENABLE", lbuf) == 0)
|
||||
CFG_MMU_ENABLE = 1;
|
||||
else if (strcmp("CONFIG_MMU_DIAG", lbuf) == 0)
|
||||
CFG_MMU_DIAG = true;
|
||||
else if (strcmp("CONFIG_MMU_SPLIT", lbuf) == 0)
|
||||
CFG_MMU_TYPE = "splittlb";
|
||||
else if (strcmp("CONFIG_MMU_COMBINED", lbuf) == 0)
|
||||
CFG_MMU_TYPE = "combinedtlb";
|
||||
else if (strcmp("CONFIG_MMU_REPARRAY", lbuf) == 0)
|
||||
CFG_MMU_REP = "replruarray";
|
||||
else if (strcmp("CONFIG_MMU_REPINCREMENT", lbuf) == 0)
|
||||
CFG_MMU_REP = "repincrement";
|
||||
else if (strcmp("CONFIG_MMU_I2", lbuf) == 0)
|
||||
CFG_MMU_I = 2;
|
||||
else if (strcmp("CONFIG_MMU_I4", lbuf) == 0)
|
||||
CFG_MMU_I = 4;
|
||||
else if (strcmp("CONFIG_MMU_I8", lbuf) == 0)
|
||||
CFG_MMU_I = 8;
|
||||
else if (strcmp("CONFIG_MMU_I16", lbuf) == 0)
|
||||
CFG_MMU_I = 16;
|
||||
else if (strcmp("CONFIG_MMU_I32", lbuf) == 0)
|
||||
CFG_MMU_I = 32;
|
||||
else if (strcmp("CONFIG_MMU_D1", lbuf) == 0)
|
||||
CFG_MMU_D = 1;
|
||||
else if (strcmp("CONFIG_MMU_D2", lbuf) == 0)
|
||||
CFG_MMU_D = 2;
|
||||
else if (strcmp("CONFIG_MMU_D4", lbuf) == 0)
|
||||
CFG_MMU_D = 4;
|
||||
else if (strcmp("CONFIG_MMU_D8", lbuf) == 0)
|
||||
CFG_MMU_D = 8;
|
||||
else if (strcmp("CONFIG_MMU_D16", lbuf) == 0)
|
||||
CFG_MMU_D = 16;
|
||||
else if (strcmp("CONFIG_MMU_D32", lbuf) == 0)
|
||||
CFG_MMU_D = 32;
|
||||
|
||||
/* CP config */
|
||||
else if (strcmp("CONFIG_CP_ENABLE", lbuf) == 0) {}
|
||||
/* Memory controller */
|
||||
else if (strcmp("CONFIG_MCTRL_8BIT", lbuf) == 0)
|
||||
CONFIG_MCTRL_8BIT = true;
|
||||
else if (strcmp("CONFIG_MCTRL_16BIT", lbuf) == 0)
|
||||
CONFIG_MCTRL_16BIT = true;
|
||||
else if (strcmp("CONFIG_MCTRL_5CS", lbuf) == 0)
|
||||
CONFIG_MCTRL_5CS = true;
|
||||
else if (strcmp("CONFIG_MCTRL_WFB", lbuf) == 0)
|
||||
CONFIG_MCTRL_WFB = true;
|
||||
else if (strcmp("CONFIG_MCTRL_SDRAM", lbuf) == 0)
|
||||
CONFIG_MCTRL_SDRAM = true;
|
||||
else if (strcmp("CONFIG_MCTRL_SDRAM_INVCLK", lbuf) == 0)
|
||||
CONFIG_MCTRL_SDRAM_INVCLK = true;
|
||||
else if (strcmp("CONFIG_MCTRL_SDRAM_SEPBUS", lbuf) == 0)
|
||||
CONFIG_MCTRL_SDRAM_SEPBUS = true;
|
||||
/* Peripherals */
|
||||
else if (strcmp("CONFIG_PERI_LCONF", lbuf) == 0)
|
||||
CONFIG_PERI_LCONF = true;
|
||||
else if (strcmp("CONFIG_PERI_AHBSTAT", lbuf) == 0)
|
||||
CONFIG_PERI_AHBSTAT = true;
|
||||
else if (strcmp("CONFIG_PERI_WPROT", lbuf) == 0)
|
||||
CONFIG_PERI_WPROT = true;
|
||||
else if (strcmp("CONFIG_PERI_WDOG", lbuf) == 0)
|
||||
CONFIG_PERI_WDOG = true;
|
||||
else if (strcmp("CONFIG_PERI_IRQ2", lbuf) == 0)
|
||||
CONFIG_PERI_IRQ2 = true;
|
||||
/* AHB */
|
||||
else if (strcmp("CONFIG_AHB_DEFMST", lbuf) == 0)
|
||||
CONFIG_AHB_DEFMST = VAL(value);
|
||||
else if (strcmp("CONFIG_AHB_SPLIT", lbuf) == 0)
|
||||
CONFIG_AHB_SPLIT = true;
|
||||
else if (strcmp("CONFIG_AHBRAM_ENABLE", lbuf) == 0)
|
||||
CONFIG_AHBRAM_ENABLE = true;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ1", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 1;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ2", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 2;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ4", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 3;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ8", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 4;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ16", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 5;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ32", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 6;
|
||||
else if (strcmp("CONFIG_AHBRAM_SZ64", lbuf) == 0)
|
||||
CFG_AHBRAM_SZ = 7;
|
||||
/* Debug */
|
||||
else if (strcmp("CONFIG_DEBUG_UART", lbuf) == 0)
|
||||
CONFIG_DEBUG_UART = true;
|
||||
else if (strcmp("CONFIG_DEBUG_IURF", lbuf) == 0)
|
||||
CONFIG_DEBUG_IURF = true;
|
||||
else if (strcmp("CONFIG_DEBUG_FPURF", lbuf) == 0)
|
||||
CONFIG_DEBUG_FPURF = true;
|
||||
else if (strcmp("CONFIG_DEBUG_NOHALT", lbuf) == 0)
|
||||
CONFIG_DEBUG_NOHALT = true;
|
||||
else if (strcmp("CONFIG_DEBUG_PC32", lbuf) == 0)
|
||||
CFG_DEBUG_PCLOW = 0;
|
||||
else if (strcmp("CONFIG_DEBUG_RFERR", lbuf) == 0)
|
||||
CONFIG_DEBUG_RFERR = true;
|
||||
else if (strcmp("CONFIG_DEBUG_CACHEMEMERR", lbuf) == 0)
|
||||
CONFIG_DEBUG_CACHEMEMERR = true;
|
||||
/* DSU */
|
||||
else if (strcmp("CONFIG_DSU_ENABLE", lbuf) == 0)
|
||||
{CONFIG_DSU_ENABLE = true; ahbmst ++;}
|
||||
else if (strcmp("CONFIG_DSU_TRACEBUF", lbuf) == 0)
|
||||
CONFIG_DSU_TRACEBUF = true;
|
||||
else if (strcmp("CONFIG_DSU_MIXED_TRACE", lbuf) == 0)
|
||||
CONFIG_DSU_MIXED_TRACE = true;
|
||||
else if (strcmp("CONFIG_DSU_TRACESZ64", lbuf) == 0)
|
||||
CFG_DSU_TRACE_SZ = 64;
|
||||
else if (strcmp("CONFIG_DSU_TRACESZ128", lbuf) == 0)
|
||||
CFG_DSU_TRACE_SZ = 128;
|
||||
else if (strcmp("CONFIG_DSU_TRACESZ256", lbuf) == 0)
|
||||
CFG_DSU_TRACE_SZ = 256;
|
||||
else if (strcmp("CONFIG_DSU_TRACESZ512", lbuf) == 0)
|
||||
CFG_DSU_TRACE_SZ = 512;
|
||||
else if (strcmp("CONFIG_DSU_TRACESZ1024", lbuf) == 0)
|
||||
CFG_DSU_TRACE_SZ = 1024;
|
||||
/* Boot */
|
||||
else if (strcmp("CONFIG_BOOT_EXTPROM", lbuf) == 0)
|
||||
CFG_BOOT_SOURCE = "memory";
|
||||
else if (strcmp("CONFIG_BOOT_INTPROM", lbuf) == 0)
|
||||
CFG_BOOT_SOURCE = "prom";
|
||||
else if (strcmp("CONFIG_BOOT_MIXPROM", lbuf) == 0)
|
||||
CFG_BOOT_SOURCE = "dual";
|
||||
else if (strcmp("CONFIG_BOOT_RWS", lbuf) == 0)
|
||||
CONFIG_BOOT_RWS = VAL(value) & 0x3;
|
||||
else if (strcmp("CONFIG_BOOT_WWS", lbuf) == 0)
|
||||
CONFIG_BOOT_WWS = VAL(value) & 0x3;
|
||||
else if (strcmp("CONFIG_BOOT_SYSCLK", lbuf) == 0)
|
||||
CONFIG_BOOT_SYSCLK = VAL(value);
|
||||
else if (strcmp("CONFIG_BOOT_BAUDRATE", lbuf) == 0)
|
||||
CONFIG_BOOT_BAUDRATE = VAL(value) & 0x3fffff;
|
||||
else if (strcmp("CONFIG_BOOT_EXTBAUD", lbuf) == 0)
|
||||
CONFIG_BOOT_EXTBAUD = true;
|
||||
else if (strcmp("CONFIG_BOOT_PROMABITS", lbuf) == 0)
|
||||
CONFIG_BOOT_PROMABITS = VAL(value) & 0x3f;
|
||||
/* Ethernet */
|
||||
else if (strcmp("CONFIG_ETH_ENABLE", lbuf) == 0)
|
||||
{ CONFIG_ETH_ENABLE = true; ahbmst++;}
|
||||
else if (strcmp("CONFIG_ETH_TXFIFO", lbuf) == 0)
|
||||
{ CONFIG_ETH_TXFIFO = VAL(value) & 0x0ffff; }
|
||||
else if (strcmp("CONFIG_ETH_RXFIFO", lbuf) == 0)
|
||||
{ CONFIG_ETH_RXFIFO = VAL(value) & 0x0ffff; }
|
||||
else if (strcmp("CONFIG_ETH_BURST", lbuf) == 0)
|
||||
{ CONFIG_ETH_BURST = VAL(value) & 0x0ffff; }
|
||||
/* PCI */
|
||||
else if (strcmp("CONFIG_PCI_ENABLE", lbuf) == 0)
|
||||
CONFIG_PCI_ENABLE = true;
|
||||
else if (strcmp("CONFIG_PCI_SIMPLE_TARGET", lbuf) == 0)
|
||||
{
|
||||
CFG_PCI_CORE = "simple_target"; ahbmst++; pciahbmst = 1;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_FAST_TARGET", lbuf) == 0)
|
||||
{
|
||||
CFG_PCI_CORE = "fast_target"; ahbmst++; pciahbmst = 1;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_MASTER_TARGET", lbuf) == 0)
|
||||
{
|
||||
CFG_PCI_CORE = "master_target"; ahbmst++; pciahbmst = 1;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_VENDORID", lbuf) == 0)
|
||||
{
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CONFIG_PCI_VENDORID = VAL(tmps) & 0x0ffff;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_DEVICEID", lbuf) == 0)
|
||||
{
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CONFIG_PCI_DEVICEID = VAL(tmps) & 0x0ffff;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_SUBSYSID", lbuf) == 0)
|
||||
{
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CONFIG_PCI_SUBSYSID = VAL(tmps) & 0x0ffff;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_REVID", lbuf) == 0)
|
||||
{
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CONFIG_PCI_REVID = VAL(tmps) & 0x0ff;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_CLASSCODE", lbuf) == 0)
|
||||
{
|
||||
strcpy(tmps, "0x"); strcat(tmps, value);
|
||||
CONFIG_PCI_CLASSCODE = VAL(tmps) & 0x0ffffff;
|
||||
}
|
||||
else if (strcmp("CONFIG_PCI_TRACE256", lbuf) == 0)
|
||||
CFG_PCI_TDEPTH = 8;
|
||||
else if (strcmp("CONFIG_PCI_TRACE512", lbuf) == 0)
|
||||
CFG_PCI_TDEPTH = 9;
|
||||
else if (strcmp("CONFIG_PCI_TRACE1024", lbuf) == 0)
|
||||
CFG_PCI_TDEPTH = 10;
|
||||
else if (strcmp("CONFIG_PCI_TRACE2048", lbuf) == 0)
|
||||
CFG_PCI_TDEPTH = 11;
|
||||
else if (strcmp("CONFIG_PCI_TRACE4096", lbuf) == 0)
|
||||
CFG_PCI_TDEPTH = 12;
|
||||
else if (strcmp("CONFIG_PCI_TRACE", lbuf) == 0)
|
||||
CONFIG_PCI_TRACE = true;
|
||||
else if (strcmp("CONFIG_PCI_FIFO2", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 1;
|
||||
else if (strcmp("CONFIG_PCI_FIFO4", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 2;
|
||||
else if (strcmp("CONFIG_PCI_FIFO8", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 3;
|
||||
else if (strcmp("CONFIG_PCI_FIFO16", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 4;
|
||||
else if (strcmp("CONFIG_PCI_FIFO32", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 5;
|
||||
else if (strcmp("CONFIG_PCI_FIFO64", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 6;
|
||||
else if (strcmp("CONFIG_PCI_FIFO128", lbuf) == 0)
|
||||
CFG_PCI_FIFO = 7;
|
||||
else if (strcmp("CONFIG_PCI_PMEPADS", lbuf) == 0)
|
||||
CONFIG_PCI_PMEPADS = true;
|
||||
else if (strcmp("CONFIG_PCI_P66PAD", lbuf) == 0)
|
||||
CONFIG_PCI_P66PAD = true;
|
||||
else if (strcmp("CONFIG_PCI_RESETALL", lbuf) == 0)
|
||||
CONFIG_PCI_RESETALL = true;
|
||||
else if (strcmp("CONFIG_PCI_ARBEN", lbuf) == 0)
|
||||
CONFIG_PCI_ARBEN = true;
|
||||
/* FT */
|
||||
else if (strcmp("CONFIG_FT_ENABLE", lbuf) == 0)
|
||||
CONFIG_FT_ENABLE = 1;
|
||||
else if (strcmp("CONFIG_FT_RF_ENABLE", lbuf) == 0)
|
||||
CONFIG_FT_RF_ENABLE = true;
|
||||
else if (strcmp("CONFIG_FT_RF_PARITY", lbuf) == 0)
|
||||
CONFIG_FT_RF_PARITY = true;
|
||||
else if (strcmp("CONFIG_FT_RF_EDAC", lbuf) == 0)
|
||||
CONFIG_FT_RF_PARBITS = 7;
|
||||
else if (strcmp("CONFIG_FT_RF_PARBITS", lbuf) == 0)
|
||||
CONFIG_FT_RF_PARBITS = abs(VAL(value) % 3) ;
|
||||
else if (strcmp("CONFIG_FT_RF_WRFAST", lbuf) == 0)
|
||||
CONFIG_FT_RF_WRFAST = true;
|
||||
else if (strcmp("CONFIG_FT_TMR_REG", lbuf) == 0)
|
||||
CONFIG_FT_TMR_REG = true;
|
||||
else if (strcmp("CONFIG_FT_TMR_CLK", lbuf) == 0)
|
||||
CONFIG_FT_TMR_CLK = true;
|
||||
else if (strcmp("CONFIG_FT_MC", lbuf) == 0)
|
||||
CONFIG_FT_MC = true;
|
||||
else if (strcmp("CONFIG_FT_MEMEDAC", lbuf) == 0)
|
||||
CONFIG_FT_MEMEDAC = true;
|
||||
else if (strcmp("CONFIG_FT_CACHEMEM_ENABLE", lbuf) == 0)
|
||||
CONFIG_FT_CACHEMEM_ENABLE = true;
|
||||
else if (strcmp("CONFIG_FT_CACHEMEM_PARBITS", lbuf) == 0)
|
||||
CONFIG_FT_CACHEMEM_PARBITS = abs(VAL(value) % 3) ;
|
||||
else if (strcmp("CONFIG_FT_CACHEMEM_APAR", lbuf) == 0)
|
||||
CONFIG_FT_CACHEMEM_APAR = true;
|
||||
else if (strcmp("CONFIG_FT_CACHEMEM_ENABLE", lbuf) == 0) {}
|
||||
else
|
||||
fprintf(stderr, "unknown config option: %s = %s\n", lbuf, value);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
fprintf(fp, "\n\
|
||||
----------------------------------------------------------------------------\n\
|
||||
-- This file is a part of the LEON VHDL model\n\
|
||||
-- Copyright (C) 1999 European Space Agency (ESA)\n\
|
||||
--\n\
|
||||
-- This library is free software; you can redistribute it and/or\n\
|
||||
-- modify it under the terms of the GNU Lesser General Public\n\
|
||||
-- License as published by the Free Software Foundation; either\n\
|
||||
-- version 2 of the License, or (at your option) any later version.\n\
|
||||
--\n\
|
||||
-- See the file COPYING.LGPL for the full details of the license.\n\
|
||||
\n\
|
||||
\n\
|
||||
-----------------------------------------------------------------------------\n\
|
||||
-- Entity: device\n\
|
||||
-- File: device.vhd\n\
|
||||
-- Author: Jiri Gaisler - Gaisler Research\n\
|
||||
-- Description: package to select current device configuration\n\
|
||||
------------------------------------------------------------------------------\n\
|
||||
\n\
|
||||
library IEEE;\n\
|
||||
use IEEE.std_logic_1164.all;\n\
|
||||
use work.target.all;\n\
|
||||
\n\
|
||||
package device is\n\
|
||||
\n\
|
||||
-----------------------------------------------------------------------------\n\
|
||||
-- Automatically generated by tkonfig/mkdevice\n\
|
||||
-----------------------------------------------------------------------------\n\
|
||||
");
|
||||
|
||||
if (CONFIG_AHBRAM_ENABLE == true) ahbram = 4; else ahbram = 0;
|
||||
if (CONFIG_DSU_ENABLE == true) dsuen = 2; else dsuen = 7;
|
||||
if (CONFIG_PCI_ENABLE == true) pcien = 3; else pcien = 7;
|
||||
if (CONFIG_ETH_ENABLE == true) ethen = 5; else ethen = 7;
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant syn_%s : syn_config_type := ( \n\
|
||||
targettech => %s , infer_pads => %s, infer_pci => %s,\n\
|
||||
infer_ram => %s, infer_regf => %s, infer_rom => %s,\n\
|
||||
infer_mult => %s, rftype => %d, targetclk => %s,\n\
|
||||
clk_mul => %d, clk_div => %d, pci_dll => %s, pci_sysclk => %s );\n\
|
||||
", CONFIG_CFG_NAME, CFG_SYN_TARGET_TECH, CONFIG_SYN_INFER_PADS, CONFIG_SYN_INFER_PCI_PADS, \
|
||||
CONFIG_SYN_INFER_RAM, CONFIG_SYN_INFER_REGF, CONFIG_SYN_INFER_ROM,\
|
||||
CONFIG_SYN_INFER_MULT, CONFIG_SYN_RFTYPE, CONFIG_TARGET_CLK,
|
||||
CONFIG_PLL_CLK_MUL, CONFIG_PLL_CLK_DIV, CONFIG_PCI_CLKDLL,
|
||||
CONFIG_PCI_SYSCLK);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant iu_%s : iu_config_type := (\n\
|
||||
nwindows => %d, multiplier => %s, mulpipe => %s, \n\
|
||||
divider => %s, mac => %s, fpuen => %d, cpen => false, \n\
|
||||
fastjump => %s, icchold => %s, lddelay => %d, fastdecode => %s, \n\
|
||||
rflowpow => %s, watchpoints => %d);\n\
|
||||
", CONFIG_CFG_NAME, CONFIG_IU_NWINDOWS, CFG_IU_MUL_TYPE, CONFIG_IU_MULPIPE,
|
||||
CFG_IU_DIVIDER, CONFIG_IU_MUL_MAC, CONFIG_FPU_ENABLE, CONFIG_IU_FASTJUMP,
|
||||
CONFIG_IU_ICCHOLD, CONFIG_IU_LDELAY, CONFIG_IU_FASTDECODE, CONFIG_IU_RFPOW,
|
||||
CONFIG_IU_WATCHPOINTS);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant fpu_%s : fpu_config_type := \n\
|
||||
(core => %s, interface => %s, fregs => %d, version => %d);\n\
|
||||
", CONFIG_CFG_NAME, CFG_FPU_CORE, CFG_FPU_IF, CONFIG_FPU_ENABLE*CONFIG_FPU_REGS,
|
||||
CONFIG_FPU_VER);
|
||||
|
||||
/*
|
||||
if ((CFG_ICACHE_SZ > 4) && (CFG_MMU_TYPE != false)) {
|
||||
CFG_ICACHE_SZ = 4;
|
||||
printf("Warning: maximum iset size 4 kbyte when MMU enabled (fixed)\n");
|
||||
}
|
||||
if ((CFG_DCACHE_SZ > 4) && (CFG_MMU_TYPE != false)) {
|
||||
CFG_DCACHE_SZ = 4;
|
||||
printf("Warning: maximum dset size 4 kbyte when MMU enabled (fixed)\n");
|
||||
}
|
||||
*/
|
||||
|
||||
if ((strcmp(CFG_ICACHE_ALGO,"lrr") == 0) && (CFG_ICACHE_ASSO > 2))
|
||||
CFG_ICACHE_ALGO = "rnd";
|
||||
if ((strcmp(CFG_DCACHE_ALGO,"lrr") == 0) && (CFG_DCACHE_ASSO > 2))
|
||||
CFG_DCACHE_ALGO = "rnd";
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant cache_%s : cache_config_type := (\n\
|
||||
isets => %d, isetsize => %d, ilinesize => %d, ireplace => %s, ilock => %d,\n\
|
||||
dsets => %d, dsetsize => %d, dlinesize => %d, dreplace => %s, dlock => %d,\n\
|
||||
dsnoop => %s, drfast => %s, dwfast => %s, dlram => %s, \n\
|
||||
dlramsize => %d, dlramaddr => 16#%02X#);\n\
|
||||
", CONFIG_CFG_NAME,
|
||||
CFG_ICACHE_ASSO, CFG_ICACHE_SZ, CFG_ICACHE_LSZ/4, CFG_ICACHE_ALGO, CFG_ICACHE_LOCK,
|
||||
CFG_DCACHE_ASSO, CFG_DCACHE_SZ, CFG_DCACHE_LSZ/4, CFG_DCACHE_ALGO, CFG_DCACHE_LOCK,
|
||||
CFG_DCACHE_SNOOP, CFG_DCACHE_RFAST, CFG_DCACHE_WFAST, CFG_DCACHE_LRAM,
|
||||
CFG_DCACHE_LRSZ, CFG_DCACHE_LRSTART);
|
||||
|
||||
fprintf (fp, "\n\
|
||||
constant mmu_%s : mmu_config_type := (\n\
|
||||
enable => %d, itlbnum => %d, dtlbnum => %d, tlb_type => %s, \n\
|
||||
tlb_rep => %s, tlb_diag => %s );\n\
|
||||
", CONFIG_CFG_NAME, CFG_MMU_ENABLE, CFG_MMU_I, CFG_MMU_D,
|
||||
CFG_MMU_TYPE, CFG_MMU_REP, CFG_MMU_DIAG);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant ahbrange_config : ahbslv_addr_type := \n\
|
||||
(0,0,0,0,0,0,%d,0,1,%d,%d,%d,%d,%d,%d,%d);\n\
|
||||
", ahbram, dsuen, pcien, ethen, pcien, pcien, pcien, pcien);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant ahb_%s : ahb_config_type := ( masters => %d, defmst => %d,\n\
|
||||
split => %s, testmod => false);\n\
|
||||
", CONFIG_CFG_NAME, ahbmst, CONFIG_AHB_DEFMST % ahbmst, CONFIG_AHB_SPLIT);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant mctrl_%s : mctrl_config_type := (\n\
|
||||
bus8en => %s, bus16en => %s, wendfb => %s, ramsel5 => %s,\n\
|
||||
sdramen => %s, sdinvclk => %s, sdsepbus => %s);\n\
|
||||
", CONFIG_CFG_NAME, CONFIG_MCTRL_8BIT, CONFIG_MCTRL_16BIT, CONFIG_MCTRL_WFB,
|
||||
CONFIG_MCTRL_5CS,
|
||||
CONFIG_MCTRL_SDRAM, CONFIG_MCTRL_SDRAM_INVCLK, CONFIG_MCTRL_SDRAM_SEPBUS);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant peri_%s : peri_config_type := (\n\
|
||||
cfgreg => %s, ahbstat => %s, wprot => %s, wdog => %s, \n\
|
||||
irq2en => %s, ahbram => %s, ahbrambits => %d, ethen => %s );\n\
|
||||
", CONFIG_CFG_NAME, CONFIG_PERI_LCONF, CONFIG_PERI_AHBSTAT, CONFIG_PERI_WPROT,
|
||||
CONFIG_PERI_WDOG, CONFIG_PERI_IRQ2, CONFIG_AHBRAM_ENABLE, 7 + CFG_AHBRAM_SZ,
|
||||
CONFIG_ETH_ENABLE);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant debug_%s : debug_config_type := ( enable => true, uart => %s, \n\
|
||||
iureg => %s, fpureg => %s, nohalt => %s, pclow => %d,\n\
|
||||
dsuenable => %s, dsutrace => %s, dsumixed => %s,\n\
|
||||
dsudpram => %s, tracelines => %d);\n\
|
||||
", CONFIG_CFG_NAME, CONFIG_DEBUG_UART, CONFIG_DEBUG_IURF, CONFIG_DEBUG_FPURF,
|
||||
CONFIG_DEBUG_NOHALT, CFG_DEBUG_PCLOW, CONFIG_DSU_ENABLE, CONFIG_DSU_TRACEBUF,
|
||||
CONFIG_DSU_MIXED_TRACE, CONFIG_SYN_TRACE_DPRAM, CFG_DSU_TRACE_SZ);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant boot_%s : boot_config_type := (boot => %s, ramrws => %d,\n\
|
||||
ramwws => %d, sysclk => %d, baud => %d, extbaud => %s,\n\
|
||||
pabits => %d);\n\
|
||||
", CONFIG_CFG_NAME, CFG_BOOT_SOURCE, CONFIG_BOOT_RWS, CONFIG_BOOT_WWS,
|
||||
CONFIG_BOOT_SYSCLK, CONFIG_BOOT_BAUDRATE, CONFIG_BOOT_EXTBAUD,
|
||||
CONFIG_BOOT_PROMABITS);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant pci_%s : pci_config_type := (\n\
|
||||
pcicore => %s , ahbmasters => %d, fifodepth => %d,\n\
|
||||
arbiter => %s, fixpri => false, prilevels => 4, pcimasters => 4,\n\
|
||||
vendorid => 16#%04X#, deviceid => 16#%04X#, subsysid => 16#%04X#,\n\
|
||||
revisionid => 16#%02X#, classcode =>16#%06X#, pmepads => %s,\n\
|
||||
p66pad => %s, pcirstall => %s, trace => %s, tracedepth => %d);\n\
|
||||
", CONFIG_CFG_NAME, CFG_PCI_CORE, pciahbmst, CFG_PCI_FIFO, CONFIG_PCI_ARBEN,
|
||||
CONFIG_PCI_VENDORID, CONFIG_PCI_DEVICEID, CONFIG_PCI_SUBSYSID,
|
||||
CONFIG_PCI_REVID, CONFIG_PCI_CLASSCODE, CONFIG_PCI_PMEPADS,
|
||||
CONFIG_PCI_P66PAD, CONFIG_PCI_RESETALL, CONFIG_PCI_TRACE, CFG_PCI_TDEPTH);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
constant irq2cfg : irq2type := irq2none;\n\
|
||||
");
|
||||
|
||||
if (CONFIG_FT_ENABLE)
|
||||
fprintf(fp, "\n\
|
||||
constant ft_%s : ft_config_type := ( rfpbits => %d, tmrreg => %s,\n\
|
||||
tmrclk => %s, mscheck => %s, memedac => %s, \n\
|
||||
rfwropt => %s, cparbits => %d, caddrpar => %s, regferr => %s,\n\
|
||||
cacheerr => %s);\n\
|
||||
", CONFIG_CFG_NAME, CONFIG_FT_RF_PARBITS, CONFIG_FT_TMR_REG, CONFIG_FT_TMR_CLK,
|
||||
CONFIG_FT_MC, CONFIG_FT_MEMEDAC, CONFIG_FT_RF_WRFAST,
|
||||
CONFIG_FT_CACHEMEM_PARBITS, CONFIG_FT_CACHEMEM_APAR, CONFIG_DEBUG_RFERR,
|
||||
CONFIG_DEBUG_CACHEMEMERR);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
\n\
|
||||
-----------------------------------------------------------------------------\n\
|
||||
-- end of automatic configuration\n\
|
||||
-----------------------------------------------------------------------------\n\
|
||||
\n\
|
||||
end;\n\
|
||||
");
|
||||
close(fp);
|
||||
fp = fopen("device.v", "w+");
|
||||
if (!fp) {
|
||||
printf("could not open file device.v\n");
|
||||
exit(1);
|
||||
}
|
||||
fprintf(fp, "\n\
|
||||
`define HEADER_VENDOR_ID 16'h%04X\n\
|
||||
`define HEADER_DEVICE_ID 16'h%04X\n\
|
||||
`define HEADER_REVISION_ID 8'h%02X\n\
|
||||
", CONFIG_PCI_VENDORID, CONFIG_PCI_DEVICEID, CONFIG_PCI_REVID);
|
||||
|
||||
if ((CONFIG_SYN_INFER_RAM == false) && (!((strcmp(CFG_SYN_TARGET_TECH, "virtex")) &&
|
||||
(strcmp(CFG_SYN_TARGET_TECH, "virtex2"))))) {
|
||||
fprintf(fp, "\n\
|
||||
`define FPGA\n\
|
||||
`define XILINX\n\
|
||||
`define WBW_ADDR_LENGTH 7\n\
|
||||
`define WBR_ADDR_LENGTH 7\n\
|
||||
`define PCIW_ADDR_LENGTH 7\n\
|
||||
`define PCIR_ADDR_LENGTH 7\n\
|
||||
`define PCI_FIFO_RAM_ADDR_LENGTH 8 \n\
|
||||
`define WB_FIFO_RAM_ADDR_LENGTH 8 \n\
|
||||
");
|
||||
} else
|
||||
fprintf(fp, "\n\
|
||||
`define WB_RAM_DONT_SHARE\n\
|
||||
`define PCI_RAM_DONT_SHARE\n\
|
||||
`define WBW_ADDR_LENGTH %d\n\
|
||||
`define WBR_ADDR_LENGTH %d\n\
|
||||
`define PCIW_ADDR_LENGTH %d\n\
|
||||
`define PCIR_ADDR_LENGTH %d\n\
|
||||
`define PCI_FIFO_RAM_ADDR_LENGTH %d \n\
|
||||
`define WB_FIFO_RAM_ADDR_LENGTH %d \n\
|
||||
", CFG_PCI_FIFO, CFG_PCI_FIFO, CFG_PCI_FIFO, CFG_PCI_FIFO,
|
||||
CFG_PCI_FIFO, CFG_PCI_FIFO);
|
||||
|
||||
fprintf(fp, "\n\
|
||||
`define ETH_WISHBONE_B3\n\
|
||||
\n\
|
||||
`define ETH_TX_FIFO_CNT_WIDTH %d\n\
|
||||
`define ETH_TX_FIFO_DEPTH %d\n\
|
||||
\n\
|
||||
`define ETH_RX_FIFO_CNT_WIDTH %d\n\
|
||||
`define ETH_RX_FIFO_DEPTH %d\n\
|
||||
\n\
|
||||
`define ETH_BURST_CNT_WIDTH %d\n\
|
||||
`define ETH_BURST_LENGTH %d\n",
|
||||
log2(CONFIG_ETH_TXFIFO)+1, CONFIG_ETH_TXFIFO,
|
||||
log2(CONFIG_ETH_RXFIFO)+1, CONFIG_ETH_RXFIFO,
|
||||
log2(CONFIG_ETH_BURST)+1, CONFIG_ETH_BURST);
|
||||
|
||||
close(fp);
|
||||
return(0);
|
||||
}
|
||||
97
bin/tkconfig/tail.tk
Normal file
97
bin/tkconfig/tail.tk
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
# FILE: tail.tk
|
||||
# This file is boilerplate TCL/TK function definitions for 'make xconfig'.
|
||||
#
|
||||
# CHANGES
|
||||
# =======
|
||||
#
|
||||
# 8 January 1998, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
# Arrange buttons in three columns for better screen fitting.
|
||||
#
|
||||
|
||||
#
|
||||
# Read the user's settings from .config. These will override whatever is
|
||||
# in config.in. Don't do this if the user specified a -D to force
|
||||
# the defaults.
|
||||
#
|
||||
|
||||
set defaults defconfig
|
||||
|
||||
if { [file readable .config] == 1} then {
|
||||
if { $argc > 0 } then {
|
||||
if { [lindex $argv 0] != "-D" } then {
|
||||
read_config .config
|
||||
if { [lindex $argv 0] == "-regen" } then {
|
||||
catch {exec cp -f .config .config.old};
|
||||
writeconfig .config config.h
|
||||
exit 2
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
read_config $defaults
|
||||
}
|
||||
} else {
|
||||
read_config .config
|
||||
}
|
||||
} else {
|
||||
read_config $defaults
|
||||
}
|
||||
|
||||
update_define 1 $total_menus 0
|
||||
update_mainmenu
|
||||
|
||||
button .f0.right.save -anchor w -text "Save and Exit" -underline 0\
|
||||
-command { catch {exec cp -f .config .config.old}; \
|
||||
writeconfig .config config.h; wrapup .wrap }
|
||||
|
||||
button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\
|
||||
-command { maybe_exit .maybe }
|
||||
|
||||
button .f0.right.load -anchor w -text "Load Configuration from File" \
|
||||
-command { load_configfile .load "Load Configuration from file" read_config_file
|
||||
}
|
||||
|
||||
button .f0.right.store -anchor w -text "Store Configuration to File" \
|
||||
-command { load_configfile .load "Store Configuration to file" write_config_file }
|
||||
|
||||
#
|
||||
# Now pack everything.
|
||||
#
|
||||
|
||||
pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \
|
||||
-padx 0 -pady 0 -side bottom -fill x
|
||||
pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y
|
||||
pack .f0 -padx 5 -pady 5
|
||||
|
||||
update idletasks
|
||||
set winy [expr 10 + [winfo reqheight .f0]]
|
||||
set scry [lindex [wm maxsize .] 1]
|
||||
set winx [expr 10 + [winfo reqwidth .f0]]
|
||||
set scrx [lindex [wm maxsize .] 0]
|
||||
if {$winx < $scrx} then {set maxx -1} else {set maxx $winx}
|
||||
if {$winy < $scry} then {set maxy -1} else {set maxy $winy}
|
||||
.f0 configure -width $winx -height $winy
|
||||
wm maxsize . $maxx $maxy
|
||||
|
||||
#
|
||||
# If we cannot write our config files, disable the write button.
|
||||
#
|
||||
if { [file exists .config] == 1 } then {
|
||||
if { [file writable .config] == 0 } then {
|
||||
.f0.right.save configure -state disabled
|
||||
}
|
||||
} else {
|
||||
if { [file writable .] == 0 } then {
|
||||
.f0.right.save configure -state disabled
|
||||
}
|
||||
}
|
||||
|
||||
#if { [file exists include/linux/autoconf.h] == 1 } then {
|
||||
# if { [file writable include/linux/autoconf.h] == 0 } then {
|
||||
# .f0.right.save configure -state disabled
|
||||
# }
|
||||
# } else {
|
||||
# if { [file writable include/linux/] == 0 } then {
|
||||
# .f0.right.save configure -state disabled
|
||||
# }
|
||||
# }
|
||||
602
bin/tkconfig/tkcond.c
Normal file
602
bin/tkconfig/tkcond.c
Normal file
|
|
@ -0,0 +1,602 @@
|
|||
/*
|
||||
* tkcond.c
|
||||
*
|
||||
* Eric Youngdale was the original author of xconfig.
|
||||
* Michael Elizabeth Chastain (mec@shout.net) is the current maintainer.
|
||||
*
|
||||
* This file takes the tokenized statement list and transforms 'if ...'
|
||||
* statements. For each simple statement, I find all of the 'if' statements
|
||||
* that enclose it, and attach the aggregate conditionals of those 'if'
|
||||
* statements to the cond list of the simple statement.
|
||||
*
|
||||
* 14 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
* - Steam-clean this file. I tested this by generating kconfig.tk for
|
||||
* every architecture and comparing it character-for-character against
|
||||
* the output of the old tkparse.
|
||||
*
|
||||
* 07 July 1999, Andrzej M. Krzysztofowicz <ankry@mif.pg.gda.pl>
|
||||
* - kvariables removed; all variables are stored in a single table now
|
||||
* - some elimination of options non-valid for current architecture
|
||||
* implemented.
|
||||
* - negation (!) eliminated from conditions
|
||||
*
|
||||
* TO DO:
|
||||
* - xconfig is at the end of its life cycle. Contact <mec@shout.net> if
|
||||
* you are interested in working on the replacement.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "tkparse.h"
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Mark variables which are defined anywhere.
|
||||
*/
|
||||
static void mark_variables( struct kconfig * scfg )
|
||||
{
|
||||
struct kconfig * cfg;
|
||||
int i;
|
||||
|
||||
for ( i = 1; i <= max_varnum; i++ )
|
||||
vartable[i].defined = 0;
|
||||
for ( cfg = scfg; cfg != NULL; cfg = cfg->next )
|
||||
{
|
||||
if ( cfg->token == token_bool
|
||||
|| cfg->token == token_choice_item
|
||||
|| cfg->token == token_define_bool
|
||||
|| cfg->token == token_define_hex
|
||||
|| cfg->token == token_define_int
|
||||
|| cfg->token == token_define_string
|
||||
|| cfg->token == token_define_tristate
|
||||
|| cfg->token == token_dep_bool
|
||||
|| cfg->token == token_dep_mbool
|
||||
|| cfg->token == token_dep_tristate
|
||||
|| cfg->token == token_hex
|
||||
|| cfg->token == token_int
|
||||
|| cfg->token == token_string
|
||||
|| cfg->token == token_tristate
|
||||
|| cfg->token == token_unset )
|
||||
{
|
||||
if ( cfg->nameindex > 0 ) /* paranoid */
|
||||
{
|
||||
vartable[cfg->nameindex].defined = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void free_cond( struct condition *cond )
|
||||
{
|
||||
struct condition *tmp, *tmp1;
|
||||
for ( tmp = cond; tmp; tmp = tmp1 )
|
||||
{
|
||||
tmp1 = tmp->next;
|
||||
free( (void*)tmp );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Remove the bang operator from a condition to avoid priority problems.
|
||||
* "!" has different priorities as "test" command argument and in
|
||||
* a tk script.
|
||||
*/
|
||||
static struct condition * remove_bang( struct condition * condition )
|
||||
{
|
||||
struct condition * conda, * condb, * prev = NULL;
|
||||
|
||||
for ( conda = condition; conda; conda = conda->next )
|
||||
{
|
||||
if ( conda->op == op_bang && conda->next &&
|
||||
( condb = conda->next->next ) )
|
||||
{
|
||||
if ( condb->op == op_eq || condb->op == op_neq )
|
||||
{
|
||||
condb->op = (condb->op == op_eq) ? op_neq : op_eq;
|
||||
conda->op = op_nuked;
|
||||
if ( prev )
|
||||
{
|
||||
prev->next = conda->next;
|
||||
}
|
||||
else
|
||||
{
|
||||
condition = conda->next;
|
||||
}
|
||||
conda->next = NULL;
|
||||
free_cond( conda );
|
||||
conda = condb;
|
||||
}
|
||||
}
|
||||
prev = conda;
|
||||
}
|
||||
return condition;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Make a new condition chain by joining the current condition stack with
|
||||
* the "&&" operator for glue.
|
||||
*/
|
||||
static struct condition * join_condition_stack( struct condition * conditions [],
|
||||
int depth )
|
||||
{
|
||||
struct condition * cond_list;
|
||||
struct condition * cond_last;
|
||||
int i, is_first = 1;
|
||||
|
||||
cond_list = cond_last = NULL;
|
||||
|
||||
for ( i = 0; i < depth; i++ )
|
||||
{
|
||||
if ( conditions[i]->op == op_false )
|
||||
{
|
||||
struct condition * cnew;
|
||||
|
||||
/* It is always false condition */
|
||||
cnew = malloc( sizeof(*cnew) );
|
||||
memset( cnew, 0, sizeof(*cnew) );
|
||||
cnew->op = op_false;
|
||||
cond_list = cond_last = cnew;
|
||||
goto join_done;
|
||||
}
|
||||
}
|
||||
for ( i = 0; i < depth; i++ )
|
||||
{
|
||||
struct condition * cond;
|
||||
struct condition * cnew;
|
||||
int add_paren;
|
||||
|
||||
/* omit always true conditions */
|
||||
if ( conditions[i]->op == op_true )
|
||||
continue;
|
||||
|
||||
/* if i have another condition, add an '&&' operator */
|
||||
if ( !is_first )
|
||||
{
|
||||
cnew = malloc( sizeof(*cnew) );
|
||||
memset( cnew, 0, sizeof(*cnew) );
|
||||
cnew->op = op_and;
|
||||
cond_last->next = cnew;
|
||||
cond_last = cnew;
|
||||
}
|
||||
|
||||
if ( conditions[i]->op != op_lparen )
|
||||
{
|
||||
/* add a '(' */
|
||||
add_paren = 1;
|
||||
cnew = malloc( sizeof(*cnew) );
|
||||
memset( cnew, 0, sizeof(*cnew) );
|
||||
cnew->op = op_lparen;
|
||||
if ( cond_last == NULL )
|
||||
{ cond_list = cond_last = cnew; }
|
||||
else
|
||||
{ cond_last->next = cnew; cond_last = cnew; }
|
||||
}
|
||||
else
|
||||
{
|
||||
add_paren = 0;
|
||||
}
|
||||
|
||||
/* duplicate the chain */
|
||||
for ( cond = conditions [i]; cond != NULL; cond = cond->next )
|
||||
{
|
||||
cnew = malloc( sizeof(*cnew) );
|
||||
cnew->next = NULL;
|
||||
cnew->op = cond->op;
|
||||
cnew->str = cond->str ? strdup( cond->str ) : NULL;
|
||||
cnew->nameindex = cond->nameindex;
|
||||
if ( cond_last == NULL )
|
||||
{ cond_list = cond_last = cnew; }
|
||||
else
|
||||
{ cond_last->next = cnew; cond_last = cnew; }
|
||||
}
|
||||
|
||||
if ( add_paren )
|
||||
{
|
||||
/* add a ')' */
|
||||
cnew = malloc( sizeof(*cnew) );
|
||||
memset( cnew, 0, sizeof(*cnew) );
|
||||
cnew->op = op_rparen;
|
||||
cond_last->next = cnew;
|
||||
cond_last = cnew;
|
||||
}
|
||||
is_first = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove duplicate conditions.
|
||||
*/
|
||||
{
|
||||
struct condition *cond1, *cond1b, *cond1c, *cond1d, *cond1e, *cond1f;
|
||||
|
||||
for ( cond1 = cond_list; cond1 != NULL; cond1 = cond1->next )
|
||||
{
|
||||
if ( cond1->op == op_lparen )
|
||||
{
|
||||
cond1b = cond1 ->next; if ( cond1b == NULL ) break;
|
||||
cond1c = cond1b->next; if ( cond1c == NULL ) break;
|
||||
cond1d = cond1c->next; if ( cond1d == NULL ) break;
|
||||
cond1e = cond1d->next; if ( cond1e == NULL ) break;
|
||||
cond1f = cond1e->next; if ( cond1f == NULL ) break;
|
||||
|
||||
if ( cond1b->op == op_variable
|
||||
&& ( cond1c->op == op_eq || cond1c->op == op_neq )
|
||||
&& cond1d->op == op_constant
|
||||
&& cond1e->op == op_rparen )
|
||||
{
|
||||
struct condition *cond2, *cond2b, *cond2c, *cond2d, *cond2e, *cond2f;
|
||||
|
||||
for ( cond2 = cond1f->next; cond2 != NULL; cond2 = cond2->next )
|
||||
{
|
||||
if ( cond2->op == op_lparen )
|
||||
{
|
||||
cond2b = cond2 ->next; if ( cond2b == NULL ) break;
|
||||
cond2c = cond2b->next; if ( cond2c == NULL ) break;
|
||||
cond2d = cond2c->next; if ( cond2d == NULL ) break;
|
||||
cond2e = cond2d->next; if ( cond2e == NULL ) break;
|
||||
cond2f = cond2e->next;
|
||||
|
||||
/* look for match */
|
||||
if ( cond2b->op == op_variable
|
||||
&& cond2b->nameindex == cond1b->nameindex
|
||||
&& cond2c->op == cond1c->op
|
||||
&& cond2d->op == op_constant
|
||||
&& strcmp( cond2d->str, cond1d->str ) == 0
|
||||
&& cond2e->op == op_rparen )
|
||||
{
|
||||
/* one of these must be followed by && */
|
||||
if ( cond1f->op == op_and
|
||||
|| ( cond2f != NULL && cond2f->op == op_and ) )
|
||||
{
|
||||
/* nuke the first duplicate */
|
||||
cond1 ->op = op_nuked;
|
||||
cond1b->op = op_nuked;
|
||||
cond1c->op = op_nuked;
|
||||
cond1d->op = op_nuked;
|
||||
cond1e->op = op_nuked;
|
||||
if ( cond1f->op == op_and )
|
||||
cond1f->op = op_nuked;
|
||||
else
|
||||
cond2f->op = op_nuked;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
join_done:
|
||||
return cond_list;
|
||||
}
|
||||
|
||||
|
||||
static char arch_sparc[] = "sparc";
|
||||
static char * current_arch = arch_sparc;
|
||||
|
||||
/*
|
||||
* Eliminating conditions with ARCH = <not current>.
|
||||
*/
|
||||
static struct condition *eliminate_other_arch( struct condition *list )
|
||||
{
|
||||
struct condition *cond1a = list, *cond1b = NULL, *cond1c = NULL, *cond1d = NULL;
|
||||
if ( current_arch == NULL )
|
||||
current_arch = getenv( "ARCH" );
|
||||
if ( current_arch == NULL )
|
||||
{
|
||||
fprintf( stderr, "error: ARCH undefined\n" );
|
||||
exit( 1 );
|
||||
}
|
||||
if ( cond1a->op == op_variable
|
||||
&& ! strcmp( vartable[cond1a->nameindex].name, "ARCH" ) )
|
||||
{
|
||||
cond1b = cond1a->next; if ( cond1b == NULL ) goto done;
|
||||
cond1c = cond1b->next; if ( cond1c == NULL ) goto done;
|
||||
cond1d = cond1c->next;
|
||||
if ( cond1c->op == op_constant && cond1d == NULL )
|
||||
{
|
||||
if ( (cond1b->op == op_eq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_neq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for another architecture */
|
||||
cond1a->op = op_false;
|
||||
cond1a->next = NULL;
|
||||
free_cond( cond1b );
|
||||
return cond1a;
|
||||
}
|
||||
else if ( (cond1b->op == op_neq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_eq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for current architecture */
|
||||
cond1a->op = op_true;
|
||||
cond1a->next = NULL;
|
||||
free_cond( cond1b );
|
||||
return cond1a;
|
||||
}
|
||||
}
|
||||
else if ( cond1c->op == op_constant && cond1d->op == op_or )
|
||||
{
|
||||
if ( (cond1b->op == op_eq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_neq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for another architecture */
|
||||
cond1b = cond1d->next;
|
||||
cond1d->next = NULL;
|
||||
free_cond( cond1a );
|
||||
return eliminate_other_arch( cond1b );
|
||||
}
|
||||
else if ( (cond1b->op == op_neq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_eq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for current architecture */
|
||||
cond1a->op = op_true;
|
||||
cond1a->next = NULL;
|
||||
free_cond( cond1b );
|
||||
return cond1a;
|
||||
}
|
||||
}
|
||||
else if ( cond1c->op == op_constant && cond1d->op == op_and )
|
||||
{
|
||||
if ( (cond1b->op == op_eq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_neq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for another architecture */
|
||||
int l_par = 0;
|
||||
|
||||
for ( cond1c = cond1d->next; cond1c; cond1c = cond1c->next )
|
||||
{
|
||||
if ( cond1c->op == op_lparen )
|
||||
l_par++;
|
||||
else if ( cond1c->op == op_rparen )
|
||||
l_par--;
|
||||
else if ( cond1c->op == op_or && l_par == 0 )
|
||||
/* Expression too complex - don't touch */
|
||||
return cond1a;
|
||||
else if ( l_par < 0 )
|
||||
{
|
||||
fprintf( stderr, "incorrect condition: programming error ?\n" );
|
||||
exit( 1 );
|
||||
}
|
||||
}
|
||||
cond1a->op = op_false;
|
||||
cond1a->next = NULL;
|
||||
free_cond( cond1b );
|
||||
return cond1a;
|
||||
}
|
||||
else if ( (cond1b->op == op_neq && strcmp( cond1c->str, current_arch ))
|
||||
|| (cond1b->op == op_eq && ! strcmp( cond1c->str, current_arch )) )
|
||||
{
|
||||
/* This is for current architecture */
|
||||
cond1b = cond1d->next;
|
||||
cond1d->next = NULL;
|
||||
free_cond( cond1a );
|
||||
return eliminate_other_arch( cond1b );
|
||||
}
|
||||
}
|
||||
}
|
||||
if ( cond1a->op == op_variable && ! vartable[cond1a->nameindex].defined )
|
||||
{
|
||||
cond1b = cond1a->next; if ( cond1b == NULL ) goto done;
|
||||
cond1c = cond1b->next; if ( cond1c == NULL ) goto done;
|
||||
cond1d = cond1c->next;
|
||||
|
||||
if ( cond1c->op == op_constant
|
||||
&& ( cond1d == NULL || cond1d->op == op_and ) ) /*???*/
|
||||
{
|
||||
if ( cond1b->op == op_eq && strcmp( cond1c->str, "" ) )
|
||||
{
|
||||
cond1a->op = op_false;
|
||||
cond1a->next = NULL;
|
||||
free_cond( cond1b );
|
||||
return cond1a;
|
||||
}
|
||||
}
|
||||
else if ( cond1c->op == op_constant && cond1d->op == op_or )
|
||||
{
|
||||
if ( cond1b->op == op_eq && strcmp( cond1c->str, "" ) )
|
||||
{
|
||||
cond1b = cond1d->next;
|
||||
cond1d->next = NULL;
|
||||
free_cond( cond1a );
|
||||
return eliminate_other_arch( cond1b );
|
||||
}
|
||||
}
|
||||
}
|
||||
done:
|
||||
return list;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* This is the main transformation function.
|
||||
*/
|
||||
void fix_conditionals( struct kconfig * scfg )
|
||||
{
|
||||
struct kconfig * cfg;
|
||||
|
||||
/*
|
||||
* Transform op_variable to op_kvariable.
|
||||
*/
|
||||
mark_variables( scfg );
|
||||
|
||||
/*
|
||||
* Walk the statement list, maintaining a stack of current conditions.
|
||||
* token_if push its condition onto the stack.
|
||||
* token_else invert the condition on the top of the stack.
|
||||
* token_endif pop the stack.
|
||||
*
|
||||
* For a simple statement, create a condition chain by joining together
|
||||
* all of the conditions on the stack.
|
||||
*/
|
||||
{
|
||||
struct condition * cond_stack [32];
|
||||
int depth = 0;
|
||||
struct kconfig * prev = NULL;
|
||||
|
||||
for ( cfg = scfg; cfg != NULL; cfg = cfg->next )
|
||||
{
|
||||
int good = 1;
|
||||
switch ( cfg->token )
|
||||
{
|
||||
default:
|
||||
break;
|
||||
|
||||
case token_if:
|
||||
cond_stack [depth++] =
|
||||
remove_bang( eliminate_other_arch( cfg->cond ) );
|
||||
cfg->cond = NULL;
|
||||
break;
|
||||
|
||||
case token_else:
|
||||
{
|
||||
/*
|
||||
* Invert the condition chain.
|
||||
*
|
||||
* Be careful to transfrom op_or to op_and1, not op_and.
|
||||
* I will need this later in the code that removes
|
||||
* duplicate conditions.
|
||||
*/
|
||||
struct condition * cond;
|
||||
|
||||
for ( cond = cond_stack [depth-1];
|
||||
cond != NULL;
|
||||
cond = cond->next )
|
||||
{
|
||||
switch( cond->op )
|
||||
{
|
||||
default: break;
|
||||
case op_and: cond->op = op_or; break;
|
||||
case op_or: cond->op = op_and1; break;
|
||||
case op_neq: cond->op = op_eq; break;
|
||||
case op_eq: cond->op = op_neq; break;
|
||||
case op_true: cond->op = op_false;break;
|
||||
case op_false:cond->op = op_true; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case token_fi:
|
||||
--depth;
|
||||
break;
|
||||
|
||||
case token_bool:
|
||||
case token_choice_item:
|
||||
case token_choice_header:
|
||||
case token_comment:
|
||||
case token_define_bool:
|
||||
case token_define_hex:
|
||||
case token_define_int:
|
||||
case token_define_string:
|
||||
case token_define_tristate:
|
||||
case token_endmenu:
|
||||
case token_hex:
|
||||
case token_int:
|
||||
case token_mainmenu_option:
|
||||
case token_string:
|
||||
case token_tristate:
|
||||
case token_unset:
|
||||
cfg->cond = join_condition_stack( cond_stack, depth );
|
||||
if ( cfg->cond && cfg->cond->op == op_false )
|
||||
{
|
||||
good = 0;
|
||||
if ( prev )
|
||||
prev->next = cfg->next;
|
||||
else
|
||||
scfg = cfg->next;
|
||||
}
|
||||
break;
|
||||
|
||||
case token_dep_bool:
|
||||
case token_dep_mbool:
|
||||
case token_dep_tristate:
|
||||
/*
|
||||
* Same as the other simple statements, plus an additional
|
||||
* condition for the dependency.
|
||||
*/
|
||||
if ( cfg->cond )
|
||||
{
|
||||
cond_stack [depth] = eliminate_other_arch( cfg->cond );
|
||||
cfg->cond = join_condition_stack( cond_stack, depth+1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
cfg->cond = join_condition_stack( cond_stack, depth );
|
||||
}
|
||||
if ( cfg->cond && cfg->cond->op == op_false )
|
||||
{
|
||||
good = 0;
|
||||
if ( prev )
|
||||
prev->next = cfg->next;
|
||||
else
|
||||
scfg = cfg->next;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if ( good )
|
||||
prev = cfg;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#if 0
|
||||
void dump_condition( struct condition *list )
|
||||
{
|
||||
struct condition *tmp;
|
||||
for ( tmp = list; tmp; tmp = tmp->next )
|
||||
{
|
||||
switch (tmp->op)
|
||||
{
|
||||
default:
|
||||
break;
|
||||
case op_variable:
|
||||
printf( " %s", vartable[tmp->nameindex].name );
|
||||
break;
|
||||
case op_constant:
|
||||
printf( " %s", tmp->str );
|
||||
break;
|
||||
case op_eq:
|
||||
printf( " =" );
|
||||
break;
|
||||
case op_bang:
|
||||
printf( " !" );
|
||||
break;
|
||||
case op_neq:
|
||||
printf( " !=" );
|
||||
break;
|
||||
case op_and:
|
||||
case op_and1:
|
||||
printf( " -a" );
|
||||
break;
|
||||
case op_or:
|
||||
printf( " -o" );
|
||||
break;
|
||||
case op_true:
|
||||
printf( " TRUE" );
|
||||
break;
|
||||
case op_false:
|
||||
printf( " FALSE" );
|
||||
break;
|
||||
case op_lparen:
|
||||
printf( " (" );
|
||||
break;
|
||||
case op_rparen:
|
||||
printf( " )" );
|
||||
break;
|
||||
}
|
||||
}
|
||||
printf( "\n" );
|
||||
}
|
||||
#endif
|
||||
1521
bin/tkconfig/tkgen.c
Normal file
1521
bin/tkconfig/tkgen.c
Normal file
File diff suppressed because it is too large
Load diff
887
bin/tkconfig/tkparse.c
Normal file
887
bin/tkconfig/tkparse.c
Normal file
|
|
@ -0,0 +1,887 @@
|
|||
/*
|
||||
* tkparse.c
|
||||
*
|
||||
* Eric Youngdale was the original author of xconfig.
|
||||
* Michael Elizabeth Chastain (mec@shout.net) is the current maintainer.
|
||||
*
|
||||
* Parse a config.in file and translate it to a wish script.
|
||||
* This task has three parts:
|
||||
*
|
||||
* tkparse.c tokenize the input
|
||||
* tkcond.c transform 'if ...' statements
|
||||
* tkgen.c generate output
|
||||
*
|
||||
* Change History
|
||||
*
|
||||
* 7 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
* - Teach dep_tristate about a few literals, such as:
|
||||
* dep_tristate 'foo' CONFIG_FOO m
|
||||
* Also have it print an error message and exit on some parse failures.
|
||||
*
|
||||
* 14 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
* - Don't fclose stdin. Thanks to Tony Hoyle for nailing this one.
|
||||
*
|
||||
* 14 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
* - Steam-clean this file. I tested this by generating kconfig.tk for
|
||||
* every architecture and comparing it character-for-character against
|
||||
* the output of the old tkparse.
|
||||
*
|
||||
* 23 January 1999, Michael Elizabeth Chastain, <mec@shout.net>
|
||||
* - Remove bug-compatible code.
|
||||
*
|
||||
* 07 July 1999, Andrzej M. Krzysztofowicz, <ankry@mif.pg.gda.pl>
|
||||
* - Submenus implemented,
|
||||
* - plenty of option updating/displaying fixes,
|
||||
* - dep_bool, define_hex, define_int, define_string, define_tristate and
|
||||
* undef implemented,
|
||||
* - dep_tristate fixed to support multiple dependencies,
|
||||
* - handling of variables with an empty value implemented,
|
||||
* - value checking for int and hex fields,
|
||||
* - more checking during condition parsing; choice variables are treated as
|
||||
* all others now,
|
||||
*
|
||||
* TO DO:
|
||||
* - xconfig is at the end of its life cycle. Contact <mec@shout.net> if
|
||||
* you are interested in working on the replacement.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "tkparse.h"
|
||||
|
||||
static struct kconfig * config_list = NULL;
|
||||
static struct kconfig * config_last = NULL;
|
||||
static const char * current_file = "<unknown file>";
|
||||
static int lineno = 0;
|
||||
|
||||
static void do_source( const char * );
|
||||
|
||||
#undef strcmp
|
||||
int my_strcmp( const char * s1, const char * s2 ) { return strcmp( s1, s2 ); }
|
||||
#define strcmp my_strcmp
|
||||
|
||||
/*
|
||||
* Report a syntax error.
|
||||
*/
|
||||
static void syntax_error( const char * msg )
|
||||
{
|
||||
fprintf( stderr, "%s: %d: %s\n", current_file, lineno, msg );
|
||||
exit( 1 );
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Find index of a specyfic variable in the symbol table.
|
||||
* Create a new entry if it does not exist yet.
|
||||
*/
|
||||
#define VARTABLE_SIZE 2048
|
||||
struct variable vartable[VARTABLE_SIZE];
|
||||
int max_varnum = 0;
|
||||
|
||||
int get_varnum( char * name )
|
||||
{
|
||||
int i;
|
||||
|
||||
for ( i = 1; i <= max_varnum; i++ )
|
||||
if ( strcmp( vartable[i].name, name ) == 0 )
|
||||
return i;
|
||||
if (max_varnum > VARTABLE_SIZE-1)
|
||||
syntax_error( "Too many variables defined." );
|
||||
vartable[++max_varnum].name = malloc( strlen( name )+1 );
|
||||
strcpy( vartable[max_varnum].name, name );
|
||||
return max_varnum;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get a string.
|
||||
*/
|
||||
static const char * get_string( const char * pnt, char ** label )
|
||||
{
|
||||
const char * word;
|
||||
|
||||
word = pnt;
|
||||
for ( ; ; )
|
||||
{
|
||||
if ( *pnt == '\0' || *pnt == ' ' || *pnt == '\t' )
|
||||
break;
|
||||
pnt++;
|
||||
}
|
||||
|
||||
*label = malloc( pnt - word + 1 );
|
||||
memcpy( *label, word, pnt - word );
|
||||
(*label)[pnt - word] = '\0';
|
||||
|
||||
if ( *pnt != '\0' )
|
||||
pnt++;
|
||||
return pnt;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get a quoted string.
|
||||
* Insert a '\' before any characters that need quoting.
|
||||
*/
|
||||
static const char * get_qstring( const char * pnt, char ** label )
|
||||
{
|
||||
char quote_char;
|
||||
char newlabel [2048];
|
||||
char * pnt1;
|
||||
|
||||
/* advance to the open quote */
|
||||
for ( ; ; )
|
||||
{
|
||||
if ( *pnt == '\0' )
|
||||
return pnt;
|
||||
quote_char = *pnt++;
|
||||
if ( quote_char == '"' || quote_char == '\'' )
|
||||
break;
|
||||
}
|
||||
|
||||
/* copy into an intermediate buffer */
|
||||
pnt1 = newlabel;
|
||||
for ( ; ; )
|
||||
{
|
||||
if ( *pnt == '\0' )
|
||||
syntax_error( "unterminated quoted string" );
|
||||
if ( *pnt == quote_char && pnt[-1] != '\\' )
|
||||
break;
|
||||
|
||||
/* copy the character, quoting if needed */
|
||||
if ( *pnt == '"' || *pnt == '\'' || *pnt == '[' || *pnt == ']' )
|
||||
*pnt1++ = '\\';
|
||||
*pnt1++ = *pnt++;
|
||||
}
|
||||
|
||||
/* copy the label into a permanent location */
|
||||
*pnt1++ = '\0';
|
||||
*label = (char *) malloc( pnt1 - newlabel );
|
||||
memcpy( *label, newlabel, pnt1 - newlabel );
|
||||
|
||||
/* skip over last quote and next whitespace */
|
||||
pnt++;
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
return pnt;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get a quoted or unquoted string. It is recognized by the first
|
||||
* non-white character. '"' and '"' are not allowed inside the string.
|
||||
*/
|
||||
static const char * get_qnqstring( const char * pnt, char ** label )
|
||||
{
|
||||
char quote_char;
|
||||
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
|
||||
if ( *pnt == '\0' )
|
||||
return pnt;
|
||||
quote_char = *pnt;
|
||||
if ( quote_char == '"' || quote_char == '\'' )
|
||||
return get_qstring( pnt, label );
|
||||
else
|
||||
return get_string( pnt, label );
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Tokenize an 'if' statement condition.
|
||||
*/
|
||||
static struct condition * tokenize_if( const char * pnt )
|
||||
{
|
||||
struct condition * list;
|
||||
struct condition * last;
|
||||
struct condition * prev;
|
||||
|
||||
/* eat the open bracket */
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
if ( *pnt != '[' )
|
||||
syntax_error( "bad 'if' condition" );
|
||||
pnt++;
|
||||
|
||||
list = last = NULL;
|
||||
for ( ; ; )
|
||||
{
|
||||
struct condition * cond;
|
||||
|
||||
/* advance to the next token */
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
if ( *pnt == '\0' )
|
||||
syntax_error( "unterminated 'if' condition" );
|
||||
if ( *pnt == ']' )
|
||||
return list;
|
||||
|
||||
/* allocate a new token */
|
||||
cond = malloc( sizeof(*cond) );
|
||||
memset( cond, 0, sizeof(*cond) );
|
||||
if ( last == NULL )
|
||||
{ list = last = cond; prev = NULL; }
|
||||
else
|
||||
{ prev = last; last->next = cond; last = cond; }
|
||||
|
||||
/* determine the token value */
|
||||
if ( *pnt == '-' && pnt[1] == 'a' )
|
||||
{
|
||||
if ( ! prev || ( prev->op != op_variable && prev->op != op_constant ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
cond->op = op_and; pnt += 2; continue;
|
||||
}
|
||||
|
||||
if ( *pnt == '-' && pnt[1] == 'o' )
|
||||
{
|
||||
if ( ! prev || ( prev->op != op_variable && prev->op != op_constant ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
cond->op = op_or; pnt += 2; continue;
|
||||
}
|
||||
|
||||
if ( *pnt == '!' && pnt[1] == '=' )
|
||||
{
|
||||
if ( ! prev || ( prev->op != op_variable && prev->op != op_constant ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
cond->op = op_neq; pnt += 2; continue;
|
||||
}
|
||||
|
||||
if ( *pnt == '=' )
|
||||
{
|
||||
if ( ! prev || ( prev->op != op_variable && prev->op != op_constant ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
cond->op = op_eq; pnt += 1; continue;
|
||||
}
|
||||
|
||||
if ( *pnt == '!' )
|
||||
{
|
||||
if ( prev && ( prev->op != op_and && prev->op != op_or
|
||||
&& prev->op != op_bang ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
cond->op = op_bang; pnt += 1; continue;
|
||||
}
|
||||
|
||||
if ( *pnt == '"' )
|
||||
{
|
||||
const char * word;
|
||||
|
||||
if ( prev && ( prev->op == op_variable || prev->op == op_constant ) )
|
||||
syntax_error( "incorrect argument" );
|
||||
/* advance to the word */
|
||||
pnt++;
|
||||
if ( *pnt == '$' )
|
||||
{ cond->op = op_variable; pnt++; }
|
||||
else
|
||||
{ cond->op = op_constant; }
|
||||
|
||||
/* find the end of the word */
|
||||
word = pnt;
|
||||
for ( ; ; )
|
||||
{
|
||||
if ( *pnt == '\0' )
|
||||
syntax_error( "unterminated double quote" );
|
||||
if ( *pnt == '"' )
|
||||
break;
|
||||
pnt++;
|
||||
}
|
||||
|
||||
/* store a copy of this word */
|
||||
{
|
||||
char * str = malloc( pnt - word + 1 );
|
||||
memcpy( str, word, pnt - word );
|
||||
str [pnt - word] = '\0';
|
||||
if ( cond->op == op_variable )
|
||||
{
|
||||
cond->nameindex = get_varnum( str );
|
||||
free( str );
|
||||
}
|
||||
else /* op_constant */
|
||||
{
|
||||
cond->str = str;
|
||||
}
|
||||
}
|
||||
|
||||
pnt++;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* unknown token */
|
||||
syntax_error( "bad if condition" );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Tokenize a choice list. Choices appear as pairs of strings;
|
||||
* note that I am parsing *inside* the double quotes. Ugh.
|
||||
*/
|
||||
static const char * tokenize_choices( struct kconfig * cfg_choose,
|
||||
const char * pnt )
|
||||
{
|
||||
int default_checked = 0;
|
||||
for ( ; ; )
|
||||
{
|
||||
struct kconfig * cfg;
|
||||
char * buffer = malloc( 64 );
|
||||
|
||||
/* skip whitespace */
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
if ( *pnt == '\0' )
|
||||
return pnt;
|
||||
|
||||
/* allocate a new kconfig line */
|
||||
cfg = malloc( sizeof(*cfg) );
|
||||
memset( cfg, 0, sizeof(*cfg) );
|
||||
if ( config_last == NULL )
|
||||
{ config_last = config_list = cfg; }
|
||||
else
|
||||
{ config_last->next = cfg; config_last = cfg; }
|
||||
|
||||
/* fill out the line */
|
||||
cfg->token = token_choice_item;
|
||||
cfg->cfg_parent = cfg_choose;
|
||||
pnt = get_string( pnt, &cfg->label );
|
||||
if ( ! default_checked &&
|
||||
! strncmp( cfg->label, cfg_choose->value, strlen( cfg_choose->value ) ) )
|
||||
{
|
||||
default_checked = 1;
|
||||
free( cfg_choose->value );
|
||||
cfg_choose->value = cfg->label;
|
||||
}
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
}
|
||||
if ( ! default_checked )
|
||||
syntax_error( "bad 'choice' default value" );
|
||||
return pnt;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Tokenize one line.
|
||||
*/
|
||||
static void tokenize_line( const char * pnt )
|
||||
{
|
||||
static struct kconfig * last_menuoption = NULL;
|
||||
enum e_token token;
|
||||
struct kconfig * cfg;
|
||||
struct dependency ** dep_ptr;
|
||||
char * buffer = malloc( 64 );
|
||||
|
||||
/* skip white space */
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
|
||||
/*
|
||||
* categorize the next token
|
||||
*/
|
||||
|
||||
#define match_token(t, s) \
|
||||
if (strncmp(pnt, s, strlen(s)) == 0) { token = t; pnt += strlen(s); break; }
|
||||
|
||||
token = token_UNKNOWN;
|
||||
switch ( *pnt )
|
||||
{
|
||||
default:
|
||||
break;
|
||||
|
||||
case '#':
|
||||
case '\0':
|
||||
return;
|
||||
|
||||
case 'b':
|
||||
match_token( token_bool, "bool" );
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
match_token( token_choice_header, "choice" );
|
||||
match_token( token_comment, "comment" );
|
||||
break;
|
||||
|
||||
case 'd':
|
||||
match_token( token_define_bool, "define_bool" );
|
||||
match_token( token_define_hex, "define_hex" );
|
||||
match_token( token_define_int, "define_int" );
|
||||
match_token( token_define_string, "define_string" );
|
||||
match_token( token_define_tristate, "define_tristate" );
|
||||
match_token( token_dep_bool, "dep_bool" );
|
||||
match_token( token_dep_mbool, "dep_mbool" );
|
||||
match_token( token_dep_tristate, "dep_tristate" );
|
||||
break;
|
||||
|
||||
case 'e':
|
||||
match_token( token_else, "else" );
|
||||
match_token( token_endmenu, "endmenu" );
|
||||
break;
|
||||
|
||||
case 'f':
|
||||
match_token( token_fi, "fi" );
|
||||
break;
|
||||
|
||||
case 'h':
|
||||
match_token( token_hex, "hex" );
|
||||
break;
|
||||
|
||||
case 'i':
|
||||
match_token( token_if, "if" );
|
||||
match_token( token_int, "int" );
|
||||
break;
|
||||
|
||||
case 'm':
|
||||
match_token( token_mainmenu_name, "mainmenu_name" );
|
||||
match_token( token_mainmenu_option, "mainmenu_option" );
|
||||
break;
|
||||
|
||||
case 's':
|
||||
match_token( token_source, "source" );
|
||||
match_token( token_string, "string" );
|
||||
break;
|
||||
|
||||
case 't':
|
||||
match_token( token_then, "then" );
|
||||
match_token( token_tristate, "tristate" );
|
||||
break;
|
||||
|
||||
case 'u':
|
||||
match_token( token_unset, "unset" );
|
||||
break;
|
||||
}
|
||||
|
||||
#undef match_token
|
||||
|
||||
if ( token == token_source )
|
||||
{
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
do_source( pnt );
|
||||
return;
|
||||
}
|
||||
|
||||
if ( token == token_then )
|
||||
{
|
||||
if ( config_last != NULL && config_last->token == token_if )
|
||||
return;
|
||||
syntax_error( "bogus 'then'" );
|
||||
}
|
||||
|
||||
#if 0
|
||||
if ( token == token_unset )
|
||||
{
|
||||
fprintf( stderr, "Ignoring 'unset' command\n" );
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
if ( token == token_UNKNOWN )
|
||||
syntax_error( "unknown command" );
|
||||
|
||||
/*
|
||||
* Allocate an item.
|
||||
*/
|
||||
cfg = malloc( sizeof(*cfg) );
|
||||
memset( cfg, 0, sizeof(*cfg) );
|
||||
if ( config_last == NULL )
|
||||
{ config_last = config_list = cfg; }
|
||||
else
|
||||
{ config_last->next = cfg; config_last = cfg; }
|
||||
|
||||
/*
|
||||
* Tokenize the arguments.
|
||||
*/
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
|
||||
cfg->token = token;
|
||||
switch ( token )
|
||||
{
|
||||
default:
|
||||
syntax_error( "unknown token" );
|
||||
|
||||
case token_bool:
|
||||
case token_tristate:
|
||||
pnt = get_qstring ( pnt, &cfg->label );
|
||||
pnt = get_string ( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
break;
|
||||
|
||||
case token_choice_header:
|
||||
{
|
||||
static int choose_number = 0;
|
||||
char * choice_list;
|
||||
|
||||
pnt = get_qstring ( pnt, &cfg->label );
|
||||
pnt = get_qstring ( pnt, &choice_list );
|
||||
pnt = get_string ( pnt, &cfg->value );
|
||||
cfg->nameindex = -(choose_number++);
|
||||
tokenize_choices( cfg, choice_list );
|
||||
free( choice_list );
|
||||
}
|
||||
break;
|
||||
|
||||
case token_comment:
|
||||
pnt = get_qstring(pnt, &cfg->label);
|
||||
if ( last_menuoption != NULL )
|
||||
{
|
||||
pnt = get_qstring(pnt, &cfg->label);
|
||||
if (cfg->label == NULL)
|
||||
syntax_error( "missing comment text" );
|
||||
last_menuoption->label = cfg->label;
|
||||
last_menuoption = NULL;
|
||||
}
|
||||
break;
|
||||
|
||||
case token_define_bool:
|
||||
case token_define_tristate:
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
if ( ( pnt[0] == 'Y' || pnt[0] == 'M' || pnt[0] == 'N'
|
||||
|| pnt[0] == 'y' || pnt[0] == 'm' || pnt[0] == 'n' )
|
||||
&& ( pnt[1] == '\0' || pnt[1] == ' ' || pnt[1] == '\t' ) )
|
||||
{
|
||||
if ( *pnt == 'n' || *pnt == 'N' ) cfg->value = strdup( "CONSTANT_N" );
|
||||
else if ( *pnt == 'y' || *pnt == 'Y' ) cfg->value = strdup( "CONSTANT_Y" );
|
||||
else if ( *pnt == 'm' || *pnt == 'M' ) cfg->value = strdup( "CONSTANT_M" );
|
||||
}
|
||||
else if ( *pnt == '$' )
|
||||
{
|
||||
pnt++;
|
||||
pnt = get_string( pnt, &cfg->value );
|
||||
}
|
||||
else
|
||||
{
|
||||
syntax_error( "unknown define_bool value" );
|
||||
}
|
||||
get_varnum( cfg->value );
|
||||
break;
|
||||
|
||||
case token_define_hex:
|
||||
case token_define_int:
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
pnt = get_string( pnt, &cfg->value );
|
||||
break;
|
||||
|
||||
case token_define_string:
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
pnt = get_qnqstring( pnt, &cfg->value );
|
||||
if (cfg->value == NULL)
|
||||
syntax_error( "missing value" );
|
||||
break;
|
||||
|
||||
case token_dep_bool:
|
||||
case token_dep_mbool:
|
||||
case token_dep_tristate:
|
||||
pnt = get_qstring ( pnt, &cfg->label );
|
||||
pnt = get_string ( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
|
||||
dep_ptr = &(cfg->depend);
|
||||
|
||||
do {
|
||||
*dep_ptr = (struct dependency *) malloc( sizeof( struct dependency ) );
|
||||
(*dep_ptr)->next = NULL;
|
||||
|
||||
if ( ( pnt[0] == 'Y' || pnt[0] == 'M' || pnt[0] == 'N'
|
||||
|| pnt[0] == 'y' || pnt[0] == 'm' || pnt[0] == 'n' )
|
||||
&& ( pnt[1] == '\0' || pnt[1] == ' ' || pnt[1] == '\t' ) )
|
||||
{
|
||||
/* dep_tristate 'foo' CONFIG_FOO m */
|
||||
if ( pnt[0] == 'Y' || pnt[0] == 'y' )
|
||||
(*dep_ptr)->name = strdup( "CONSTANT_Y" );
|
||||
else if ( pnt[0] == 'N' || pnt[0] == 'n' )
|
||||
(*dep_ptr)->name = strdup( "CONSTANT_N" );
|
||||
else
|
||||
(*dep_ptr)->name = strdup( "CONSTANT_M" );
|
||||
pnt++;
|
||||
get_varnum( (*dep_ptr)->name );
|
||||
}
|
||||
else if ( *pnt == '$' )
|
||||
{
|
||||
pnt++;
|
||||
pnt = get_string( pnt, &(*dep_ptr)->name );
|
||||
get_varnum( (*dep_ptr)->name );
|
||||
}
|
||||
else
|
||||
{
|
||||
syntax_error( "can't handle dep_bool/dep_mbool/dep_tristate condition" );
|
||||
}
|
||||
dep_ptr = &(*dep_ptr)->next;
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
} while ( *pnt );
|
||||
|
||||
/*
|
||||
* Create a conditional for this object's dependencies.
|
||||
*/
|
||||
{
|
||||
char fake_if [1024];
|
||||
struct dependency * dep;
|
||||
struct condition ** cond_ptr;
|
||||
int first = 1;
|
||||
|
||||
cond_ptr = &(cfg->cond);
|
||||
for ( dep = cfg->depend; dep; dep = dep->next )
|
||||
{
|
||||
if ( token == token_dep_tristate
|
||||
&& ! strcmp( dep->name, "CONSTANT_M" ) )
|
||||
{
|
||||
continue;
|
||||
}
|
||||
if ( first )
|
||||
{
|
||||
first = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
*cond_ptr = malloc( sizeof(struct condition) );
|
||||
memset( *cond_ptr, 0, sizeof(struct condition) );
|
||||
(*cond_ptr)->op = op_and;
|
||||
cond_ptr = &(*cond_ptr)->next;
|
||||
}
|
||||
*cond_ptr = malloc( sizeof(struct condition) );
|
||||
memset( *cond_ptr, 0, sizeof(struct condition) );
|
||||
(*cond_ptr)->op = op_lparen;
|
||||
if ( token == token_dep_bool )
|
||||
sprintf( fake_if, "[ \"$%s\" = \"y\" -o \"$%s\" = \"\" ]; then",
|
||||
dep->name, dep->name );
|
||||
else
|
||||
sprintf( fake_if, "[ \"$%s\" = \"y\" -o \"$%s\" = \"m\" -o \"$%s\" = \"\" ]; then",
|
||||
dep->name, dep->name, dep->name );
|
||||
(*cond_ptr)->next = tokenize_if( fake_if );
|
||||
while ( *cond_ptr )
|
||||
cond_ptr = &(*cond_ptr)->next;
|
||||
*cond_ptr = malloc( sizeof(struct condition) );
|
||||
memset( *cond_ptr, 0, sizeof(struct condition) );
|
||||
(*cond_ptr)->op = op_rparen;
|
||||
cond_ptr = &(*cond_ptr)->next;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case token_else:
|
||||
case token_endmenu:
|
||||
case token_fi:
|
||||
break;
|
||||
|
||||
case token_hex:
|
||||
case token_int:
|
||||
pnt = get_qstring ( pnt, &cfg->label );
|
||||
pnt = get_string ( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
pnt = get_string ( pnt, &cfg->value );
|
||||
break;
|
||||
|
||||
case token_string:
|
||||
pnt = get_qstring ( pnt, &cfg->label );
|
||||
pnt = get_string ( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
pnt = get_qnqstring ( pnt, &cfg->value );
|
||||
if (cfg->value == NULL)
|
||||
syntax_error( "missing initial value" );
|
||||
break;
|
||||
|
||||
case token_if:
|
||||
cfg->cond = tokenize_if( pnt );
|
||||
break;
|
||||
|
||||
case token_mainmenu_name:
|
||||
pnt = get_qstring( pnt, &cfg->label );
|
||||
break;
|
||||
|
||||
case token_mainmenu_option:
|
||||
if ( strncmp( pnt, "next_comment", 12 ) == 0 )
|
||||
last_menuoption = cfg;
|
||||
else
|
||||
pnt = get_qstring( pnt, &cfg->label );
|
||||
break;
|
||||
|
||||
case token_unset:
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
while (*pnt)
|
||||
{
|
||||
cfg->next = (struct kconfig *) malloc( sizeof(struct kconfig) );
|
||||
memset( cfg->next, 0, sizeof(struct kconfig) );
|
||||
cfg = cfg->next;
|
||||
cfg->token = token_unset;
|
||||
pnt = get_string( pnt, &buffer );
|
||||
cfg->nameindex = get_varnum( buffer );
|
||||
while ( *pnt == ' ' || *pnt == '\t' )
|
||||
pnt++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static char *genv;
|
||||
static char *genv_extra;
|
||||
|
||||
/*
|
||||
* Implement the "source" command.
|
||||
*/
|
||||
static void do_source( const char * filename )
|
||||
{
|
||||
char buffer[2048], buffer2[1024], buffer3[1024];
|
||||
FILE * infile, *hfile, *ofile;
|
||||
const char * old_file;
|
||||
int old_lineno;
|
||||
int offset;
|
||||
static first = 0, first2 = 0, first3 = 0;
|
||||
|
||||
strcpy(buffer, filename);
|
||||
|
||||
/* open the file */
|
||||
if ( strcmp( filename, "-" ) == 0 )
|
||||
infile = stdin;
|
||||
else
|
||||
infile = fopen( filename, "r" );
|
||||
|
||||
/* if that failed, try second argument as path */
|
||||
if (( infile == NULL ) && (genv))
|
||||
{
|
||||
sprintf( buffer, "%s/%s", genv, filename );
|
||||
infile = fopen( buffer, "r" );
|
||||
}
|
||||
|
||||
/* if that failed, try third argument as path */
|
||||
if (( infile == NULL ) && (genv_extra))
|
||||
{
|
||||
sprintf( buffer, "%s/%s", genv_extra, filename );
|
||||
infile = fopen( buffer, "r" );
|
||||
}
|
||||
|
||||
if ( infile == NULL )
|
||||
{
|
||||
sprintf( buffer, "unable to open %s", buffer );
|
||||
syntax_error( buffer );
|
||||
} else {
|
||||
strcpy(buffer2, buffer);
|
||||
strcpy(buffer3, buffer);
|
||||
strcat(buffer, ".h");
|
||||
hfile = fopen( buffer, "r" );
|
||||
if (hfile != NULL) {
|
||||
if (first)
|
||||
ofile = fopen( "tkconfig.h", "a" );
|
||||
else {
|
||||
ofile = fopen( "tkconfig.h", "w" );
|
||||
first = 1;
|
||||
}
|
||||
while (!feof(hfile)) {
|
||||
offset = fread(buffer, 1, 1024, hfile);
|
||||
fwrite(buffer, 1, offset, ofile);
|
||||
}
|
||||
fclose( hfile );
|
||||
fclose( ofile );
|
||||
}
|
||||
strcat(buffer2, ".help");
|
||||
hfile = fopen( buffer2, "r" );
|
||||
if (hfile != NULL) {
|
||||
if (first2)
|
||||
ofile = fopen( "config.help", "a" );
|
||||
else {
|
||||
ofile = fopen( "config.help", "w" );
|
||||
first2 = 1;
|
||||
}
|
||||
while (!feof(hfile)) {
|
||||
offset = fread(buffer, 1, 1024, hfile);
|
||||
fwrite(buffer, 1, offset, ofile);
|
||||
}
|
||||
fclose( hfile );
|
||||
fclose( ofile );
|
||||
}
|
||||
strcat(buffer3, ".vhd");
|
||||
hfile = fopen( buffer3, "r" );
|
||||
if (hfile != NULL) {
|
||||
if (first3)
|
||||
ofile = fopen( "config.vhd.h", "a" );
|
||||
else {
|
||||
ofile = fopen( "config.vhd.h", "w" );
|
||||
first3 = 1;
|
||||
}
|
||||
while (!feof(hfile)) {
|
||||
offset = fread(buffer, 1, 1024, hfile);
|
||||
fwrite(buffer, 1, offset, ofile);
|
||||
}
|
||||
fclose( hfile );
|
||||
fclose( ofile );
|
||||
}
|
||||
}
|
||||
|
||||
/* push the new file name and line number */
|
||||
old_file = current_file;
|
||||
old_lineno = lineno;
|
||||
current_file = filename;
|
||||
lineno = 0;
|
||||
|
||||
/* read and process lines */
|
||||
for ( offset = 0; ; )
|
||||
{
|
||||
char * pnt;
|
||||
|
||||
/* read a line */
|
||||
fgets( buffer + offset, sizeof(buffer) - offset, infile );
|
||||
if ( feof( infile ) )
|
||||
break;
|
||||
lineno++;
|
||||
|
||||
/* strip the trailing return character */
|
||||
pnt = buffer + strlen(buffer) - 1;
|
||||
if ( *pnt == '\n' )
|
||||
*pnt-- = '\0';
|
||||
|
||||
/* eat \ NL pairs */
|
||||
if ( *pnt == '\\' )
|
||||
{
|
||||
offset = pnt - buffer;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* tokenize this line */
|
||||
tokenize_line( buffer );
|
||||
offset = 0;
|
||||
}
|
||||
|
||||
/* that's all, folks */
|
||||
if ( infile != stdin )
|
||||
fclose( infile );
|
||||
current_file = old_file;
|
||||
lineno = old_lineno;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Main program.
|
||||
*/
|
||||
int main( int argc, char * argv [] )
|
||||
{
|
||||
if (argc >= 3) genv = argv[2];
|
||||
if (argc == 4) genv_extra = argv[3];
|
||||
do_source ( argv[1] );
|
||||
fix_conditionals ( config_list );
|
||||
dump_tk_script ( config_list );
|
||||
return 0;
|
||||
}
|
||||
127
bin/tkconfig/tkparse.h
Normal file
127
bin/tkconfig/tkparse.h
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* tkparse.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* Token types (mostly statement types).
|
||||
*/
|
||||
|
||||
enum e_token
|
||||
{
|
||||
token_UNKNOWN,
|
||||
token_bool,
|
||||
token_choice_header,
|
||||
token_choice_item,
|
||||
token_comment,
|
||||
token_define_bool,
|
||||
token_define_hex,
|
||||
token_define_int,
|
||||
token_define_string,
|
||||
token_define_tristate,
|
||||
token_dep_bool,
|
||||
token_dep_mbool,
|
||||
token_dep_tristate,
|
||||
token_else,
|
||||
token_endmenu,
|
||||
token_fi,
|
||||
token_hex,
|
||||
token_if,
|
||||
token_int,
|
||||
token_mainmenu_name,
|
||||
token_mainmenu_option,
|
||||
token_source,
|
||||
token_string,
|
||||
token_then,
|
||||
token_tristate,
|
||||
token_unset,
|
||||
};
|
||||
|
||||
/*
|
||||
* Operator types for conditionals.
|
||||
*/
|
||||
|
||||
enum operator
|
||||
{
|
||||
op_eq,
|
||||
op_neq,
|
||||
op_and,
|
||||
op_and1,
|
||||
op_or,
|
||||
op_bang,
|
||||
op_lparen,
|
||||
op_rparen,
|
||||
op_constant,
|
||||
op_variable,
|
||||
op_true,
|
||||
op_false,
|
||||
op_nuked
|
||||
};
|
||||
|
||||
/*
|
||||
* Conditions come in linked lists.
|
||||
* Some operators take strings:
|
||||
*
|
||||
* op_constant "foo"
|
||||
* op_variable "$ARCH", "$CONFIG_PMAC", "$CONFIG_EXPERIMENTAL"
|
||||
*
|
||||
* Most "$..." constructs refer to a variable which is defined somewhere
|
||||
* in the script. Note that it is legal to test variables which are never
|
||||
* defined, such as variables that are meaningful only on other architectures.
|
||||
*/
|
||||
|
||||
struct condition
|
||||
{
|
||||
struct condition * next;
|
||||
enum operator op;
|
||||
const char * str; /* op_constant */
|
||||
int nameindex; /* op_variable */
|
||||
};
|
||||
|
||||
/*
|
||||
* Dependency list for dep_bool, dep_mbool, dep_tristate
|
||||
*/
|
||||
|
||||
struct dependency
|
||||
{
|
||||
char * name;
|
||||
struct dependency * next;
|
||||
};
|
||||
|
||||
/*
|
||||
* A statement from a config.in file
|
||||
*/
|
||||
|
||||
struct kconfig
|
||||
{
|
||||
struct kconfig * next;
|
||||
enum e_token token;
|
||||
int nameindex;
|
||||
char * label;
|
||||
char * value;
|
||||
struct condition * cond;
|
||||
struct dependency * depend; /* token_dep_tristate */
|
||||
struct kconfig * cfg_parent; /* token_choice_item */
|
||||
|
||||
/* used only in tkgen.c */
|
||||
int menu_number;
|
||||
int menu_line;
|
||||
struct kconfig * menu_next;
|
||||
};
|
||||
|
||||
struct variable
|
||||
{
|
||||
char * name;
|
||||
char defined;
|
||||
char global_written;
|
||||
};
|
||||
|
||||
extern struct variable vartable[];
|
||||
extern int max_varnum;
|
||||
|
||||
/*
|
||||
* Prototypes
|
||||
*/
|
||||
|
||||
extern void fix_conditionals ( struct kconfig * scfg ); /* tkcond.c */
|
||||
extern void dump_tk_script ( struct kconfig * scfg ); /* tkgen.c */
|
||||
extern int get_varnum ( char * name ); /* tkparse.c */
|
||||
12
bin/top.dc
Normal file
12
bin/top.dc
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
catch {sh mkdir synopsys}
|
||||
set objects synopsys
|
||||
#set trans_dc_max_depth 1
|
||||
#set hdlin_seqmap_sync_search_depth 1
|
||||
#set hdlin_nba_rewrite false
|
||||
set hdlin_ff_always_sync_set_reset true
|
||||
set hdlin_ff_always_async_set_reset false
|
||||
#set hdlin_infer_complex_set_reset true
|
||||
#set hdlin_translate_off_skip_text true
|
||||
set suppress_errors VHDL-2285
|
||||
#set hdlin_use_carry_in true
|
||||
source compile.dc
|
||||
3
bin/top.rc
Normal file
3
bin/top.rc
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
set_attribute input_pragma_keyword "cadence synopsys get2chip g2c fast ambit pragma"
|
||||
include compile.rc
|
||||
|
||||
1
bin/wish
Executable file
1
bin/wish
Executable file
|
|
@ -0,0 +1 @@
|
|||
wish84.exe "$@"
|
||||
1194
bin/xgrlib.tcl
Executable file
1194
bin/xgrlib.tcl
Executable file
File diff suppressed because it is too large
Load diff
4
bin/xstmod
Executable file
4
bin/xstmod
Executable file
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh
|
||||
# runxst top_entity file device vhdl|verilog
|
||||
echo run -top $1 -ifn $2 -ifmt $4 -p $3 -ofn $1 -iobuf no -bus_delimiter "()"
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue